Write operation circuit and memory

Abstract

The application provides a write operation circuit and a memory. The write operation circuit comprises a target unit to be written with data, a first write circuit for writing "0" and a second write circuit for writing "1". The first write circuit comprises a first write driving unit for performing multiple write "0" operations on the target unit according to a write "0" driving signal in one write cycle, a first voltage comparator for verifying whether the write "0" is successful, and a first logic unit for outputting the write "0" driving signal. The second write circuit comprises a second write driving unit for performing multiple write "1" operations on the target unit according to a write "1" driving signal in one write cycle, a second voltage comparator for verifying whether the write "1" is successful, and a second logic unit for outputting the write "1" driving signal.

Description

Technical Field

[0001] This invention relates to the field of memory design technology, and in particular to a write operation circuit and a memory. Background Technology

[0002] Given the current immaturity of MRAM manufacturing processes, the slight deviations between cells, and the varying parasitic resistances of arrays accessed at different locations, the actual write voltage required for each cell in the array is inconsistent. During write operations, typically only the most difficult cell to write is considered. When this most difficult cell can be written, the write voltage for the remaining cells actually exceeds the required write voltage, causing the number of erasable and rewrite cycles of the target cell to decrease exponentially, resulting in poor chip durability.

[0003] To address the aforementioned issues, a write-verify-write (W-Verify-Rewrite) technique is introduced. This technique first uses a low voltage for writing, and then performs a read operation after the write operation is complete. If data has been written, the write operation is finished; otherwise, the write voltage is increased to perform a second write operation, and so on, until the array is completely written. Because this technique uses a suitable voltage for writing to the array, it prevents the chip's durability from deteriorating due to excessively high write voltage.

[0004] In the process of realizing this invention, the inventors discovered at least the following technical problems in the prior art:

[0005] In the existing write-verify-write technology, a read operation is required on the array after each write operation to verify whether the write was successful. Considering the need for multiple write operations, a single write cycle actually consists of several sets of write and read operations, which makes the write time particularly long, reduces the chip's operating frequency, and makes the write speed very slow. Summary of the Invention

[0006] To address the aforementioned problems, this invention provides a write operation circuit and a memory that can shorten the write cycle and increase the write speed without reducing chip durability.

[0007] On one hand, the present invention provides a write operation circuit, comprising:

[0008] The system includes a target cell for writing data, a first write circuit for writing "0" to the target cell, and a second write circuit for writing "1".

[0009] The first write circuit includes:

[0010] The first write driver unit has an input terminal that receives a write "0" drive signal and an output terminal that is connected to the bit line of the target unit. It is used to perform multiple write "0" operations on the target unit according to the write "0" drive signal within one write cycle.

[0011] The first voltage comparator takes the bit line voltage and the first reference voltage as inputs and is used to verify whether writing "0" was successful by comparing the bit line voltage and the first reference voltage.

[0012] The first logic unit is configured to output the write "0" drive signal based on the comparison result of the first voltage comparator.

[0013] The second write circuit includes:

[0014] The second write drive unit receives a write "1" drive signal at its input terminal and connects its output terminal to the source line of the target unit. It is used to perform multiple write "1" operations on the target unit according to the write "1" drive signal within one write cycle.

[0015] The second voltage comparator takes the source line voltage and the second reference voltage as inputs and is used to verify whether writing "1" was successful by comparing the source line voltage and the second reference voltage.

[0016] The second logic unit is used to output the write "1" drive signal based on the comparison result of the second voltage comparator.

[0017] Optionally, the bit line voltage is input to the inverting input terminal of the first voltage comparator, and the first reference voltage is input to the non-inverting input terminal;

[0018] The second reference voltage is input to the inverting input terminal of the second voltage comparator, and the source line voltage is input to the non-inverting input terminal.

[0019] Optionally, the first reference voltage is taken as the midpoint of the target cell bit line voltage before and after writing "0";

[0020] The second reference voltage is the midpoint between the source line voltage of the target unit before and after writing "1".

[0021] Optionally, the first logic unit includes:

[0022] The first AND gate has one input terminal connected to the output terminal of the first voltage comparator to input the comparison result of the first voltage comparator, and the other input terminal inputting the clock signal;

[0023] The first latch has a set terminal connected to the output terminal of the first AND gate, and a reset terminal that receives a write cycle signal and outputs a write "0" complete signal.

[0024] The first NOT gate, whose input is connected to the output of the first latch, inverts the write "0" completion signal;

[0025] The second AND gate has one input terminal receiving a write "0" enable signal and the other input terminal connected to the output terminal of the first NOT gate, outputting a write "0" drive signal.

[0026] Optionally, the second logic unit includes:

[0027] The third AND gate has one input terminal connected to the output terminal of the second voltage comparator to input the comparison result of the second voltage comparator, and the other input terminal inputting the clock signal;

[0028] The second latch has its set terminal connected to the output terminal of the third AND gate, and its reset terminal receives a write cycle signal and outputs a write "1" completion signal.

[0029] The second NOT gate, whose input is connected to the output of the second latch, inverts the write "1" completion signal;

[0030] The fourth AND gate has one input terminal receiving a write "1" enable signal and the other input terminal connected to the output terminal of the second NOT gate, outputting a write "1" drive signal.

[0031] Optionally, when the write "0" drive signal is high, the first write drive unit performs a write "0" operation;

[0032] When the write "0" drive signal is low, the first write drive unit stops writing "0" operation;

[0033] When the write "1" drive signal is high, the second write drive unit performs a write "1" operation;

[0034] When the write "1" drive signal is low, the second write drive unit stops writing "1" operation.

[0035] Optionally, the first write circuit further includes a first transistor for keeping the source line of the target cell connected to the ground line when writing "0".

[0036] Optionally, the second write circuit further includes a second transistor for keeping the bit line of the target cell connected to the ground line when writing a "1".

[0037] Optionally, the target unit includes a magnetic tunnel junction and a gate transistor, wherein the free layer side of the magnetic tunnel junction is connected to the bit line, and the reference layer side of the magnetic tunnel junction is connected to the source line.

[0038] On the other hand, the present invention provides a memory including the above-described write operation circuit.

[0039] This invention provides a write operation circuit and memory that eliminates the need for read operations after data is written. A comparator amplifier determines whether the write operation to the memory cell was successful, and logic circuitry controls the write drive circuit. Once a write operation is successful, no further write operations are performed. This eliminates the need for read operations after each write operation while ensuring chip durability, shortening the write cycle and increasing write speed. This invention achieves this function through a combination of a voltage comparator and logic circuitry. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the circuit structure of a write operation circuit according to an embodiment of the present invention;

[0041] Figure 2 This is the timing function diagram of the voltage comparator;

[0042] Figure 3 This is a schematic diagram showing the voltage change of BL when writing "0";

[0043] Figure 4 This is a schematic diagram showing the voltage change of SL when writing "1";

[0044] Figure 5 A simplified circuit diagram illustrating the process of writing "0";

[0045] Figure 6 The timing function diagram for writing the "0" operation. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0048] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0049] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0050] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0051] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0052] One embodiment of the present invention provides a write operation circuit, such as... Figure 1 As shown, the write operation circuit includes a target unit 100 for writing data, a first write circuit for writing "0" to the target unit, and a second write circuit for writing "1" to the target unit.

[0053] The first write circuit includes a first write drive unit 111, a first voltage comparator 112, and a first logic unit. In this embodiment, the first write drive unit 111 receives a write "0" drive signal Write AP2P at its input terminal and its output terminal is connected to the bit line of the target unit 100. It is used to perform multiple write "0" operations on the target unit within one write cycle based on the write "0" drive signal. The control effect of the write "0" drive signal on the first write drive unit is as follows:

[0054] When the write "0" drive signal is high, the first write drive unit performs a write "0" operation;

[0055] When the write "0" drive signal is low, the first write drive unit stops writing "0".

[0056] If the previous write operation to "0" failed, the write voltage increases sequentially with each write operation. The first voltage comparator 112 takes the bit line voltage VBL and the first reference voltage VREF_AP2P as inputs and verifies whether the write operation to "0" was successful by comparing the bit line voltage and the first reference voltage. The first logic unit outputs the write drive signal Write AP2P based on the comparison result of the first voltage comparator 112.

[0057] The second write circuit includes a second write driver unit 121, a second voltage comparator 122, and a second logic unit. In this embodiment, the second write driver unit 121 receives a write "1" drive signal Write P2AP at its input terminal and its output terminal is connected to the source line of the target unit 100. It is used to perform multiple write "1" operations on the target unit within one write cycle based on the write "1" drive signal. The control effect of the write "1" drive signal on the second write driver unit is as follows:

[0058] When the write "1" drive signal is high, the second write drive unit performs a write "1" operation;

[0059] When the write "1" drive signal is low, the second write drive unit stops writing "1".

[0060] If the previous write operation to "1" failed, the write voltage increases sequentially with each write operation. Whether a write operation to "1" is performed is controlled by the write drive signal. The second voltage comparator 122 takes the source line voltage VSL and the second reference voltage VREF_P2AP as inputs and verifies whether the write operation to "1" was successful by comparing the source line voltage and the second reference voltage. The second logic unit outputs the write drive signal WriteP2AP based on the comparison result of the second voltage comparator 122.

[0061] Further, refer to Figure 1 The first write circuit also includes a first transistor M1, used to keep the source line of the target cell connected to the ground line when writing "0". The second write circuit also includes a second transistor M2, used to keep the bit line of the target cell connected to the ground line when writing "1".

[0062] In one implementation, the target cell can be an MRAM cell, including a magnetic tunnel junction and a gate transistor, wherein the free layer side of the magnetic tunnel junction is connected to the bit line, and the reference layer side of the magnetic tunnel junction is connected to the source line. However, it should be noted that the target cell type is not limited to an MRAM cell, and can be any type of memory cell whose state can be distinguished by resistance changes, such as a resistive random access memory (RRAM) cell.

[0063] This embodiment of the invention uses a voltage comparator to verify whether the write operation was successful. The voltage comparator operates as follows: Figure 2 As shown:

[0064] The voltage comparator is a four-port device. COMPARE_EN is the enable switch, and terminals A and B are the comparison voltage inputs. A is the inverting input, and B is the non-inverting input. No current flows into the comparator during normal operation. COMPARE_OUT is the output terminal. The voltage comparator can continuously compare the voltages across terminals A and B while COMPARE_EN is high, until COMPARE_EN is pulled low.

[0065] If the voltage at terminal A is higher than the voltage at terminal B, the output COMPARE_OUT is 0; if the voltage at terminal A is lower than the voltage at terminal B, the output COMPARE_OUT is 1.

[0066] When a voltage change occurs during the comparison process, COMPARE_OUT requires a T_SENSING time to output. (Refer to...) Figure 2 When the voltage at terminal A is lower than the voltage at terminal B, the output signal COMPARE_OUT goes high after a time interval of T_SENSING. Ideally, T_SENSING should be 0. In actual circuits, this time depends on the size of the MOSFET in the voltage comparator and the magnitude of the comparison voltage. It can be adjusted according to the actual situation to make T_SENSING smaller.

[0067] In this embodiment, the bit line voltage is input to the inverting input terminal (A terminal) of the first voltage comparator, and the first reference voltage is input to the non-inverting input terminal (B terminal). The second reference voltage is input to the inverting input terminal (A terminal) of the second voltage comparator, and the source line voltage is input to the non-inverting input terminal (B terminal). When the output terminal COMPARE_OUT of the first / second voltage comparator is low, it indicates that the write operation has failed. When the output terminal COMPARE_OUT is high, it indicates that the write operation has succeeded.

[0068] Since the MTJ resistor flips after a successful write operation, its resistance value changes drastically. The MTJ has a smaller resistance in the parallel state (P state) and a larger resistance in the anti-parallel state (AP state). Therefore, the flipping characteristic of the MTJ is used to verify whether the write operation was successful.

[0069] When the MTJ resistor changes, the voltage across BL / SL changes due to the change in resistance across the entire branch. For example, when MTJ flips from the AP state to the P state (which can be denoted as AP2P, i.e., writing "0"), the MTJ resistance suddenly decreases, and the voltage across BL decreases due to the change in MTJ voltage divider. If a reference voltage is used, its value is the midpoint between the BL voltage before and after the flip, and it can be raised according to the write voltage adjustment. Therefore, the relationship between the voltage across BL and the reference voltage can be used to determine whether writing "0" was successful. Figure 3 The diagram shows the voltage change of BL when writing "0".

[0070] For example, when MTJ flips from the P state to the AP state (which can be denoted as P2AP, i.e., writing "1"), the resistance of MTJ suddenly increases. The voltage on SL will increase due to the change in the voltage divider of MTJ. If a reference voltage is used at this time, its value is the midpoint between the voltage on SL before and after the flip, and it can be raised according to the write voltage adjustment. Therefore, the relationship between the voltage on SL and the reference voltage can be used to determine whether "1" has been successfully written. Figure 4 The diagram shows the voltage change of SL when writing "1".

[0071] Further reference Figure 1 , Figure 1 An implementation of the first and second logic units is given. The first logic unit includes a first AND gate 113, a first latch 114, a first NOT gate 115, and a second AND gate 116.

[0072] One input of the first AND gate 113 is connected to the output of the first voltage comparator 112, and the comparison result COMPARE_OUT0 of the first voltage comparator is input. The other input is the clock signal CLK_IN.

[0073] The set terminal of the first latch 114 is connected to the output terminal of the first AND gate 113. The reset terminal receives the write cycle signal CLK_WRITE and outputs the write "0" completion signal WRITE_AP2P_FINISH.

[0074] The input of the first NOT gate 115 is connected to the output of the first latch 114 to invert the write "0" completion signal.

[0075] One input of the second AND gate 116 receives the Write AP2P_EN enable signal, and the other input is connected to the output of the first NOT gate, outputting the Write AP2P drive signal.

[0076] The second logic unit includes a third AND gate 123, a second latch 124, a second NOT gate 125, and a fourth AND gate 126.

[0077] One input of the third AND gate 123 is connected to the output of the second voltage comparator 122, and the comparison result COMPARE_OUT1 of the second voltage comparator is input. The other input is the clock signal CLK_IN.

[0078] The set terminal of the second latch 124 is connected to the output terminal of the third AND gate 123. The reset terminal inputs the write cycle signal CLK_WRITE and outputs the write "1" completion signal WRITE_P2AP_FINISH.

[0079] The input of the second NOT gate 125 is connected to the output of the second latch 124 to invert the write "1" completion signal.

[0080] The fourth AND gate 126 has one input terminal receiving the write "1" enable signal Write P2AP_EN, and the other input terminal connected to the output terminal of the second NOT gate 125, which outputs the write "1" drive signal Write P2AP.

[0081] Figure 1 The logic circuit shown is only an example, and there are other implementations. It can generate a drive signal for any comparison result of the voltage comparator, and use the drive signal to implement the circuit structure that controls the write operation of the write drive unit.

[0082] This invention provides a write operation circuit that, during a write operation, determines whether the target cell has been successfully written by comparing a reference voltage with the voltage on SL / BL. When the target cell MTJ flips, the comparison voltage momentarily drops below the reference voltage due to the resistor's switching, causing COMPARE_OUT to go high and be latched by a latch. When the write completion signal is high, it indicates that the array has completed the write operation, and subsequent write operations will not be performed until the entire write cycle is completed. At the start of the next write cycle, the latch is reset by the write cycle signal clk_write, and the write completion signal is then set back to 0. Compared with the prior art, the write operation circuit of this invention can use a suitable write voltage to write to different MTJ cells, and can verify whether the write is successful without a read operation, shortening the entire cycle and achieving faster write speed while ensuring device tolerance.

[0083] Specifically, taking the AP2P writing of "0" as an example, the workflow of the write operation circuit in this embodiment of the invention is explained. At this time, only the first write circuit is working. Figure 1 The circuit can be simplified to Figure 5The format is as follows. Assume the first write driver unit can perform three write operations within one write cycle. The first write operation has the lowest voltage, ensuring most cells are written. The second operation has a slightly higher voltage, capable of writing the remaining cells that were not fully written in the first operation and require a higher voltage. The third operation has the highest voltage, used to write the individual cells that are more difficult to write. Assuming the second write operation is successful, the specific process is as follows:

[0084] When a write operation is performed, an external write cycle signal CLK_WRITE is input to initiate the write operation. On the rising edge of CLK_WRITE, the latch is reset, pulling the write completion signal WRITE_AP2P_FINISH low. After passing through an inverter, the write drive signal WRITE_AP2P input to the first write drive unit is high, and the first write operation is performed. The write voltage output by the write drive unit is WRITE_VOLTAGE1. After comparison by a voltage comparator, it is found that the MTJ voltage does not change, and the COMPARE_OUT0 output is low, indicating that the first write operation failed.

[0085] At this point, the second write operation begins, raising the write voltage to WRITE_VOLTAGE2. A voltage comparator is used in the same write operation for voltage comparison, and a voltage jump is detected. COMPARE_OUT0 outputs a high level, indicating that the second write operation was successful. The latch set pin is now high, thus the write completion signal WRITE_AP2P_FINISH is pulled high. Since WRITE_AP2P_FINISH is high, after passing through an inverter and an AND gate, the write "0" drive signal WRITE_AP2P is made low.

[0086] Because of the latching function, WRITE_AP2P_FINISH will not be set to 0 until the rising edge of CLK_WRITE in the next write cycle, so as to ensure that no write operation after this write operation (i.e., the third write operation) will be performed in this write cycle. Figure 6 The diagram shows the write voltage, the voltage on the MTJ, and the timing relationship of the voltage comparator output level corresponding to the above process.

[0087] The process of writing "1" in P2AP is similar to the process described above, and will not be elaborated further.

[0088] On the other hand, another embodiment of the present invention also provides a memory that includes the above-described write operation circuit and has the same technical effect.

[0089] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A write operation circuit, characterized in that, include: The system includes a target cell for writing data, a first write circuit for writing "0" to the target cell, and a second write circuit for writing "1". The first write circuit includes: The first write driver unit has an input terminal that receives a write "0" drive signal and an output terminal that is connected to the bit line of the target unit. It is used to perform multiple write "0" operations on the target unit according to the write "0" drive signal within one write cycle. The first voltage comparator takes the bit line voltage and the first reference voltage as inputs and is used to verify whether writing "0" was successful by comparing the bit line voltage and the first reference voltage. A first logic unit is configured to output a write "0" drive signal based on the comparison result of the first voltage comparator. The first logic unit includes a first AND gate, a first latch, a first NOT gate, and a second AND gate. One input of the first AND gate is connected to the output of the first voltage comparator to receive the comparison result of the first voltage comparator. The other input of the first AND gate receives a clock signal. The set input of the first latch is connected to the output of the first AND gate. The reset input of the first latch receives a write cycle signal and outputs a write "0" completion signal. The input of the first NOT gate is connected to the output of the first latch to invert the write "0" completion signal. One input of the second AND gate receives a write "0" enable signal, and the other input is connected to the output of the first NOT gate. The second AND gate outputs a write "0" drive signal. The second write circuit includes: The second write drive unit has an input terminal that receives a write "1" drive signal and an output terminal that is connected to the source line of the target unit. It is used to perform multiple write "1" operations on the target unit according to the write "1" drive signal within one write cycle. The second voltage comparator takes the source line voltage and the second reference voltage as inputs and is used to verify whether writing "1" was successful by comparing the source line voltage and the second reference voltage. The second logic unit is used to output the write "1" drive signal according to the comparison result of the second voltage comparator. The second logic unit includes a third AND gate, a second latch, a second NOT gate, and a fourth AND gate. One input of the third AND gate is connected to the output of the second voltage comparator to input the comparison result of the second voltage comparator. The other input of the third AND gate is a clock signal. The set terminal of the second latch is connected to the output of the third AND gate. The reset terminal of the second latch is a write cycle signal input and outputs a write "1" completion signal. The input of the second NOT gate is connected to the output of the second latch to invert the write "1" completion signal. One input of the fourth AND gate is a write "1" enable signal input, and the other input is connected to the output of the second NOT gate. The fourth AND gate outputs the write "1" drive signal.

2. The write operation circuit according to claim 1, characterized in that, The bit line voltage is input to the inverting input terminal of the first voltage comparator, and the first reference voltage is input to the non-inverting input terminal. The second reference voltage is input to the inverting input terminal of the second voltage comparator, and the source line voltage is input to the non-inverting input terminal.

3. The write operation circuit according to claim 2, characterized in that, The first reference voltage is taken as the midpoint of the target cell bit line voltage before and after writing "0"; The second reference voltage is the midpoint between the source line voltage of the target unit before and after writing "1".

4. The write operation circuit according to claim 1, characterized in that, When the write "0" drive signal is high, the first write drive unit performs a write "0" operation; When the write "0" drive signal is low, the first write drive unit stops writing "0" operation; When the write "1" drive signal is high, the second write drive unit performs a write "1" operation; When the write "1" drive signal is low, the second write drive unit stops writing "1" operation.

5. The write operation circuit according to claim 1, characterized in that, The first write circuit further includes a first transistor for keeping the source line of the target cell connected to the ground line when writing "0".

6. The write operation circuit according to claim 1, characterized in that, The second write circuit also includes a second transistor for keeping the bit line of the target cell connected to ground when writing a "1".

7. The write operation circuit according to claim 1, characterized in that, The target unit includes a magnetic tunnel junction and a gate transistor, wherein the free layer side of the magnetic tunnel junction is connected to the bit line, and the reference layer side of the magnetic tunnel junction is connected to the source line.

8. A memory, characterized in that, The memory includes a write operation circuit as described in any one of claims 1-7.

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