Common-source double-ring gate p-type gallium nitride enhancement-mode device and preparation method thereof

Abstract

The application discloses a common-source double-ring gate P-type gallium nitride enhancement-mode device and a preparation method thereof. The preparation method comprises the following steps: GaN epitaxial growth; device isolation; growth of SiO2 protection active area mesa; etching of a source-drain region of the device structure; sputtering of a source-drain electrode, annealing to form an ohmic contact; sputtering of a ring gate electrode to form a Schottky contact; etching to form electrical isolation; growth of a SiO2 passivation layer; and opening. The application improves the threshold voltage and the breakdown voltage of the device, reduces the current collapse effect, the edge effect and the on-resistance, improves the gate control ability, the current driving ability, the subthreshold slope and the switching current ratio, effectively suppresses the reverse leakage current, reduces the dynamic Ron / static Ron ratio, and realizes better dynamic characteristics.

Description

Technical Field

[0001] This invention relates to the field of semiconductor microelectronics, specifically to a common-source dual-ring gate P-type gallium nitride enhancement-mode device and its fabrication method. Background Technology

[0002] Due to the advantages of GaN materials such as chemical stability, high electron mobility, high temperature resistance, and high breakdown voltage, GaN HEMT devices have been widely used in the field of integrated circuits, especially in the field of high-frequency power circuits in recent years.

[0003] Currently, GaN HEMT devices often employ AlGaN / GaN heterojunction structures. Increasing the Al content in the AlGaN / GaN heterojunction can effectively increase the concentration of 2DEG, thereby improving the device's output current. However, with increasing Al content, the crystal quality of the AlGaN barrier layer deteriorates, and the surface morphology also worsens, leading to leakage current. Using a GaN / AlGaN heterostructure offers higher electron mobility and higher output current. However, current GaN / AlGaN HEMT devices often employ planar structures, resulting in poor gate control. Gate leakage severely affects the device's turn-off capability, consequently degrading device reliability and electrical characteristics.

[0004] Compared to dual-gate and triple-gate structures, the toroidal gate has the largest contact area between the gate and the channel, effectively suppressing the effects of short-channel effects. Therefore, designing and optimizing novel toroidal gate devices can maximize gate control capabilities and reduce the impact of short-channel effects. Only by achieving device performance that meets the requirements of integrated circuits while scaling device feature sizes can the speed of information transmission and the performance of electronic products be improved. Therefore, designing and optimizing novel toroidal gate devices is of great significance to the development of the semiconductor industry. Summary of the Invention

[0005] To address the aforementioned technical shortcomings, the present invention aims to provide a common-source dual-ring-gate P-type gallium nitride (GaN) enhancement-mode device and its fabrication method. This method improves the structure of traditional ring-gate GaN HEMT devices by designing a dual-ring-gate structure, increasing the contact area between the gate and the channel, and solving the problem of decreased gate control capability. This improves subthreshold characteristics such as current drive capability, subthreshold slope, and switching current ratio, thereby enhancing the device's switching performance. Simultaneously, the on-resistance of the device is reduced, and ohmic contact performance is improved.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0007] A method for fabricating a common-source dual-ring gate p-type gallium nitride enhancement-mode device, characterized in that,

[0008] Step 1: Fabricating the wafer for the device: An AlGaN buffer layer (202), a GaN channel layer (203), an AlGaN barrier layer (204), a GaN cap layer (205), and a P-GaN layer (206) are sequentially grown on a Si substrate (201) to generate a P-GaN HEMT epitaxial structure.

[0009] Step 2: Cleaning the epitaxial wafer: Use acetone, ethanol, and dilute hydrochloric acid solution to remove impurities. First, treat organic matter with acetone and ethanol, then use dilute hydrochloric acid to remove inorganic matter. Ultrasonic assistance is used during the cleaning process. Finally, rinse with deionized water and dry with nitrogen.

[0010] Step 3, Device Isolation: Place the cleaned epitaxial wafer in a 100℃ wafer dryer and dry for 5 minutes; then perform photolithography. After photolithography, hard film is applied. Part of the P-GaN (206) area is masked with photoresist, and then etched using plasma inductively coupled etching (ICP) process. Vertically remove P-GaN (206), GaN cap layer (205), AlGaN barrier layer (204), and the upper part of GaN channel layer (203); the etching depth is 400nm, so that the etching depth is below the two-dimensional electron gas. Then, use acetone to clean the photoresist.

[0011] Step 4: Growing SiO2 to protect the mesa: After cleaning the device after the plasma inductively coupled etching process, perform a second photolithography, cover the active area with photoresist, grow 200nm SiO2 using inductively coupled plasma chemical vapor deposition, and then put it into the stripping solution for stripping to remove the SiO2 in the active area and expose the active area, retaining the SiO2 at the channel and the edge of the active area (112).

[0012] Step 5: Perform P-GaN etching: Perform photolithography on the device, cover part of the P-GaN (206) with photoresist, and then use plasma inductive coupling etching technology to etch to a depth of 100nm, that is, remove part of the P-GaN, leaving only the P-GaN below the gate and the part of the P-GaN below the drain; then clean the photoresist.

[0013] Step 6: Isolate between electrodes: Perform photolithography on the device and perform ICP etching on (113) of the device to a depth of 400nm, so that the etching depth is below the two-dimensional electron gas.

[0014] Step 7: Sputtering source and drain electrodes: Perform photolithography on the device, and then sputter metal electrodes on the grooves (103) etched at the source electrode and the grooves (106) etched at the drain electrode in the region after P-GaN etching, wherein the drain electrode encapsulates part of the P-GaN.

[0015] Step 8: Perform rapid thermal annealing: Place the device in a rapid annealing furnace for rapid thermal annealing, so that the source metal (101) and drain metal form ohmic contacts with the AlGaN barrier layer (204).

[0016] Step 9, Growing the gate electrode: The device is subjected to photolithography to deposit the gate metal on the double-ring P-GaN(206) formed after ICP etching;

[0017] Step 10: Passivation: A Si3N4(207) passivation layer is grown using plasma-enhanced chemical vapor deposition.

[0018] Step 11, Opening: The device is opened to expose the source electrode (101) and gate electrode (114) to form the final product.

[0019] The present invention also relates to an enhanced gallium nitride high electron mobility transistor device prepared by the above method.

[0020] The beneficial effects of this invention are: 1. Improved current output characteristics:

[0021] Traditional GaN devices use strip-shaped gate electrodes, while the device described in this invention uses a ring-shaped gate electrode. Because its ring structure has no ends, it avoids the edge effects of conventional strip-shaped gates, thus improving the breakdown voltage. Furthermore, due to its ring structure, the ring-shaped gate has a significantly larger gate width compared to a conventional strip-shaped gate device of the same size, allowing for a larger output current.

[0022] 2. Increased breakdown voltage:

[0023] In traditional GaN-based HEMTs, a depletion region forms below the gate electrode towards the drain, resulting in a relatively high electric field on the drain side of the gate electrode. A ring structure can alleviate this high electric field, increasing the average breakdown electric field between the gate and drain, thereby improving the device's breakdown voltage.

[0024] 3. Improved gate control capability:

[0025] Feature size scaling in traditional semiconductor devices is limited by various factors, including device structure and performance. The device described in this invention features a dual-ring gate electrode, effectively mitigating the problem of significantly reduced gate control over the channel caused by feature size scaling.

[0026] 4. Reduced on-resistance:

[0027] When the gate and drain voltages exceed the threshold voltage, holes in the p-GaN drain begin to inject into the channel, suppressing the sharp electric field formed on the drain side. Therefore, the hybrid p-GaN ohmic drain can effectively suppress current collapse and reduce the dynamic on-resistance Ron.

[0028] 5. Increased reverse blocking voltage:

[0029] With zero bias at the gate and drain, the 2DEG channel beneath the p-GaN gate and drain regions is completely depleted by the p-GaN layer. When the gate and drain voltages are greater than the threshold voltage (Vth) but less than the built-in potential (VF) of the pn junction in the hybrid ohmic drain, a 2DEG forms in the channel beneath the p-GaN gate and drain regions. At this point, channel electrons can easily flow from the source to the ohmic drain. As the gate and drain voltages increase, holes in the p-GaN gate and drain begin to inject into the channel, further increasing the drain current. Conversely, when the drain is negatively biased and the gate is on, the reverse-biased pn junction in the hybrid p-GaN ohmic drain forms a wide depletion region in the channel, resulting in a large reverse blocking voltage. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 A top view of the enhanced gallium nitride high electron mobility transistor device provided by the present invention;

[0032] Figure 2 A cross-sectional view of the enhanced gallium nitride high electron mobility transistor device provided by the present invention;

[0033] Figure 3 A schematic diagram of the epitaxial structure of the enhanced gallium nitride high electron mobility transistor device provided by the present invention;

[0034] Figure 4 A schematic diagram of step 3 in the fabrication method of the enhanced gallium nitride high electron mobility transistor device provided by the present invention;

[0035] Figure 5 A schematic diagram of step 4 in the fabrication method of the enhanced gallium nitride high electron mobility transistor device provided by the present invention;

[0036] Figure 6 A schematic diagram of step 5 in the fabrication method of the enhanced gallium nitride high electron mobility transistor device provided by the present invention;

[0037] Figure 7 A schematic diagram of step 7 in the method for fabricating the enhanced gallium nitride high electron mobility transistor device provided by the present invention;

[0038] Figure 8 A schematic diagram of step 9 in the method for fabricating the enhanced gallium nitride high electron mobility transistor device provided by the present invention;

[0039] Figure 9 A schematic diagram of step 10 in the fabrication method of the enhanced gallium nitride high electron mobility transistor device provided by the present invention;

[0040] Figure 10 A schematic diagram of the electrical isolation steps for the enhanced gallium nitride high electron mobility transistor device provided by the present invention;

[0041] Figure 11 A schematic diagram of the electrical isolation steps for the enhanced gallium nitride high electron mobility transistor device provided by the present invention.

[0042] Explanation of reference numerals in the attached figures:

[0043] 101. Source aperture region; 102. Source electrode; 103. Trench etched at the source electrode; 104. Sputtered internal drain electrode; 105. Internal drain electrode; 106. Trench etched at the drain electrode; 107. Remaining P-GaN under the gate after etching; 108. Ring-shaped external gate electrode; 109. Ring-shaped internal gate electrode; 110. Square drain aperture region; 111. External drain electrode; 112. SiO2 protective layer; 113. Electrical isolation; 114. Gate aperture region; 201. Si substrate; 202. AlGaN buffer layer; 203. GaN channel layer; 204. AlGaN barrier layer; 205. GaN cap layer; 206. P-GaN layer; 207. Si3N4 passivation layer. Detailed Implementation

[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] Example 1

[0046] The fabrication method of the common-source dual-ring gate P-type gallium nitride enhancement-mode device is as follows:

[0047] Step 1: Fabricating the device wafer: An AlGaN buffer layer (202), a GaN channel layer (203), an AlGaN barrier layer (204), a GaN cap layer (205), and a P-GaN layer (206) are sequentially grown on a Si substrate (201) to form a P-GaN HEMT epitaxial structure. (See schematic diagram below.) Figure 3 As shown.

[0048] Step 2: Cleaning the epitaxial wafer: Acetone, ethanol, dilute hydrochloric acid and other solutions are usually used to remove impurities. First, acetone and ethanol are used to treat organic matter, and then dilute hydrochloric acid is used to remove inorganic matter. Ultrasonic waves are used to assist in the cleaning process. Finally, deionized water is used for rinsing and nitrogen is used for drying.

[0049] Step 3, Device Isolation: The cleaned epitaxial wafer is placed in a 100℃ wafer dryer and dried for 5 minutes; then photolithography is performed. After photolithography, hard coating is performed, and a portion of the P-GaN (206) area is masked with photoresist. Then, inductively coupled plasma etching (ICP) is used to etch the P-GaN (206), GaN cap layer (205), AlGaN barrier layer (204), and the upper part of GaN channel layer (203) vertically. The etching depth is 400nm, so that the etching depth is below the two-dimensional electron gas. Then, the photoresist is cleaned with acetone. Schematic diagram as follows. Figure 4 As shown.

[0050] Step 4: Growing SiO2 to Protect the Mesa: After cleaning the device following the inductively coupled plasma etching (ICP) process, perform a second photolithography step, masking the active region with photoresist. Grow 200nm SiO2 using inductively coupled plasma chemical vapor deposition (ICPCVD), then immerse the device in a stripping solution to remove the SiO2 from the active region, exposing the active region. Retain the SiO2 at the channel and the edge of the active region (112). See schematic diagram below. Figure 5 As shown.

[0051] Step 5: P-GaN Etching: The device undergoes photolithography. A portion of the P-GaN (206) is masked with photoresist, and then etched using inductively coupled plasma (ICP) etching technology to a depth of 100 nm, removing a portion of the P-GaN. The photoresist is then cleaned. (See schematic diagram below.) Figure 6 As shown.

[0052] Step 6: Isolate the electrodes: Perform photolithography on the device, and etch (113) of the device using ICP etching to a depth of 400 nm, so that the etching depth is below the two-dimensional electron gas. (See schematic diagram below.) Figure 10 , Figure 11 As shown.

[0053] Step 7: Sputtering source and drain electrodes: Perform photolithography on the device, and then sputter metal electrodes, such as Ti / Al / Ni / Au, onto the grooves (103) etched at the source electrode and the grooves (106) etched at the drain electrode in the region after P-GaN etching. (See schematic diagram below.) Figure 7 As shown.

[0054] Step 8: Perform rapid thermal annealing: Place the device in a rapid annealing furnace for rapid thermal annealing, so that the source metal (101) and drain metal (104) form ohmic contacts with the AlGaN barrier layer (204).

[0055] Step 9: Growing the gate electrode: The device is subjected to photolithography to deposit gate metal, such as Ti / Au, on the double-ring P-GaN(206) formed after ICP etching, forming a double-ring gate electrode. The double-ring gate electrode forms a Schottky contact with the P-GaN(206). A schematic diagram is shown below. Figure 8 As shown.

[0056] Step 10: Passivation: A 300 nm Si3N4 (207) passivation layer is grown using plasma-enhanced chemical vapor deposition (ICPCVD). Schematic diagram shown below. Figure 9 As shown.

[0057] Step 11, Opening: The device is opened by using the photoresist retained after photolithography as a mask to etch the passivation layer, exposing the source electrode (101) and gate electrode (114) to form the final product.

[0058] Example 2

[0059] An enhanced GaN HEMT dual-ring gate device. See also Figure 1 From the top view of the device, it is divided into 14 regions from the inside out: the source aperture region (101), the circular drain aperture region (104), the square drain aperture region (110), the gate aperture region (114), the groove etched at the source electrode (103), the remaining P-GaN under the gate after etching (107), the annular outer gate electrode (108), the annular inner gate electrode (109), the groove etched at the drain electrode (106), the inner drain electrode (105), the outer drain electrode (111), the SiO2 protective layer (112), and the electrical isolation (113). The device cross-sectional structure is shown in the figure. Figure 2As shown, the structure from bottom to top is as follows: Si substrate (201), AlGaN buffer layer (202), GaN channel layer (203), AlGaN barrier layer (204), GaN cap layer (205), P-GaN layer (206), SiO2 protective layer (112), sputtered source electrode (101), sputtered inner drain electrode (104), sputtered outer drain electrode (110), sputtered inner ring gate electrode (109), sputtered outer ring gate electrode (108), and Si3N4 passivation layer (207). Its epitaxial structure is as follows. Figure 3 As shown.

[0060] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for fabricating a common-source dual-ring gate p-type gallium nitride enhancement-mode device, characterized in that, Step 1: Fabricating the wafer for the device: An AlGaN buffer layer (202), a GaN channel layer (203), an AlGaN barrier layer (204), a GaN cap layer (205), and a P-GaN layer (206) are sequentially grown on a Si substrate (201) to generate a P-GaN HEMT epitaxial structure. Step 2: Cleaning the epitaxial wafer: Use acetone, ethanol, and dilute hydrochloric acid solution to remove impurities. First, treat organic matter with acetone and ethanol, then use dilute hydrochloric acid to remove inorganic matter. Ultrasonic assistance is used during the cleaning process. Finally, rinse with deionized water and dry with nitrogen. Step 3, Device Isolation: Place the cleaned epitaxial wafer in a 100℃ wafer dryer and dry for 5 minutes; then perform photolithography. After photolithography, hard film is applied. Part of the P-GaN (206) area is covered with photoresist, and then plasma inductively coupled etching is used to etch. The P-GaN (206), GaN cap layer (205), AlGaN barrier layer (204), and the upper part of GaN channel layer (203) are removed vertically in a localized manner. The etching depth is 400nm, so that the etching depth is below the two-dimensional electron gas. Then, the photoresist is cleaned with acetone. Step 4: Growing SiO2 to protect the mesa: After cleaning the device after the plasma-inductively coupled etching process, perform a second photolithography, cover the active area with photoresist, grow 200nm SiO2 using inductively coupled plasma chemical vapor deposition, and then put it into the stripping solution to strip away the SiO2 in the active area to expose the active area, retaining the SiO2 at the channel and the edge of the active area (112); Step 5: Perform P-GaN etching: The device is photolithographically processed, and a portion of the P-GaN (206) is masked with photoresist. Then, plasma inductive coupling etching is used to etch the P-GaN to a depth of 100nm, which removes part of the P-GaN, leaving only the P-GaN below the gate and the P-GaN below the drain. Then clean the photoresist; Step 6: Perform isolation between electrodes: Perform photolithography on the device and perform ICP etching on the electrical isolation (113) in the device. The etching depth is 400nm, so that the etching depth is below the two-dimensional electron gas. Then clean the photoresist; Step 7: Sputtering source and drain electrodes: Perform photolithography on the device, and then sputter metal electrodes on the grooves (103) etched at the source electrode and the grooves (106) etched at the drain electrode in the region after P-GaN etching, wherein the drain electrode encapsulates part of the P-GaN. Step 8: Perform rapid thermal annealing: Place the device in a rapid annealing furnace for rapid thermal annealing, so that the source metal (101) and drain metal form ohmic contacts with the AlGaN barrier layer (204); Step 9, Growing the gate electrode: Perform photolithography on the device and sputter the gate metal onto the double-ring P-GaN(206) formed after ICP etching; Step 10: Passivation: A 300 nm Si3N4(207) passivation layer is grown using plasma-enhanced chemical vapor deposition. Step 11, Opening: The device is opened by using the photoresist retained after photolithography as a mask to etch the passivation layer, exposing the source electrode (101) and gate electrode (114) to form the final product.

2. An enhanced gallium nitride high electron mobility transistor device prepared by the method described in claim 1.

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