A three-phase grid-connected phase-locked loop based on double-layer filtering

Abstract

The present application relates to new energy power generation technology field, especially to a kind of three-phase grid-connected phase-locked loop based on double-layer filtering.The present application includes CLARK conversion unit, double-layer filtering unit based on frequency compensation, PARK conversion unit, PI control link, frequency feedback and compensation link, phase output link;Three-phase grid voltage collected is carried out CLARK conversion by CLARK conversion unit, obtains grid voltage component under stationary coordinate system, eliminates common harmonic component in grid voltage, direct current offset under stationary coordinate system by double-layer filtering unit based on frequency compensation, extracts positive sequence component of grid voltage, obtains grid voltage component under synchronous rotating coordinate system again through PARK conversion unit, and is controlled through PI link, the output of PI control is added to grid rated frequency to obtain real-time grid frequency, grid real-time frequency is provided to double-layer filtering unit for frequency compensation by grid real-time frequency feedback link, and the phase of three-phase grid voltage is obtained by integration of grid real-time frequency.

Description

Technical Field

[0001] This invention relates to the field of new energy power generation technology, and in particular to a three-phase grid-connected phase-locked loop based on dual-layer filtering. Background Technology

[0002] To connect distributed generation systems (such as wind and solar power) to the power grid and inject renewable energy into the power system, thereby improving energy efficiency and reducing carbon emissions, grid synchronization technology is required. Among various grid synchronization technologies, phase-locked loops (PLLs) are the most widely used.

[0003] Among them, the Synchronous Reference Coordinate System (SRF-PLL) phase-locked loop is a common method in power grid synchronization phase-locked loop technology, with a simple structure and certain stability. However, with the increasing prevalence of nonlinear loads, harmonic pollution in the power grid is becoming more and more serious, and achieving accurate grid-connected synchronization under such non-ideal power grid conditions remains challenging. In order to improve the filtering capability and dynamic response capability of SRF-PLL and enable it to operate stably under non-ideal power grid conditions such as asymmetric voltage drops and the presence of harmonics, some scholars have proposed using a phase-locked loop structure based on dual second-order generalized integrators (DSOGI-PLL) to extract the positive and negative sequence components of the grid voltage. Compared with SRF-PLL, DSOGI-PLL can reduce the impact of harmonic distortion on the phase-locked loop during power grid faults. However, because DSOGI-PLL is a combination of a bandpass filter and a low-pass filter, it exhibits non-full bandpass filtering characteristics. When the grid voltage experiences DC offset, DSOGI-PLL cannot suppress the interference of the DC offset component on the grid-connected phase-locked loop process, and DSOGI-PLL cannot completely filter out harmonics. To address the issue of DSOGI-PLL's inability to handle DC offset, some researchers have proposed MSTOUGI-PLL, a hybrid second- and third-order generalized integrator phase-locked loop. By modifying the structure of the second-order generalized integrator, it combines two bandpass filters internally to achieve full bandpass filtering characteristics, thus filtering out DC offset components. However, like DSOGI-PLL, MSTOUGI-PLL only suppresses harmonic components and cannot completely filter them out. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention proposes a three-phase grid-connected phase-locked loop based on dual-layer filtering.

[0005] To achieve the above-mentioned objectives, the present invention adopts the following technical solution:

[0006] A three-phase grid-connected phase-locked loop (PLL) based on dual-layer filtering includes a Clark transform unit, a frequency-compensated dual-layer filtering unit, a Park transform unit, a PI control loop, a frequency feedback and compensation loop, and a phase output loop. The collected three-phase grid voltage is subjected to Clark transform by the Clark transform unit to obtain the grid voltage components in a stationary coordinate system. In the stationary coordinate system, the frequency-compensated dual-layer filtering unit eliminates common harmonic components and DC offsets in the grid voltage, extracting the positive-sequence components. The Park transform unit then obtains the grid voltage components in a synchronously rotating coordinate system, which are controlled by a PI control loop. The output of the PI control is added to the grid's rated frequency to obtain the real-time grid frequency. The grid frequency feedback loop provides the real-time grid frequency to the dual-layer filtering unit for frequency compensation. The real-time grid frequency is integrated to obtain the phase of the three-phase grid voltage.

[0007] As a further preferred embodiment of the present invention, the frequency-compensated dual-layer filtering unit is composed of a delay signal canceller in a stationary coordinate system and a dual second- or third-order generalized integrator with full bandpass filtering characteristics.

[0008] Furthermore, as a preferred embodiment of the present invention, the delay signal canceller in the stationary coordinate system is obtained by extending the series delay element in the synchronous rotating coordinate system to the stationary coordinate system, and taking the delay period as (T) n +T c ) / N,T n T is the rated period of the three-phase power grid voltage. c For periodic compensation, N is the delay factor, which takes values ​​of 4, 6, and 24 respectively; the transfer function of the series delay signal canceller in the stationary coordinate system is:

[0009]

[0010] Where s represents the complex frequency and j represents the imaginary unit.

[0011] Furthermore, as a preferred embodiment of the present invention, the dual second- and third-order generalized integrator with full bandpass filtering characteristics introduces frequency compensation in the hybrid second- and third-order generalized integrator; the transfer function of the dual second- and third-order generalized integrator is:

[0012]

[0013] Where k is the damping factor, w n The rated frequency of the three-phase power grid, w c For frequency compensation.

[0014] Furthermore, as a preferred embodiment of the present invention, the transfer function of the frequency-compensated dual-layer filter unit is:

[0015]

[0016] The three-phase grid-connected phase-locked loop based on dual-layer filtering described in this invention has the following technical advantages compared with existing technologies:

[0017] The phase-locked loop (PLL) with a dual-layer filter unit proposed in this invention can operate stably under various non-ideal power grid conditions. Compared with traditional second-order generalized integrator PLLs and hybrid second- and third-order generalized integrator PLLs, the PLL structure proposed in this invention has more comprehensive anti-interference capabilities and can operate under non-ideal power grid conditions such as harmonic injection, DC offset, and asymmetrical voltage drops, thus having a wider range of applications. Attached Figure Description

[0018] Figure 1 A schematic diagram of a three-phase grid-connected phase-locked loop structure based on double-layer filtering provided by the present invention;

[0019] Figure 2 A schematic diagram of the multi-delay signal canceller structure based on period compensation provided by the present invention;

[0020] Figure 3 Bode plot of the transfer function of the multi-delay signal canceller provided by the present invention;

[0021] Figure 4 Bode plot of the transfer function of the double second-order generalized integrator provided by the present invention;

[0022] Figure 5 Bode plot of the transfer function of the hybrid second- and third-order generalized integrator provided by the present invention;

[0023] Figure 6 A schematic diagram of the dual second- and third-order generalized integrator structure based on frequency compensation provided by the present invention;

[0024] Figure 7 Bode plot of the transfer function of the frequency-compensated dual second- and third-order generalized integrator provided in this invention;

[0025] Figure 8 Bode plot of the transfer function of the two-layer filter unit provided in this invention;

[0026] Figure 9 This is a waveform diagram of a three-phase power grid voltage asymmetry drop in an embodiment of the present invention;

[0027] Figure 10 This is a frequency estimation diagram for a three-phase power grid voltage asymmetry drop in an embodiment of the present invention;

[0028] Figure 11This is a waveform diagram of DC offset mixed into the three-phase power grid voltage in an embodiment of the present invention;

[0029] Figure 12 This is a frequency estimation diagram of DC offset mixed into the three-phase power grid voltage in an embodiment of the present invention;

[0030] Figure 13 This is a waveform diagram of harmonics mixed into the three-phase power grid voltage in an embodiment of the present invention;

[0031] Figure 14 This is a frequency estimation diagram of harmonics mixed into the three-phase power grid voltage in an embodiment of the present invention;

[0032] Figure 15 This is a waveform diagram showing the mixing of harmonic components and frequency jumps in the three-phase power grid voltage in an embodiment of the present invention.

[0033] Figure 16 This is a frequency estimation diagram showing the mixing of harmonic components and frequency jumps in the three-phase power grid voltage in an embodiment of the present invention. Detailed Implementation

[0034] The present invention will be further explained in detail below with reference to the accompanying drawings, so that those skilled in the art can better understand and implement the present invention. However, the following examples are only used to explain the present invention and are not intended to limit the present invention.

[0035] like Figure 1 As shown, a three-phase grid-connected phase-locked loop (PLL) based on dual-layer filtering includes a Clark converter unit, a frequency-compensated dual-layer filter unit, a Parker converter unit, a PI control loop, a frequency feedback and compensation loop, and a phase output loop. The three-phase grid voltage, after Clark converter transformation, outputs components in a stationary coordinate system. The output is connected to the dual-layer filter unit, which consists of a period-compensated multi-delay signal canceller and a frequency-compensated dual second- and third-order generalized integrators. The dual-layer filter unit first filters out harmonic components from the input signal, then filters out DC offset components, and outputs the positive-sequence component. The output of the dual-layer filter unit is connected to the input of the Parker converter, which converts the three-phase grid voltage components from the stationary coordinate system to a synchronous rotating coordinate system. The output of the Parker converter, after PI control, is added to the grid's rated frequency, and after integration, outputs a phase signal, which is fed back to the Parker converter.

[0036] Synchronous rotating coordinate system phase-locked loops (SRF-PLLs) can accurately extract the phase of the grid voltage when the grid voltage is stable. However, if the grid voltage experiences three-phase asymmetric drops, DC offset, or harmonic interference, traditional SRF-PLLs cannot accurately lock the grid voltage phase. Dual second-order generalized integrator phase-locked loops (DSOGI-PLLs) can still accurately detect the grid voltage phase even during asymmetric voltage drops. However, DSOGI-PLLs cannot handle interference caused by DC offset because the dual second-order generalized integrator internally uses a combination of a bandpass filter and a low-pass filter, not a full bandpass filter. The second- and third-order hybrid generalized integrator phase-locked loop (MSTOGI-PLL), compared to DSOGI-PLLs, has an improved internal design with a combination of two bandpass filters, achieving a full bandpass filter and thus effectively eliminating DC offset. However, neither DSOGI-PLLs nor MSTOGI-PLLs are sufficient to suppress harmonic components mixed into the grid voltage. To address the interference caused by harmonics, a frequency-compensated dual-layer filter unit is used. Within the dual-layer filter unit, harmonics and DC offset are eliminated, and the positive-sequence component of the grid voltage is extracted, thereby achieving accurate detection of the grid voltage phase.

[0037] The transfer function of using a delay element to eliminate grid voltage harmonic components in a synchronously rotating (dq) coordinate system is:

[0038]

[0039] In the formula, T represents the power grid cycle.

[0040] To achieve a fast dynamic response in the phase-locked loop (PLL), this component is moved from inside the PLL to outside the loop, i.e., after transforming from the synchronous rotating (dq) coordinate system to the stationary reference (αβ) coordinate system, the transfer function becomes:

[0041]

[0042] The delay period of the delay signal canceller is selected based on the common harmonic components (-5, +7, -11, +13) in the power grid voltage and then connected in series. Its transfer function is:

[0043]

[0044] To accurately eliminate harmonic components even when the power grid frequency fluctuates, frequency compensation is introduced, which is reflected in the delay signal cancellation unit as period compensation T. c The delay period is (T) n +T c ) / N,T n T is the rated period of the three-phase power grid voltage. cFor periodic compensation, N is the delay factor, which takes values ​​of 4, 6, and 24 respectively; the improved structure is as follows: Figure 2 As shown, the transfer function of this stage is:

[0045]

[0046] Bode plot of the transfer function of the delay signal cancellation unit as shown in Figure 3 As shown, the solid line represents the characteristic curve when the grid frequency is 50Hz, and the dashed line represents the characteristic curve when the grid frequency fluctuates to 55Hz. Before and after the frequency change, the amplitude gain is 1 and the phase is 0 for the fundamental frequency of the grid. However, for common harmonic components in the grid voltage (-5, +7, -11, +13), the amplitude gain is 0, indicating that the aforementioned delay signal canceller structure has the ability to cancel harmonic components.

[0047] The transfer function of a traditional double second-order generalized integrator is:

[0048]

[0049] In the formula, w is the resonant frequency, and w = 100*pi is taken.

[0050] The Bode plot of its transfer function is as follows Figure 4 As shown, the amplitude gain is not zero at the DC component, meaning that the DC component cannot be filtered out. Therefore, if a dual second-order generalized integrator is used, it is impossible to accurately detect the phase of the three-phase grid voltage when the DC component is present.

[0051] The transfer function of the hybrid second- and third-order generalized integrator is:

[0052]

[0053] The Bode plot of its transfer function is as follows Figure 5 As shown, for the fundamental frequency of the power grid, the amplitude gain is 1 and the phase is 0. At the DC component, the amplitude gain is 0, which means that the DC component can be filtered out. Therefore, by using a hybrid second- or third-order generalized integrator, the phase of the three-phase power grid voltage can be detected even when the DC component is present.

[0054] To eliminate the DC component and preserve the extraction of the fundamental frequency of the power grid even during frequency fluctuations, frequency compensation (w) is introduced. c The improved structure is as follows: Figure 6 As shown, its transfer function is:

[0055]

[0056] In the formula w n The rated frequency of the grid voltage.

[0057] The Bode plot of its transfer function is as follows Figure 7 As shown, the solid line represents the characteristic curve when the grid frequency is 50Hz, and the dashed line represents the characteristic curve when the grid frequency fluctuates to 55Hz. Before and after the frequency change, for the fundamental frequency of the grid, the amplitude gain is 1 and the phase is 0. However, for the DC offset component in the grid voltage, the amplitude gain is 0.

[0058] In summary, the transfer function of the two-layer filter unit is:

[0059]

[0060] The transfer function of the two-layer filter unit is as follows Figure 8 As shown, regardless of whether the voltage is at the grid's rated frequency or experiencing frequency fluctuations, the amplitude gain is 0 at each harmonic (-5, +7, -11, +13) and DC offset component, while the amplitude gain is 1 and the phase is 0 at the grid voltage's rated frequency. Therefore, the proposed frequency-compensated dual-layer filter unit can completely filter out the harmonic components of the grid voltage, eliminate DC offset, extract the positive-sequence fundamental component of the grid voltage, and achieve grid voltage phase detection.

[0061] To verify the performance of the phase-locked loop (PLL) proposed in this invention, simulation experiments were conducted using MATLAB / SIMULINK. The anti-interference performance of the PLL under non-ideal grid voltage conditions was verified, including: asymmetrical grid voltage drops, harmonic interference, harmonic interference at non-rated grid voltage frequencies, and DC offset component injection. In the experiment, the rated grid frequency was 50Hz, and the three-phase grid voltage amplitude was 311V. The comparison objects were the dual second-order generalized integrator PLL DSOGI-PLL and the second- and third-order hybrid generalized integrator PLL MSTOGI-PLL.

[0062] Figure 9 This is the power grid waveform during a three-phase power grid voltage asymmetry drop in an application embodiment of the present invention. Figure 10 The grid frequency is estimated under this condition. The time for a two-phase voltage drop of 0.15 pu is 0.15 s. All three phase-locked loops can recover after being disturbed and accurately detect the grid frequency. Among them, the phase-locked loop technology proposed in this invention has the smallest frequency fluctuation. The frequency estimation overshoot of DSOGI-PLL is 2.03 Hz, that of MSTGI-PLL is 0.82 Hz, and that of DLF-PLL is 0.22 Hz.

[0063] Figure 11 This is the power grid waveform when a DC offset component is injected into the three-phase power grid voltage in an application embodiment of the present invention. Figure 12For the grid frequency estimation under this condition, the DC offset injection time is 0.15s. It can be observed that the traditional DSOGI-PLL cannot extract the grid voltage frequency when DC offset is mixed in, while the MSTOGI-PLL, due to its full bandpass filtering characteristics, can filter out the DC component in the grid voltage. The phase-locked loop proposed in this invention, due to its use of a dual-layer filtering unit, can also filter out the DC component in the grid voltage, and has the smallest overshoot in frequency estimation. The MSTOGI-PLL overshoot is 1.72Hz, and the DLF-PLL frequency estimation overshoot is 0.35Hz.

[0064] Figure 13 This is the power grid waveform when harmonics are mixed into the three-phase power grid voltage in an application embodiment of the present invention. Figure 14 For the grid frequency estimation under this condition, the -5th harmonic (0.1 pu) and +7th harmonic (0.05 pu) are mixed in at 0.15s. Neither DSOGI-PLL nor MSTOOGI-PLL can filter out the harmonic components of the grid voltage, and their frequency estimation is oscillating. However, the phase-locked loop proposed in this invention achieves the elimination of grid harmonic components through a two-layer filtering technique. Therefore, after the harmonic components are mixed in, the lock on the grid frequency can be restored in less than half of the grid cycle.

[0065] Figure 15 This is a power grid waveform in an application embodiment of the present invention, showing frequency fluctuations and the inclusion of harmonics in the three-phase power grid voltage. Figure 16 For the grid frequency estimation under this condition, a 5Hz frequency jump occurs at 0.15s, mixed with the -11th harmonic (0.05pu) and +13th harmonic (0.05pu). Even if the grid frequency is not the rated value, the phase-locked loop proposed in this invention can still filter out harmonics and accurately lock the grid voltage frequency. In contrast, DSOGI-PLL and MSTOUGI-PLL cannot filter out harmonics and therefore cannot accurately lock the grid voltage frequency.

[0066] Through the above application scenarios, the phase-locked loop (PLL) proposed in this invention possesses more comprehensive anti-interference capabilities, and can operate under conditions such as harmonic injection, DC offset, and asymmetrical voltage drops in the power grid, achieving anti-interference coverage under various non-ideal operating conditions. This invention employs dual-layer filtering to eliminate harmonics and DC offset, extracts the positive-sequence component of the power grid voltage, and can still maintain stable phase-locking even under conditions such as asymmetrical voltage drops and frequency jumps. The PLL proposed in this invention exhibits good filtering performance, high locking accuracy, and strong anti-interference capabilities.

[0067] The specific implementation schemes described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific implementation schemes of the present invention and are not intended to limit the scope of the present invention. Any equivalent changes and modifications made by those skilled in the art without departing from the concept and principles of the present invention should fall within the scope of protection of the present invention.

Claims

1. A three-phase grid-connected phase-locked loop based on dual-layer filtering, characterized in that, The system includes a Clark transform unit, a frequency-compensated double-layer filter unit, a Park transform unit, a PI control loop, a frequency feedback and compensation loop, and a phase output loop. The collected three-phase grid voltage is subjected to a Clark transform by the Clark transform unit to obtain the grid voltage components in the stationary coordinate system. In the stationary coordinate system, the frequency-compensated double-layer filter unit eliminates common harmonic components and DC offset in the grid voltage, extracting the positive-sequence component of the grid voltage. The Park transform unit then obtains the grid voltage components in the synchronous rotating coordinate system, which are controlled by a PI loop. The output of the PI control is added to the grid's rated frequency to obtain the real-time grid frequency. The grid frequency feedback loop provides the real-time grid frequency to the double-layer filter unit for frequency compensation. The real-time grid frequency is integrated to obtain the phase of the three-phase grid voltage. The frequency-compensated dual-layer filter unit consists of a delay signal canceller in a stationary coordinate system and a dual second- or third-order generalized integrator with full bandpass filtering characteristics. The delay signal canceller in the stationary coordinate system is obtained by extending the series delay element in the synchronous rotating coordinate system to the stationary coordinate system, with a delay period of (T). n +T c ) / N,T n T is the rated period of the three-phase power grid voltage. c For periodic compensation, N is the delay factor; the transfer function of the series delay signal canceller in the stationary coordinate system is: ； Where s represents the complex frequency and j represents the imaginary unit; The dual second- and third-order generalized integrator with full bandpass filtering characteristics introduces frequency compensation into the hybrid second- and third-order generalized integrator; the transfer function of the dual second- and third-order generalized integrator is: ； Where k is the damping factor, w n The rated frequency of the three-phase power grid, w c For frequency compensation.

2. The three-phase grid-connected phase-locked loop based on dual-layer filtering according to claim 1, characterized in that, The transfer function of the frequency-compensated two-layer filter unit is: 。

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