Fixed frequency DC-DC converter

Abstract

The disclosure provides a kind of fixed frequency DC-DC converter, comprising: PWM drive circuit, upper power tube, lower power tube, output circuit, comparison circuit, transient enhancement circuit and or gate;Wherein, PWM drive circuit generates PWM signal according to the output signal of or gate, and generates the first drive signal of upper power tube and the second drive signal of lower power tube according to PWM signal;Comparison circuit generates pulse width modulation signal according to the output feedback voltage generated by output circuit, transient enhancement circuit generates first ripple voltage, and the superposition processing of output feedback voltage and first ripple voltage is carried out to generate second ripple voltage, and the generated second ripple voltage is compared with the reference voltage of second ripple voltage, and comparison signal is obtained, wherein, the duty cycle of first ripple voltage is related to the duty cycle of PWM signal;Or gate according to pulse width modulation signal and comparison signal, output signal to PWM drive circuit.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and specifically to a fixed-frequency DC-DC converter. Background Technology

[0002] Currently, the pace of technological advancements in consumer electronics, communications, IoT, and automotive electronics is accelerating, performance requirements are becoming increasingly stringent, and functions are becoming more complex. This places ever higher demands on the dynamic performance of switching converters such as DC-DC converters. With the world entering the era of big data, the implementation of national "East-West Data Computing" projects, and the rapid development of AI technology, the demand for servers and data centers is becoming increasingly urgent. Many servers require rapidly changing current from loads such as Field-Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), and other high-power central processing units (CPUs). Moreover, to ensure data security and the safety and reliability of server systems, server power supplies often have more stringent transient response requirements.

[0003] Pulse Width Modulation (PWM) offers a constant switching period, resulting in a narrower noise spectrum bandwidth, simpler filter circuit design, and lower output voltage ripple. It is also more resistant to electromagnetic interference (EMI) design. Furthermore, fixed-frequency systems are easier to synchronize with external frequencies, which is beneficial for multi-phase parallel operation and stable phase control. Therefore, introducing optimized circuits to improve key performance parameters of the constant-frequency PWM control system, such as fast load transition response, output voltage, undershoot voltage, and overshoot voltage, to enhance the stability and robustness of the power supply system and protect downstream modules, is a highly attractive design approach.

[0004] However, in optimizing transient response, the fixed-frequency DC-DC converter in the related technology needs to wait for the output signal of the error amplifier with a small bandwidth in the loop to change during the load change process, which results in a delay. Summary of the Invention

[0005] The main objective of this disclosure is to provide a fixed-frequency DC-DC converter to solve the problem in related technologies where, when optimizing transient response, the fixed-frequency DC-DC converter needs to wait for the output signal of the error amplifier with a small bandwidth in the loop to change during load changes, resulting in a delay.

[0006] To achieve the above objectives, a first aspect of this disclosure provides a fixed-frequency DC-DC converter, comprising: a PWM drive circuit, an upper power transistor, a lower power transistor, an output circuit, a comparator circuit, a transient enhancement circuit, and an OR gate;

[0007] The PWM drive circuit is configured to generate a PWM signal based on the output signal of the OR gate, and to generate a first drive signal for the upper power transistor and a second drive signal for the lower power transistor based on the PWM signal.

[0008] The comparator circuit is configured to generate a pulse width modulation signal based on the output feedback voltage generated by the output circuit;

[0009] The transient enhancement circuit is configured to generate a first ripple voltage, superimpose the output feedback voltage and the first ripple voltage to generate a second ripple voltage, and compare the generated second ripple voltage with a reference voltage of the second ripple voltage to obtain a comparison signal, wherein the duty cycle of the first ripple voltage is related to the duty cycle of the PWM signal; and

[0010] The OR gate is configured to output a signal to the PWM drive circuit based on the pulse width modulation signal and the comparison signal output by the transient enhancement circuit.

[0011] Optionally, the PWM drive circuit includes an oscillator, PWM logic circuitry, and a driver;

[0012] The oscillator is configured to output an oscillation signal to the PWM logic circuit;

[0013] The first terminal of the PWM logic circuit is coupled to the oscillator, and the second terminal of the PWM logic circuit is coupled to the output terminal of the OR gate. The PWM logic circuit is configured to perform pulse width modulation according to the oscillation signal and the output signal of the OR gate, and output a PWM signal to the driver.

[0014] The driver is configured to output a first drive signal for the upper power transistor and a second drive signal for the lower power transistor based on the PWM signal.

[0015] Optionally, the output circuit includes an inductor, an output capacitor, a first feedback resistor, and a second feedback resistor;

[0016] The first end of the inductor is coupled to the first node between the upper power transistor and the lower power transistor, and the second end of the inductor is coupled to the first end of the output capacitor and the first end of the first feedback resistor, respectively. The inductor is configured to store energy when the upper power transistor is turned on.

[0017] The second end of the first feedback resistor is coupled to the first end of the second feedback resistor via a second node, and the second node is used to generate the output feedback voltage.

[0018] The second terminal of the output capacitor and the second terminal of the second feedback resistor are respectively grounded.

[0019] Optionally, the comparison circuit includes an error amplifier and a pulse width modulation comparator;

[0020] The input of the error amplifier is coupled to the output feedback voltage, and the output of the error amplifier is coupled to the input of the pulse width modulation comparator. The error amplifier is configured to compare the output feedback voltage with the reference voltage of the output feedback voltage and output the error integral result to the pulse width modulation comparator. The reference voltage of the output feedback voltage is provided by a fixed-frequency DC-DC converter.

[0021] The output of the pulse width modulation comparator is coupled to the first input of the OR gate. The pulse width modulation comparator is configured to compare the output signal of the error amplifier and the reference voltage of the output signal, and output the pulse width modulation signal to the OR gate. The PWM drive circuit, the upper power transistor, the lower power transistor, the output circuit, the comparator circuit and the OR gate form a loop. The reference voltage of the output signal is generated by real-time acquisition of loop information.

[0022] Optionally, the transient enhancement circuit includes a ripple generation circuit and a comparator;

[0023] The first terminal of the ripple generation circuit is coupled to the output feedback voltage, and the second terminal of the ripple generation circuit is coupled to the first input terminal of the comparator. The ripple generation circuit is configured to generate a first ripple voltage, generate a second ripple voltage based on the first ripple voltage and the output feedback voltage, and output the second ripple voltage to the comparator.

[0024] The comparator is configured to output a comparison signal to the OR gate when the second ripple voltage is less than or equal to the reference voltage of the second ripple voltage, and when the second ripple voltage is greater than the reference voltage of the second ripple voltage, the comparison signal output to the OR gate is at an active level.

[0025] Furthermore, the ripple generation circuit includes a first resistor, a first capacitor, a DC value extractor, a first adder, an amplifier, a second adder, and a first buffer;

[0026] The first end of the first resistor is coupled to the first node between the upper power transistor and the lower power transistor, and the second end of the first resistor is coupled to the first input terminal of the first adder via the third node.

[0027] The first terminal of the first capacitor is coupled to the third node, and the second terminal of the first capacitor is grounded.

[0028] The input terminal of the DC value extractor is coupled to the third node, and the output terminal of the DC value extractor is coupled to the second input terminal of the first adder.

[0029] The output of the first adder is coupled to the input of the amplifier. The first adder is configured to remove the DC signal from the signal from the third node and output the AC signal from the signal of the third node to the amplifier.

[0030] The output of the amplifier is coupled to the first input of the second adder. The amplifier is configured to amplify the AC signal by a factor of k before outputting it to the second adder.

[0031] The first terminal of the first buffer is coupled to the output feedback voltage, and the second terminal of the first buffer is coupled to the second input terminal of the second adder.

[0032] The second adder is configured to superimpose the amplified AC signal (by a factor of k) and the output feedback voltage, thereby generating a second ripple voltage through the output of the second adder.

[0033] Optionally, the ripple generation circuit includes a DC level generation circuit, a triangular wave generation circuit, and a signal superposition circuit;

[0034] The first terminal of the DC level generation circuit is coupled to the output feedback voltage, and the second terminal of the DC level generation circuit is coupled to the first input terminal of the signal superposition circuit. The DC level generation circuit is configured to generate a DC level based on the output feedback voltage.

[0035] The PWM signal is input through the first terminal of the triangular wave generation circuit, and the second terminal of the triangular wave generation circuit is coupled to the second input terminal of the signal superposition circuit. The triangular wave generation circuit is configured to generate a triangular wave with a corresponding duty cycle according to the duty cycle of the PWM signal.

[0036] The output of the signal superposition circuit is coupled to the fourth node. The signal superposition circuit is configured to superimpose a DC level and a triangular wave to generate a second ripple voltage.

[0037] Furthermore, the DC level generation circuit includes a second buffer, a second resistor, and a second capacitor;

[0038] The first end of the second buffer is coupled to the output feedback voltage, and the second end of the second buffer is coupled to the first end of the second resistor.

[0039] The second end of the second resistor is coupled to the first end of the second capacitor, and the second resistor is configured to generate a DC level.

[0040] The second terminal of the second capacitor is grounded;

[0041] The triangular wave generating circuit includes a second transconductance amplifier, an inverter, a switch, and a third capacitor;

[0042] The non-inverting input of the second transconductance amplifier is coupled to the second reference voltage terminal, the inverting input of the second transconductance amplifier is grounded, the current input of the second transconductance amplifier is coupled to the power supply voltage terminal, the output of the second transconductance amplifier is coupled to the fifth node, and the second transconductance amplifier is configured to generate a triangular wave at the fifth node.

[0043] The PWM signal is input through the first terminal of the inverter, and the second terminal of the inverter is coupled to the first terminal of the switch.

[0044] The second terminal of the switch is coupled to the fifth node, and the third and fourth terminals of the switch are grounded.

[0045] The first terminal of the third capacitor is coupled to the fifth node, and the second terminal of the third capacitor is grounded.

[0046] The signal superposition circuit includes a first transconductance amplifier, a third resistor, and a third transconductance amplifier;

[0047] The non-inverting input terminal of the first transconductance amplifier is coupled to the second terminal of the second resistor and the first terminal of the second capacitor, respectively; the inverting input terminal of the first transconductance amplifier is coupled to the first reference voltage terminal; the current input terminal of the first transconductance amplifier is coupled to the power supply voltage terminal; and the output terminal of the first transconductance amplifier is coupled to the first terminal of the third resistor and the fourth node, respectively.

[0048] The second terminal of the third resistor is grounded;

[0049] The non-inverting input of the third transconductance amplifier is coupled to the fifth node, the inverting input of the third transconductance amplifier is grounded, the current input of the third transconductance amplifier is coupled to the power supply voltage terminal, and the output of the third transconductance amplifier is coupled to the fourth node. The third transconductance amplifier is configured to superimpose a DC level and a triangular wave at the fourth node to generate a second ripple voltage.

[0050] Optionally, the reference voltage generation circuit for the second ripple voltage includes a fourth transconductance amplifier and a fourth resistor;

[0051] The reference voltage of the output feedback voltage is input through the non-inverting input terminal of the fourth transconductance amplifier, the inverting input terminal of the fourth transconductance amplifier is coupled to the first reference voltage terminal, the current input terminal of the fourth transconductance amplifier is coupled to the power supply voltage terminal, and the output terminal of the fourth transconductance amplifier is coupled to the first terminal of the fourth resistor. The fourth transconductance amplifier is configured to generate the reference voltage of the second ripple voltage.

[0052] The second terminal of the fourth resistor is grounded.

[0053] Furthermore, the reference voltage generation circuit for the second ripple voltage also includes a fifth transconductance amplifier;

[0054] The voltage input to the non-inverting input of the fifth transconductance amplifier is related to the ratio of the output voltage to the input voltage in the loop. The inverting input of the fifth transconductance amplifier is grounded. The current input of the fifth transconductance amplifier is coupled to the power supply voltage terminal. The output of the fifth transconductance amplifier is coupled to the first terminal of the fourth resistor.

[0055] A second aspect of this disclosure provides a chip comprising a fixed-frequency DC-DC converter according to any one of the first aspects.

[0056] A third aspect of this disclosure provides an electronic device including the chip of the second aspect.

[0057] In the fixed-frequency DC-DC converter provided in this embodiment, a transient enhancement circuit is configured to generate a first ripple voltage, and to superimpose the output feedback voltage and the first ripple voltage to generate a second ripple voltage. The generated second ripple voltage is then compared with a reference voltage to obtain a second comparison signal. The duty cycle of the first ripple voltage is related to the duty cycle of the PWM signal. An OR gate is configured to output a signal to the PWM drive circuit based on the pulse width modulation signal and the comparison signal output by the transient enhancement circuit. This disclosure, through the transient enhancement circuit, can accelerate the transient response of the load during load changes without waiting for the output signal of the error amplifier with a small bandwidth in the loop to change. This solves the problem of delay in related technologies where fixed-frequency DC-DC converters need to wait for the output signal of the error amplifier with a small bandwidth in the loop to change during load changes when optimizing transient response. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the specific embodiments of this disclosure or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 To adopt V 2 An exemplary circuit diagram of a control method optimized for a fixed-frequency DC-DC converter;

[0060] Figure 2 To adopt V 2 An exemplary circuit diagram of a fixed-frequency DC-DC converter optimized by the C control method;

[0061] Figure 3 An exemplary circuit diagram for optimizing a fixed-frequency DC-DC converter using hybrid buck-linear technology;

[0062] Figure 4 This is an exemplary block diagram of a fixed-frequency DC-DC converter provided in an embodiment of this disclosure;

[0063] Figure 5 An exemplary circuit diagram of a fixed-frequency DC-DC converter provided in this disclosure embodiment;

[0064] Figure 6 An exemplary circuit diagram of a ripple generation circuit provided in an embodiment of this disclosure;

[0065] Figure 7 An exemplary circuit block diagram of a ripple generation circuit provided in yet another embodiment of this disclosure;

[0066] Figure 8 An exemplary circuit diagram of a ripple generation circuit provided in yet another embodiment of this disclosure;

[0067] Figure 9 An exemplary circuit diagram of a reference voltage generation circuit for a second ripple voltage provided in an embodiment of this disclosure;

[0068] Figure 10 An exemplary circuit diagram of a reference voltage generation circuit for a second ripple voltage provided in another embodiment of this disclosure;

[0069] Figure 11 A schematic diagram of the second ripple voltage and the reference voltage of the second ripple voltage provided in the embodiments of this disclosure;

[0070] Figure 12 This is a schematic diagram illustrating the working principle of transient enhancement technology in a fixed-frequency DC-DC converter provided in this embodiment of the disclosure.

[0071] Figure 13 The transient response simulation results with transient enhancement circuit provided for the embodiments of this disclosure are shown in the figure.

[0072] Figure 14 The simulation results for the transient response without the transient enhancement circuit are shown in the figure.

[0073] Figure 15 A simulation comparison diagram of the transient response of the output voltage with and without transient enhancement circuit provided in the embodiments of this disclosure. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0075] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0076] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. The transistors used in the embodiments of this disclosure are primarily switching transistors. Furthermore, for the sake of consistency, in this context, the base of a bipolar junction transistor (BJT) is referred to as the control terminal, the collector of the BJT as the second terminal, and the emitter of the BJT as the first terminal. Additionally, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0077] Today, consumer electronics, communication electronics, IoT, and automotive electronics are being updated and replaced at an increasingly rapid pace, with increasingly stringent performance requirements and more complex functions, placing ever higher demands on the dynamic performance of switching converters. As the world enters the era of big data, with the implementation of national "East-West Data Computing" projects and the rapid advancement of AI technology, the demand for servers and data centers is becoming increasingly urgent. Many servers require rapid changes in current from loads such as Field-Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), and other high-power Central Processing Units (CPUs). Moreover, to ensure data security and the safety and reliability of server systems, server power supplies often have even stricter transient response requirements.

[0078] Pulse Width Modulation (PWM) offers a constant switching period, resulting in a narrower noise spectrum bandwidth, simpler filter circuit design, and lower output voltage ripple. It is also more resistant to electromagnetic interference (EMI) design. Furthermore, fixed-frequency systems are easier to synchronize with external frequencies, which is beneficial for multi-phase parallel operation and stable phase control. Therefore, introducing optimized circuits to improve key performance parameters of the constant-frequency PWM control system, such as fast load transition response, output voltage, undershoot voltage, and overshoot voltage, to enhance the stability and robustness of the power supply system and protect downstream modules, is a highly attractive design approach.

[0079] Currently, there are two main methods for optimizing the transient response of fixed-frequency DC-DC systems:

[0080] (1) Optimization of control methods for fixed-frequency DC-DC converters

[0081] Some designs in fixed-frequency systems acquire information from loops that change more rapidly, adding more "fast-response" loops to the original system, increasing feedforward paths, and improving system bandwidth through the rational design of the relationships between various signals, thereby accelerating transient response. For example... Figure 1 The V shown 2 Control methods Figure 2 The V shown 2 C control methods and Figure 3 The Hybrid Buck-Linear (HBL) technology shown; Figure 3 In this context, MUX stands for multiplexer, and the voltage V... G The expression is a two-way strobe, and V in steady-state DC-DC mode. G =V GP In the case of transient enhancement, V G =V GP2 , Figure 3 The error amplifier with a smaller bandwidth in the loop is EA1.

[0082] However, the above Figure 1 , Figure 2 and Figure 3 The method shown undoubtedly requires careful design and comprehensive simulation of the loop during implementation. Moreover, it still requires waiting for the output signal of the error amplifier with a small bandwidth in the loop to change during load changes, resulting in a certain delay and considerable room for optimization.

[0083] (2) Transient enhancement of nonlinear loop

[0084] Some designs accelerate the change of a slower-changing node in the loop during load changes by altering circuit states or compensation parameters. For example, this could involve increasing the slew rate (SR) of the COMP node at the error amplifier output or increasing the bandwidth of the COMP node. Corresponding to these two approaches are Slew Rate Enhancement (SRE) and Variable Compensation (DCC) techniques. These techniques essentially improve dynamic performance by increasing the loop bandwidth under load, which may lead to decreased reliability and stability issues in the design. Furthermore, they still require waiting for the error amplifier output signal to change, thus introducing a delay.

[0085] To optimize the transient response characteristics of a fixed-frequency DC-DC converter and reduce the undershoot voltage of the power supply system during loading, this disclosure provides a fixed-frequency DC-DC converter, as illustrated in the exemplary circuit block diagram below. Figure 4 As shown, it includes: a PWM drive circuit, an upper power transistor M1, a lower power transistor M2, an output circuit, a comparator circuit, a transient enhancement circuit, and an OR gate;

[0086] The PWM drive circuit is configured to generate a PWM signal based on the output signal of the OR gate, and to generate a first drive signal for the upper power transistor M1 and a second drive signal for the lower power transistor M2 based on the PWM signal; the upper power transistor M1 is the upper transistor, i.e., the high-side MOSFET, and the lower power transistor M2 is the lower transistor.

[0087] The PWM drive circuit is coupled to the control terminal of the upper power transistor M1 and the control terminal of the lower power transistor M2 respectively. The first terminal of the upper power transistor M1 is coupled to the input voltage terminal Vin, and the second terminal of the upper power transistor M1 is coupled to the second terminal of the lower power transistor M2 through the first node. The first terminal of the lower power transistor M2 is grounded.

[0088] The first terminal of the output circuit is coupled to the first node SW(N1), the second terminal of the output circuit is coupled to the first terminal of the comparator circuit via the second node FB(N2), the third terminal of the output circuit is grounded, the second terminal of the comparator circuit is coupled to the first input terminal of the OR gate, and the comparator circuit is configured to generate a pulse width modulation signal based on the output feedback voltage generated by the output circuit.

[0089] The first terminal of the transient enhancement circuit is coupled to the second node FB(N2), and the second terminal of the transient enhancement circuit is coupled to the second input terminal of the OR gate. The transient enhancement circuit is configured to generate a first ripple voltage, and to superimpose the output feedback voltage on the second node FB(N2) with the first ripple voltage to generate a second ripple voltage ripple. The generated second ripple voltage ripple is then compared with a reference voltage Ref_ripple of the second ripple voltage to obtain a comparison signal. The duty cycle of the first ripple voltage is related to the duty cycle of the PWM signal, the frequency of the first ripple voltage is consistent with the frequency of the PWM signal, and the duty cycle of the first ripple voltage is consistent with the duty cycle of the PWM signal.

[0090] The OR gate is configured to output a signal to the PWM drive circuit based on the pulse width modulation signal and the comparison signal output by the transient enhancement circuit.

[0091] This disclosure solves the problem in related technologies where, when optimizing transient response, fixed-frequency DC-DC converters need to wait for changes in the output signal of the error amplifier with a small bandwidth in the loop during load changes, resulting in a delay.

[0092] An exemplary circuit diagram of the fixed-frequency DC-DC converter provided in this disclosure is shown below. Figure 5 As shown, the PWM drive circuit includes an oscillator, a PWM logic circuit, and a driver. Figure 5 In the diagram, PWM LOGIC refers to the PWM logic circuit, Driver refers to the driver, and the first loop information / reference and the second loop information / reference are signals generated by real-time acquisition of reference loop information. The first loop information / reference, the second loop information / reference and the reference are different.

[0093] The oscillator is configured to output an oscillation signal to the PWM logic circuit according to a fixed-frequency clock.

[0094] The first terminal of the PWM logic circuit is coupled to the oscillator, and the second terminal of the PWM logic circuit is coupled to the output terminal of the OR gate. The PWM logic circuit is configured to perform pulse width modulation according to the oscillation signal and the output signal of the OR gate, and output a PWM signal to the driver.

[0095] The driver is configured to output a first drive signal for the upper power transistor M1 and a second drive signal for the lower power transistor M2 according to the PWM signal.

[0096] Figure 5 In the exemplary circuit diagram of the fixed-frequency DC-DC converter shown, the output circuit includes an inductor L, an output capacitor Cout, a first feedback resistor Rfb1, and a second feedback resistor Rfb2.

[0097] The first end of the inductor L is coupled to the first node SW(N1) between the upper power transistor M1 and the lower power transistor M2. The second end of the inductor L is coupled to the first end of the output capacitor Cout and the first end of the first feedback resistor Rfb1 respectively. The inductor L is configured to store energy when the upper power transistor M1 is turned on.

[0098] The second end of the first feedback resistor Rfb1 is coupled to the first end of the second feedback resistor Rfb2 via the second node FB(N2), and the second node FB(N2) is used to generate the output feedback voltage.

[0099] The second terminal of the output capacitor Cout and the second terminal of the second feedback resistor Rfb2 are respectively grounded.

[0100] Figure 5 In the exemplary circuit diagram of the fixed-frequency DC-DC converter shown, the comparator circuit includes an error amplifier and a pulse width modulation comparator;

[0101] The input of the error amplifier is coupled to the second node FB(N2), and the output of the error amplifier is coupled to the input of the pulse width modulation comparator. The error amplifier is configured to compare the output feedback voltage of the second node FB(N2) with the reference voltage Ref_FB of the output feedback voltage, and output the error integration result to the pulse width modulation comparator. The reference voltage Ref_FB of the output feedback voltage is provided by a fixed-frequency DC-DC converter. Figure 5 The reference in the output feedback voltage is the reference voltage Ref_FB;

[0102] The output of the pulse width modulation comparator is coupled to the first input of the OR gate. The pulse width modulation comparator is configured to compare the output signal of the error amplifier and the reference voltage of the output signal, and output the pulse width modulation signal to the OR gate. The PWM drive circuit, the upper power transistor M1, the lower power transistor M2, the output circuit, the comparator circuit, and the OR gate form a loop. Figure 5 The first loop information / reference is the reference voltage of the output signal, which is generated by real-time acquisition of loop information.

[0103] The loop can be voltage-mode, current-mode, or V-mode. 2 Control, V 2 C-control or other fixed-frequency control systems.

[0104] Figure 5 In the exemplary circuit diagram of the fixed-frequency DC-DC converter shown, the transient enhancement circuit includes a ripple generation circuit and a comparator; Figure 5 In this context, Ripple generation is the ripple generation circuit, and Comparator is the comparator.

[0105] The first terminal of the ripple generation circuit is coupled to the output feedback voltage, and the second terminal of the ripple generation circuit is coupled to the first input terminal of the comparator. The ripple generation circuit is configured to generate a first ripple voltage, generate a second ripple voltage based on the first ripple voltage and the output feedback voltage, and output the second ripple voltage to the comparator.

[0106] The reference voltage Ref_ripple of the second ripple voltage is input through the second input terminal of the comparator. The comparator is configured to output a comparison signal to the OR gate. When the second ripple voltage ripple is less than or equal to the reference voltage Ref_ripple, the comparison signal output to the OR gate is at an active level. When the comparison signal is active, the upper power transistor M1 is continuously turned on until the second ripple voltage ripple is greater than the reference voltage Ref_ripple or the maximum duty cycle limit is triggered. When the second ripple voltage ripple is greater than the reference voltage Ref_ripple, the comparison signal output to the OR gate is at an inactive level. Figure 5 The second loop information / reference is the reference voltage Ref_ripple of the second ripple voltage. When the second ripple voltage ripple is less than or equal to the reference voltage Ref_ripple, the comparison signal is valid and the upper power transistor M1 is continuously turned on. When the second ripple voltage ripple is greater than the reference voltage Ref_ripple, the comparison signal is invalid. By setting the comparator and its two input terminals, the comparison signal can be at a high level when it is valid.

[0107] This disclosure adds a transient enhancement circuit to the loop structure of most conventional fixed-frequency DC-DC converters. This accelerates the transient response of the power system under increased load without waiting for changes in the error amplifier output. Simultaneously, it does not disrupt the original loop characteristics during steady-state operation, only participating in regulation during loading. Most importantly, this disclosure does not disrupt the fixed-frequency operation of the loop when intervening in control, facilitating the design of system EMI.

[0108] In one optional embodiment of this disclosure, a second ripple voltage ripple can be generated using the first node SW(N1). An exemplary circuit diagram of the ripple generation circuit is shown below. Figure 6 As shown, the ripple generation circuit includes a first resistor R1, a first capacitor C1, a DC value extractor, a first adder, an amplifier, a second adder, and a first buffer buffer1. Figure 6 In the diagram, DC value extractor is a DC value extractor, k is an amplifier, indicating that the signal is amplified by k times, and ripple is the second ripple voltage.

[0109] The first end of the first resistor R1 is coupled to the first node SW(N1) between the upper power transistor M1 and the lower power transistor M2, and the second end of the first resistor R1 is coupled to the first input terminal of the first adder via the third node N3.

[0110] The first terminal of the first capacitor C1 is coupled to the third node N3, and the second terminal of the first capacitor C1 is grounded.

[0111] The input terminal of the DC value extractor is coupled to the third node N3, and the output terminal of the DC value extractor is coupled to the second input terminal of the first adder.

[0112] The output of the first adder is coupled to the input of the amplifier. The first adder is configured to remove the DC signal from the signal from the third node N3 and output the AC signal from the signal of the third node N3 to the amplifier. The duty cycle of the AC signal is related to the duty cycle of the PWM signal. In this embodiment, the first ripple voltage can be the AC signal.

[0113] The output of the amplifier is coupled to the first input of the second adder. The amplifier is configured to amplify the AC signal by a factor of k before outputting it to the second adder.

[0114] The first end of the first buffer buffer1 is coupled to the output feedback voltage, and the second end of the first buffer buffer1 is coupled to the second input end of the second adder;

[0115] The second adder is configured to superimpose the amplified AC signal (by a factor of k) and the output feedback voltage, thereby generating a second ripple voltage through the output of the second adder.

[0116] In one optional embodiment of this disclosure, a charge pump can also be used to generate the second ripple voltage. An exemplary circuit block diagram of the ripple generation circuit is shown below. Figure 7 As shown, an exemplary circuit diagram of the ripple generation circuit is as follows: Figure 8 As shown, the ripple generation circuit includes a DC level generation circuit, a triangular wave generation circuit, and a signal superposition circuit.

[0117] The first terminal of the DC level generation circuit is coupled to the output feedback voltage, and the second terminal of the DC level generation circuit is coupled to the first input terminal of the signal superposition circuit. The DC level generation circuit is configured to generate a DC level based on the output feedback voltage of the second node FB(N2).

[0118] A PWM signal is input through the first terminal of the triangular wave generation circuit, and the second terminal of the triangular wave generation circuit is coupled to the second input terminal of the signal superposition circuit. The triangular wave generation circuit is configured to generate a triangular wave with a corresponding duty cycle according to the duty cycle of the PWM signal. In this embodiment, the first ripple voltage can be a triangular wave.

[0119] The output of the signal superposition circuit is coupled to the fourth node N4. The signal superposition circuit is configured to superimpose a DC level and a triangular wave to generate a second ripple voltage.

[0120] exist Figure 8 In the exemplary circuit diagram of the ripple generation circuit shown, the DC level generation circuit includes a second buffer 2, a second resistor R2, and a second capacitor C2.

[0121] Among them, the first end of the second buffer 2 is coupled to the output feedback voltage, and the second end of the second buffer 2 is coupled to the first end of the second resistor R2.

[0122] The second end of the second resistor R2 is coupled to the first end of the second capacitor C2, and the second resistor R2 is configured to generate a DC level.

[0123] The second terminal of the second capacitor C2 is grounded;

[0124] The triangular wave generating circuit includes a second transconductance amplifier gm2, an inverter, a switch K, and a third capacitor C3;

[0125] The non-inverting input of the second transconductance amplifier gm2 is coupled to the second reference voltage terminal Ref_2, the inverting input of the second transconductance amplifier gm2 is grounded, the current input of the second transconductance amplifier gm2 is coupled to the power supply voltage terminal VCC, the output of the second transconductance amplifier gm2 is coupled to the fifth node N5, and the second transconductance amplifier gm2 is configured to generate a triangular wave at the fifth node N5.

[0126] A PWM signal is input through the first terminal of the inverter, and the second terminal of the inverter is coupled to the first terminal of the switch K. When the output signal of the second terminal of the inverter is high, the switch K is closed; otherwise, the switch K is open.

[0127] The second terminal of switch K is coupled to the fifth node N5, and the third and fourth terminals of switch K are grounded.

[0128] The first terminal of the third capacitor C3 is coupled to the fifth node N5, and the second terminal of the third capacitor C3 is grounded.

[0129] The signal superposition circuit includes a first transconductance amplifier gm1, a third resistor R3, and a third transconductance amplifier gm3;

[0130] The non-inverting input terminal of the first transconductance amplifier gm1 is coupled to the second terminal of the second resistor R2 and the first terminal of the second capacitor C2, respectively. The inverting input terminal of the first transconductance amplifier gm1 is coupled to the first reference voltage terminal Ref_1. The current input terminal of the first transconductance amplifier gm1 is coupled to the power supply voltage terminal VCC. The output terminal of the first transconductance amplifier gm1 is coupled to the first terminal of the third resistor R3 and the fourth node N4, respectively.

[0131] The second terminal of the third resistor R3 is grounded;

[0132] The non-inverting input of the third transconductance amplifier gm3 is coupled to the fifth node N5, the inverting input of the third transconductance amplifier gm3 is grounded, the current input of the third transconductance amplifier gm3 is coupled to the power supply voltage VCC, and the output of the third transconductance amplifier gm3 is coupled to the fourth node N4. The third transconductance amplifier gm3 is configured to superimpose a DC level and a triangular wave at the fourth node N4 to generate the second ripple voltage ripple.

[0133] In the ripple generation circuit using the charge pump method in this embodiment, the second reference voltage input through the second reference voltage terminal Ref_2, the second transconductance amplifier gm2, and the third transconductance amplifier gm3 are used to change the magnitude of the second ripple voltage ripple, thereby controlling the speed of the transient response.

[0134] In one optional embodiment of this disclosure, an exemplary circuit diagram of the reference voltage generation circuit for the second ripple voltage is shown below. Figure 9 As shown, the reference voltage Ref_ripple generation circuit for the second ripple voltage includes a fourth transconductance amplifier gm4 and a fourth resistor R4.

[0135] The reference voltage Ref_FB for the output feedback voltage is input through the non-inverting input terminal of the fourth transconductance amplifier gm4, the inverting input terminal of the fourth transconductance amplifier gm4 is coupled to the first reference voltage terminal Ref_1, the current input terminal of the fourth transconductance amplifier gm4 is coupled to the power supply voltage terminal VCC, and the output terminal of the fourth transconductance amplifier gm4 is coupled to the first terminal of the fourth resistor R4. The fourth transconductance amplifier gm4 is configured to generate the reference voltage Ref_ripple for the second ripple voltage; wherein, the reference voltage Ref_FB for the output feedback voltage is provided by the fixed-frequency DC-DC converter itself;

[0136] The second terminal of the fourth resistor R4 is grounded.

[0137] The reference voltage compared to the second ripple voltage can be generated from the circuit's reference by adding loop input / output information, or it can be provided by the embodiments of this disclosure. Figure 9 The circuit shown generates the output feedback voltage using the reference voltage Ref_FB. Figure 9 In this design, the reference voltage Ref_ripple of the second ripple voltage is fixed, and the transient enhancement characteristics can better support low duty cycle applications.

[0138] When a charge pump is used to generate the second ripple voltage, the circuit diagram of the ripple generation circuit is as follows: Figure 8 As shown, the circuit diagram of the reference voltage generation circuit for the second ripple voltage is as follows: Figure 9 As shown, Figure 9 and Figure 8 The parameters of the components used are the same. Figure 9 The fourth transconductance amplifier gm4 and Figure 8 The parameters of the first transconductance amplifier gm1 are the same. Figure 9 The fourth resistor R4 and Figure 8 The resistance value of the third resistor R3 is the same, and the inverting input terminal is always coupled to the first reference voltage terminal Ref_1. Therefore, there is no need to generate a second ripple voltage reference voltage Ref_ripple, which can reduce system error.

[0139] Based on the above embodiments, in a preferred embodiment of this disclosure, an exemplary circuit diagram of the reference voltage generation circuit for the second ripple voltage is as follows: Figure 10 As shown, except Figure 9 In addition to the structure shown, the reference voltage Ref_ripple generation circuit for the second ripple voltage also includes a fifth transconductance amplifier gm5;

[0140] The voltage input to the non-inverting input of the fifth transconductance amplifier gm5 is related to the ratio of the output voltage Vout to the input voltage Vin in the loop. The inverting input of the fifth transconductance amplifier gm5 is grounded. The current input of the fifth transconductance amplifier gm5 is coupled to the power supply voltage VCC. The output of the fifth transconductance amplifier gm5 is coupled to the first terminal of the fourth resistor R4.

[0141] When the power supply system is operating normally, the schematic diagram of the second ripple voltage ripple and the reference voltage Ref_ripple of the second ripple voltage is as follows: Figure 11 As shown, Figure 11 In this context, H represents the amplitude of the second ripple voltage, Z1 represents the maximum value of the second ripple voltage, and the difference between the reference voltage Ref_ripple of the second ripple voltage. The expression for the amplitude H of the second ripple voltage is:

[0142] H = k × DT

[0143] Where k is the slope of the second ripple voltage, D is the duty cycle, and T is the period;

[0144] according to Figure 8From the exemplary circuit diagram of the ripple generation circuit shown, the slope k of the second ripple voltage ripple can be derived as:

[0145]

[0146] Where Ref_2 is the second reference voltage at the second reference voltage terminal, gm2 is the transconductance coefficient of the second transconductance amplifier, C3 is the capacitance value of the third capacitor, gm3 is the transconductance coefficient of the third transconductance amplifier, and R3 is the resistance value of the third resistor;

[0147] Combining the above formula, the amplitude H of the second ripple voltage ripple can be obtained as:

[0148]

[0149] Where Vout is the output voltage and Vin is the input voltage;

[0150] according to Figure 10 From the circuit diagram of the reference voltage generation circuit for the second ripple voltage shown, we can derive:

[0151]

[0152] Where gm5 is the transconductance coefficient of the fifth transconductance amplifier, R4 is the resistance value of the fourth resistor, and V in_gm5 The voltage input to the non-inverting input terminal of the fifth transconductance amplifier gm5;

[0153] According to the above formula, the voltage V input to the non-inverting input terminal of the fifth transconductance amplifier gm5 is... in_gm5 for:

[0154]

[0155] Where Z1 and Z2 are both constants, It determines the transient response speed to a certain extent.

[0156] As can be seen from the above formula, Figure 10 In this circuit, the reference voltage Ref_ripple of the second ripple voltage is not fixed, but is related to the ratio of the output voltage Vout to the input voltage Vin. The transient enhancement characteristics can cover both high duty cycle and low duty cycle applications well.

[0157] The following is combined Figure 5 The exemplary circuit diagram of the fixed-frequency DC-DC converter shown is as follows: Figure 12 The diagram shown illustrates the working principle of the transient enhancement technology in the fixed-frequency DC-DC converter, thus explaining the working principle of the fixed-frequency DC-DC converter provided in this embodiment.

[0158] When the power supply system is running normally, when the pulse width modulation comparator in the loop controls the power transistor M1 to turn off, the second ripple voltage ripple is higher than the reference voltage Ref_ripple of the second ripple voltage. The transient enhancement circuit does not intervene in the loop, and the loop operates with its original characteristics.

[0159] When the load load increases and the output voltage Vout drops, if the switching signal for the upper power transistor M1 controlled by the loop to switch from on to off is issued from the pulse width modulation comparator, and the second ripple voltage ripple is still lower than the reference voltage Ref_ripple of the second ripple voltage, then the transient enhancement circuit intervenes to control and continues to turn on the upper power transistor M1 until the second ripple voltage ripple is higher than the reference voltage Ref_ripple of the second ripple voltage or the maximum duty cycle limit is triggered. At this time, the upper power transistor M1 is turned off and waits for the next clock cycle.

[0160] During the period when the transient enhancement technology is involved, the loop self-adjusts until the second ripple voltage ripple is higher than the reference voltage Ref_ripple of the second ripple voltage. Then the loop takes over control again, and the transient enhancement technology naturally exits.

[0161] Taking Vin = 12V, Vout = 1V, and a load step change of 1A to 16A taking 15μs as an example, transient simulation was performed. The simulation results of transient response with and without transient enhancement circuit are as follows: Figures 13 to 15 As shown, the transient response simulation results with transient enhancement circuitry are as follows: Figure 13 As shown, the transient response simulation results without the transient enhancement circuit are as follows: Figure 14 As shown, the simulation comparison of the output voltage transient response with and without transient boosting circuitry is as follows: Figure 15 As shown;

[0162] Under the same conditions, after adding a transient enhancement circuit, the on-time of the power transistor is significantly increased during the loading process after the transient enhancement technology is applied. Figures 13 to 15 The simulation results show that the drop in output voltage Vout1 with the transient enhancement circuit is 45mV, which is 75% less than the drop in output voltage Vout2 without the transient enhancement circuit. This significantly reduces the drop in output voltage Vout and decreases the undershoot voltage of the power supply system during loading. Therefore, the transient enhancement technology used in the fixed-frequency DC-DC converter with transient enhancement circuit provided in this embodiment can effectively accelerate the transient response of the load.

[0163] This disclosure also provides a chip that includes a fixed-frequency DC-DC converter according to embodiments of this disclosure. This chip can be a chip that requires fast transient response to server power supplies.

[0164] This disclosure also provides an electronic device that includes a chip according to embodiments of this disclosure. The electronic device may be a communication device or an in-vehicle electronic device.

[0165] As can be seen from the above description, this disclosure achieves the following technical effects:

[0166] This disclosure uses a transient enhancement circuit to output a comparison signal that continuously turns on the upper power transistor to an OR gate. When the load increases and the first comparison signal is a switching signal that controls the upper power transistor to switch from on to off, the second comparison signal is at an active level. This can accelerate the transient response of the load during load changes without waiting for the output signal of the error amplifier with a small bandwidth in the loop to change. This solves the problem of delay in the optimization of transient response of fixed-frequency DC-DC converters in related technologies, where it is necessary to wait for the output signal of the error amplifier with a small bandwidth in the loop to change during load changes.

[0167] The fixed-frequency DC-DC converter disclosed herein adds a transient enhancement circuit to the loop structure, which can accelerate the transient response of the power supply system when the load increases, without waiting for the error amplifier output to change; at the same time, it does not destroy the original loop characteristics during steady-state operation, and only participates in regulation during the loading process. Furthermore, this disclosure does not disrupt the fixed-frequency operation characteristics of the loop when intervening in control, which provides convenience for the design of system EMI.

[0168] The transient enhancement technology employed in this disclosure significantly reduces the output voltage drop and decreases the undershoot voltage of the power supply system during loading, thereby effectively accelerating the transient response of the load.

[0169] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0170] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusive. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0171] Further aspects and scope will become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for illustrative purposes only and are not intended to limit the scope of this application.

[0172] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A fixed-frequency DC-DC converter, characterized in that, include: PWM drive circuit, upper power transistor, lower power transistor, output circuit, comparator circuit, transient enhancement circuit, and OR gate; The PWM drive circuit is configured to generate a PWM signal based on the output signal of the OR gate, and to generate a first drive signal for the upper power transistor and a second drive signal for the lower power transistor based on the PWM signal. The comparator circuit is configured to generate a pulse width modulation signal based on the output feedback voltage generated by the output circuit. The transient enhancement circuit is configured to generate a first ripple voltage, superimpose the output feedback voltage and the first ripple voltage to generate a second ripple voltage, and compare the generated second ripple voltage with a reference voltage of the second ripple voltage to obtain a comparison signal, wherein the duty cycle of the first ripple voltage is related to the duty cycle of the PWM signal; and The OR gate is configured to output a signal to the PWM drive circuit based on the pulse width modulation signal and the comparison signal output by the transient enhancement circuit; The transient enhancement circuit includes a ripple generation circuit and a comparator; The first terminal of the ripple generation circuit is coupled to the output feedback voltage, and the second terminal of the ripple generation circuit is coupled to the first input terminal of the comparator. The ripple generation circuit is configured to generate a first ripple voltage, generate a second ripple voltage based on the first ripple voltage and the output feedback voltage, and output the second ripple voltage to the comparator. The comparator is configured to output a comparison signal to the OR gate when the second ripple voltage is less than or equal to the reference voltage of the second ripple voltage, and when the second ripple voltage is greater than the reference voltage of the second ripple voltage, the comparison signal output to the OR gate is at an active level.

2. The fixed-frequency DC-DC converter according to claim 1, characterized in that, The PWM drive circuit includes an oscillator, PWM logic circuit, and a driver; The oscillator is configured to output an oscillation signal to the PWM logic circuit; The first terminal of the PWM logic circuit is coupled to the oscillator, and the second terminal of the PWM logic circuit is coupled to the output terminal of the OR gate. The PWM logic circuit is configured to perform pulse width modulation based on the oscillation signal and the output signal of the OR gate, and output a PWM signal to the driver. The driver is configured to output a first drive signal for the upper power transistor and a second drive signal for the lower power transistor according to the PWM signal.

3. The fixed-frequency DC-DC converter according to claim 1, characterized in that, The output circuit includes an inductor, an output capacitor, a first feedback resistor, and a second feedback resistor. The first end of the inductor is coupled to a first node between the upper power transistor and the lower power transistor, and the second end of the inductor is coupled to the first end of the output capacitor and the first end of the first feedback resistor, respectively. The inductor is configured to store energy when the upper power transistor is turned on. The second end of the first feedback resistor is coupled to the first end of the second feedback resistor via a second node, the second node being used to generate the output feedback voltage; The second terminal of the output capacitor and the second terminal of the second feedback resistor are respectively grounded.

4. The fixed-frequency DC-DC converter according to claim 1, characterized in that, The comparison circuit includes an error amplifier and a pulse width modulation comparator; The input terminal of the error amplifier is coupled to the output feedback voltage, and the output terminal of the error amplifier is coupled to the input terminal of the pulse width modulation comparator. The error amplifier is configured to compare the output feedback voltage with a reference voltage of the output feedback voltage and output the error integration result to the pulse width modulation comparator. The reference voltage of the output feedback voltage is provided by the fixed-frequency DC-DC converter. The output terminal of the pulse width modulation comparator is coupled to the first input terminal of the OR gate. The pulse width modulation comparator is configured to compare the output signal of the error amplifier with the reference voltage of the output signal and output the pulse width modulation signal to the OR gate. The PWM drive circuit, the upper power transistor, the lower power transistor, the output circuit, the comparator circuit, and the OR gate form a loop. The reference voltage of the output signal is generated by real-time acquisition of loop information.

5. The fixed-frequency DC-DC converter according to claim 1, characterized in that, The ripple generation circuit includes a first resistor, a first capacitor, a DC value extractor, a first adder, an amplifier, a second adder, and a first buffer. The first end of the first resistor is coupled to the first node between the upper power transistor and the lower power transistor, and the second end of the first resistor is coupled to the first input terminal of the first adder via the third node. The first terminal of the first capacitor is coupled to the third node, and the second terminal of the first capacitor is grounded. The input terminal of the DC value extractor is coupled to the third node, and the output terminal of the DC value extractor is coupled to the second input terminal of the first adder. The output of the first adder is coupled to the input of the amplifier. The first adder is configured to remove the DC signal from the signal from the third node and output the AC signal from the signal of the third node to the amplifier. The output of the amplifier is coupled to the first input of the second adder, and the amplifier is configured to amplify the AC signal by a factor of k before outputting it to the second adder; The first terminal of the first buffer is coupled to the output feedback voltage, and the second terminal of the first buffer is coupled to the second input terminal of the second adder; The second adder is configured to superimpose the amplified AC signal (by a factor of k) and the output feedback voltage, thereby generating a second ripple voltage through the output of the second adder.

6. The fixed-frequency DC-DC converter according to claim 1, characterized in that, The ripple generation circuit includes a DC level generation circuit, a triangular wave generation circuit, and a signal superposition circuit. The first terminal of the DC level generation circuit is coupled to the output feedback voltage, and the second terminal of the DC level generation circuit is coupled to the first input terminal of the signal superposition circuit. The DC level generation circuit is configured to generate a DC level based on the output feedback voltage. The PWM signal is input through the first terminal of the triangular wave generating circuit, and the second terminal of the triangular wave generating circuit is coupled to the second input terminal of the signal superposition circuit. The triangular wave generating circuit is configured to generate a triangular wave with a corresponding duty cycle according to the duty cycle of the PWM signal. The output of the signal superposition circuit is coupled to the fourth node. The signal superposition circuit is configured to superimpose the DC level and the triangular wave to generate a second ripple voltage.

7. The fixed-frequency DC-DC converter according to claim 6, characterized in that, The DC level generation circuit includes a second buffer, a second resistor, and a second capacitor; Wherein, the first end of the second buffer is coupled to the output feedback voltage, and the second end of the second buffer is coupled to the first end of the second resistor; The second end of the second resistor is coupled to the first end of the second capacitor, and the second resistor is configured to generate a DC level; The second terminal of the second capacitor is grounded; The triangular wave generating circuit includes a second transconductance amplifier, an inverter, a switch, and a third capacitor; Wherein, the non-inverting input terminal of the second transconductance amplifier is coupled to the second reference voltage terminal, the inverting input terminal of the second transconductance amplifier is grounded, the current input terminal of the second transconductance amplifier is coupled to the power supply voltage terminal, the output terminal of the second transconductance amplifier is coupled to the fifth node, and the second transconductance amplifier is configured to generate a triangular wave at the fifth node; The PWM signal is input through the first terminal of the inverter, and the second terminal of the inverter is coupled to the first terminal of the switch. The second terminal of the switch is coupled to the fifth node, and the third and fourth terminals of the switch are grounded. The first terminal of the third capacitor is coupled to the fifth node, and the second terminal of the third capacitor is grounded. The signal superposition circuit includes a first transconductance amplifier, a third resistor, and a third transconductance amplifier; Wherein, the non-inverting input terminal of the first transconductance amplifier is coupled to the second terminal of the second resistor and the first terminal of the second capacitor, the inverting input terminal of the first transconductance amplifier is coupled to the first reference voltage terminal, the current input terminal of the first transconductance amplifier is coupled to the power supply voltage terminal, and the output terminal of the first transconductance amplifier is coupled to the first terminal of the third resistor and the fourth node. The second terminal of the third resistor is grounded; The non-inverting input of the third transconductance amplifier is coupled to the fifth node, the inverting input of the third transconductance amplifier is grounded, the current input of the third transconductance amplifier is coupled to the power supply voltage terminal, and the output of the third transconductance amplifier is coupled to the fourth node. The third transconductance amplifier is configured to superimpose the DC level and the triangular wave at the fourth node to generate a second ripple voltage.

8. The fixed-frequency DC-DC converter according to claim 1, characterized in that, The reference voltage generation circuit for the second ripple voltage includes a fourth transconductance amplifier and a fourth resistor; The reference voltage for the output feedback voltage is input through the non-inverting input terminal of the fourth transconductance amplifier, the inverting input terminal of the fourth transconductance amplifier is coupled to the first reference voltage terminal, the current input terminal of the fourth transconductance amplifier is coupled to the power supply voltage terminal, the output terminal of the fourth transconductance amplifier is coupled to the first terminal of the fourth resistor, and the fourth transconductance amplifier is configured to generate the reference voltage for the second ripple voltage. The second terminal of the fourth resistor is grounded.

9. The fixed-frequency DC-DC converter according to claim 8, characterized in that, The reference voltage generation circuit for the second ripple voltage also includes a fifth transconductance amplifier; The voltage related to the ratio of the output voltage to the input voltage in the loop is input through the non-inverting input terminal of the fifth transconductance amplifier. The inverting input terminal of the fifth transconductance amplifier is grounded. The current input terminal of the fifth transconductance amplifier is coupled to the power supply voltage terminal. The output terminal of the fifth transconductance amplifier is coupled to the first terminal of the fourth resistor.

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