A dimming glass multi-zone drive system and vehicle

Abstract

This invention discloses a multi-zone driving system for dimming glass and a vehicle, including an MCU chip, a first logic conversion circuit, a second logic conversion circuit, a first half-bridge driving circuit, a second half-bridge driving circuit, and a filtering circuit. The MCU chip outputs two pulse signals to the first and second logic conversion circuits respectively. The first logic conversion circuit inverts one set of pulse signals and directly outputs multiple sets of pulse signals to the first half-bridge driving circuit. These multiple sets of pulse signals are filtered by the filtering circuit and then output to the PDLC dimming glass. The second logic conversion circuit inverts another set of pulse signals and outputs multiple sets of pulse signals to the first and second terminals of the second half-bridge driving circuit. The required commutation level is generated by the conduction and cutoff relationship between the first and second terminals and then directly output to the PDLC dimming glass. This system effectively simplifies the structure of the driving circuit and improves the reliability of the PDLC dimming glass driving circuit.

Description

Technical Field

[0001] This invention relates to automobile manufacturing, and more specifically to a multi-drive scheme for automotive dimming glass. Background Technology

[0002] Smart glass is a new type of glass that incorporates a smart glass film between two layers of glass, forming a laminated structure that is integrally molded under high temperature and pressure. Users can flexibly control the glass's haze and adjust the visibility of the car window through a light sensor, a hollow screen, voice control, or a knob to adjust the voltage and protect the privacy of occupants.

[0003] See Figures 1-2 The description is an example of the current mainstream dimming glass driving circuit. The current mainstream dimming glass driving circuit generally uses a MOSFET or equivalent chip to form an inverter bridge, which converts the SPWM (sinusoidal pulse width modulation) signal generated by the MCU into the AC SPWM required by the load, and then uses an LC filter circuit to convert the SPWM signal into a sinusoidal AC signal.

[0004] The dimming glass drive circuit with this structure has the following drawbacks in practical applications:

[0005] (1) The inverter bridge has a complex structure and requires a dedicated half-bridge or full-bridge driver chip (such as two sets of driver chips, along with MOSFETs Q1, Q2, Q3 and Q4), which is relatively expensive.

[0006] (2) Due to the characteristics of the inverter bridge, it will output two SPWM signals. Therefore, two sets of LC circuits are required to obtain the required sinusoidal AC signal. In addition, the filter circuit is located at the output end, which has certain requirements for the filter inductor and the cost is relatively high.

[0007] (3) If multiple SPWM (sinusoidal pulse width modulation) signals are required to control the structure that requires multiple drives, then a powerful chip is needed, and higher requirements are also placed on the software control.

[0008] As can be seen from the above, the existing dimming glass driving circuit is complex and relatively expensive. Therefore, how to effectively reduce the structure and cost of PDLC dimming glass driving circuit and improve its reliability is a problem that needs to be solved in this field. Summary of the Invention

[0009] To address the technical problems of complex structure and relatively high cost of existing dimming glass drive circuits, the present invention aims to provide a dimming glass multi-zone drive system. This system effectively simplifies the structure of the drive circuit, improves the reliability of the PDLC dimming glass drive circuit, and overcomes the problems existing in the prior art. On this basis, the present invention also provides a vehicle using this dimming glass multi-zone drive system.

[0010] To achieve the above objectives, this solution provides a dimming glass multi-zone driving system, including an MCU chip, a first logic conversion circuit, at least one set of second logic conversion circuits, a first half-bridge driving circuit, a second half-bridge driving circuit, and a filtering circuit. The signal output terminal of the MCU chip outputs two pulse signals, which are directly input to the first logic conversion circuit and the second logic conversion circuit, respectively.

[0011] The first logic conversion circuit flips a set of pulse signals and directly outputs multiple sets of pulse signals to the first half-bridge drive circuit. The first half-bridge drive circuit filters the multiple sets of pulse signals through the filter circuit and outputs them to the PDLC dimming glass.

[0012] The second logic conversion circuit flips another set of pulse signals and directly outputs multiple sets of pulse signals to the second half-bridge drive circuit. The second half-bridge drive circuit includes a first terminal and a second terminal. The multiple sets of pulse signals are respectively input to the first terminal and the second terminal of the second half-bridge drive circuit. The required commutation level is generated through the conduction and cutoff relationship of the first terminal and the second terminal of the second half-bridge drive circuit, and directly output to the PDLC dimming glass.

[0013] Furthermore, the MCU chip generates SPWM signal and PWM signal in a time-division multiplexing manner. The SPWM signal is converted into SPWM1 signal and SPWM2 signal after phase inversion after passing through the first logic conversion circuit. The PWM signal is converted into PWM1 signal and PWM2 signal after phase inversion after passing through the second logic conversion circuit.

[0014] Furthermore, the first logic conversion circuit and the second logic conversion circuit each include several gate circuits, which convert one pulse signal generated by the MCU chip into two pulse signals by flipping the pulse signal.

[0015] Furthermore, the first logic conversion circuit and the second logic conversion circuit are respectively provided with a delay circuit. The delay circuit includes a first resistor and a first capacitor. The output terminal of the first resistor is connected to the input terminal of the first capacitor and is set in the first logic conversion circuit. The second logic conversion circuit flips and outputs either of the two pulse signals. The dead time between SPWM1 and SPWM2, and between PWM1 and PWM2, is adjusted by adjusting the values ​​of the first resistor and the first capacitor.

[0016] Furthermore, the output lines of the first logic conversion circuit and the second logic conversion circuit are each equipped with a plurality of Schmitt trigger inverters, which stabilize the output signals in the output lines of the first logic conversion circuit and the second logic conversion circuit.

[0017] Furthermore, the first half-bridge driving circuit includes a driving chip, a first MOSFET and a second MOSFET. The input terminal of the driving chip is connected to the first logic conversion circuit, and the output terminal is connected to the gate of the first MOSFET and the gate of the second MOSFET respectively. The source and drain of the first MOSFET and the second MOSFET are output to the filter circuit.

[0018] Furthermore, the output of the second logic conversion circuit can be equipped with multiple AND gate circuits in parallel to realize the output of multiple commutation level output circuits.

[0019] Furthermore, the multiple sets of commutation level output circuits are arranged in parallel at the output terminal of the second logic conversion circuit.

[0020] Furthermore, the second half-bridge driving circuit includes an N-channel MOS transistor circuit and a P-channel MOS transistor circuit. The input terminals of the N-channel MOS transistor circuit and the P-channel MOS transistor circuit are respectively connected to the two signals after phase inversion by the second logic conversion circuit, and the output terminal outputs the commutation level directly to the dimming glass.

[0021] To achieve the above objectives, the present invention provides a vehicle equipped with the aforementioned dimming glass multi-zone drive system.

[0022] The dimming glass multi-zone driving system provided by the present invention firstly uses a logic conversion circuit to flip the phase of one SPWM signal and the PWM signal generated by the MCU into several groups, which can greatly save MCU resources and reduce costs for multi-channel control.

[0023] Secondly, the half-bridge in the lower bridge arm is driven by a discrete scheme. The upper end of the half-bridge uses PMOS and the lower end uses NMOS. Compared with the traditional driver chip + half-bridge, the driving method of using two NMOS can simplify the driving and greatly reduce the cost.

[0024] Finally, for the separate control of multi-zone PDLC sunroof glass, it is only necessary to add a commutation bridge arm to the output of the PWM, and control the switching of different zones only through the enable signal, which greatly saves hardware resources and reduces costs. Attached Figure Description

[0025] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0026] Figure 1 This is a schematic diagram of the existing dimming glass driving circuit.

[0027] Figure 2 This is a schematic diagram of the control logic of an existing dimming glass drive circuit.

[0028] Figure 3 This is a schematic diagram of the control logic of the multi-zone drive system for this dimming glass;

[0029] Figure 4 This is a schematic diagram of the multi-zone drive system for this dimming glass;

[0030] Figure 5 This is a schematic diagram of the logic conversion circuit in the multi-zone drive system for this dimming glass.

[0031] Figure 6 This is a waveform diagram showing the application of the delay circuit in the multi-zone drive system of this dimming glass.

[0032] Figure 7 This is a schematic diagram of the logic conversion circuit at each point in the multi-zone drive system of this dimming glass;

[0033] Figure 8 This is a schematic diagram of the partition circuit in the multi-zone drive system of this dimming glass;

[0034] Figure 9 This is a schematic diagram of the first logic conversion circuit of the partition structure in the multi-zone driving system of this dimming glass.

[0035] Figure 10 This is a schematic diagram of the logic of each point in the second logic conversion circuit of the partition structure in this dimming glass multi-zone driving system. Detailed Implementation

[0036] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below with reference to specific illustrations.

[0037] To address the problems existing in current PDLC dimming glass driving solutions, this solution provides a multi-zone driving system for dimming glass. This innovative system uses a logic conversion circuit to construct a multi-zone control circuit. An MCU chip, through an LC low-pass filter circuit, works in conjunction with this control circuit to generate a sinusoidal AC power supply from DC power for the PDLC dimming glass. This allows for zoned adjustment of the glass's light transmittance. This dimming glass driving system not only simplifies the driving circuit but also effectively improves its reliability and reduces costs.

[0038] Example 1:

[0039] See Figure 3 In this solution, the MCU chip 110 in the dimming glass multi-zone drive system is used to generate two sets of pulse signals: SPWM and PWM.

[0040] The SPWM and PWM pulse signals are converted into two phase-flipping SPWM / PWM signals by the first and second logic conversion circuits, respectively, with a certain dead time. For multi-channel control, this can greatly save MCU resources and reduce costs (because multiple SPWM / PWM signals would occupy more MCU resources and require a relatively high-specification MCU), simplify software control logic, and improve reliability.

[0041] Furthermore, the SPWM1 and SPWM2 formed after passing through the first logic conversion circuit are respectively driven by the half-bridge driver chip in the upper bridge arm so that the signal meets the voltage and current requirements of driving the half-bridge MOS transistor. Then, the two sets of half-bridges are driven to obtain two sets of SPWM waveforms that meet the requirements of driving the dimming glass. The SPWM waveform is integrated and filtered by the LC filter circuit to obtain the final output sine wave.

[0042] Simultaneously, the two signals PWM1 and PWM2 formed after the second logic conversion circuit are driven by the lower bridge arm in a discrete scheme. PWM1 and PWM2 are respectively passed through the first half-bridge terminal (P-channel MOSFET) and the second half-bridge terminal (N-channel MOSFET) in the lower bridge arm. Through the conduction and cutoff relationship of the upper half-bridge terminal (P-channel MOSFET) and the lower half-bridge terminal (N-channel MOSFET), the required commutation level is generated at the output terminal of the lower bridge arm, and the sinusoidal AC current controlling the dimming glass is directly output.

[0043] Since the lower bridge arm only performs commutation and the PDLC drive current is relatively small, the half-bridge can be driven by a discrete scheme. The upper end of the half-bridge uses PMOS (P-channel MOSFET) and the lower end uses NMOS (N-channel MOSFET). Compared with the traditional driver chip + half-bridge, the driving method of using two NMOS can simplify the driving and greatly reduce the cost.

[0044] Meanwhile, the discrete hardware driver solution combined with unipolar SPWM modulation can also greatly save PCB area, reduce controller size, reduce hardware costs in all aspects, and improve the flexibility of controller application.

[0045] Furthermore, when controlling the switching of SPWM1 and SPWM2, as well as PWM1 and PWM2 signals, a delay corresponding to the characteristics of SPWM1 and SPWM2, as well as PWM1 and PWM2 signals, is added. Based on this delay, a certain phase difference is generated between SPWM1 and SPWM2, as well as PWM1 and PWM2 signals. This phase difference is the dead time between the output SPWM1 and SPWM2, as well as PWM1 and PWM2, which is the dead time controlled by the NMOS and PMOS switches at the first and second ends of the half-bridge, thus avoiding a short circuit in the power supply caused by the simultaneous turn-on of the upper and lower MOS.

[0046] Regarding the dimming glass driving system provided by the invention, see [link to invention]. Figure 4 The following example illustrates the specific structure and functional implementation of this dimming glass drive system.

[0047] Furthermore, this embodiment does not limit the configuration of the MCU chip used, and it can be determined according to actual needs, as long as it can achieve the aforementioned functions of the MCU chip 100.

[0048] For example, the MCU chip in this example can generate SPWM pulse signals and PWM pulse signals, and directly transmit them to the corresponding first logic conversion circuit and second logic conversion circuit.

[0049] The first logic conversion circuit can convert one SPWM / PWM channel into two SPWM1 / PWM1 and SPWM2 / PWM2 channels by phase inversion.

[0050] See Figure 5The first logic conversion circuit and the second logic conversion circuit include an AND gate circuit U4 and a NOR gate circuit U5. The SPWM / PWM signals generated by the MCU chip are transmitted to the first input terminal of the AND gate circuit U4 and the second input terminal of the NOR gate circuit U5, respectively. The second input terminal of the AND gate circuit U4 is connected to the input circuit of the second input terminal of the NOR gate circuit U5, and the first input terminal of the NOR gate circuit U5 is connected to the input circuit of the first input terminal of the AND gate circuit U4. SPWM1 / PWM1 and SPWM2 / PWM2 are generated by the NOR gate circuit U5 and the AND gate circuit U4, respectively.

[0051] Meanwhile, a delay circuit is also provided in the first logic conversion circuit and the second logic conversion circuit to adjust the dead time between SPWM1 / PWM1 and SPWM2 / PWM2.

[0052] The delay circuit includes a resistor R1 and a capacitor C1. The SPWM / PWM generated by the MCU chip is directly input to the input terminal of the resistor R1. The output terminal of the resistor R1 is connected to the input terminal of the capacitor C1. The rising and falling edges of the waveform after passing through the resistor R1 and the capacitor C1 are slower than the original waveform. Therefore, the gate circuit will recognize the time when the level changes from high to low or from low to high later than the original waveform.

[0053] After passing through resistor R1 and capacitor C1, SPWM / PWM is described in detail below. Figure 6 A phase difference is generated between the waveforms at points B and C. Finally, after passing through AND and NOR gates respectively, the AND gate outputs SPWM 1 / PWM1 high only when both waveforms at points B and C are high. Similarly, the NOR gate outputs high only when both waveforms at points B and C are low. In other words, if either point B or C is high, the NOR gate outputs low. This creates a low-level interval (dead time) between SPWM1 and SPWM2, or between PWM1 and PWM2, during the high-low transition. This allows the NMOS and PMOS at the first and second ends of the half-bridge to turn off before the first NMOS and PMOS turn on, preventing a short circuit caused by both MMOS turning on simultaneously and potentially damaging the circuit.

[0054] Therefore, the dead time between SPWM1 / PWM1 and SPWM2 / PWM2 can be adjusted by the values ​​of resistor R1 and capacitor C1.

[0055] This solution improves the reliability of the control logic and greatly saves MCU resources by controlling the dead time and phase reversal of SPWM and PWM through hardware circuits.

[0056] Secondly, to improve the stability of this circuit, it is preferable to add several Schmitt inverting flip-flops to each output circuit of the first and second logic conversion circuits. In this scheme, it is preferable to add three Schmitt inverting flip-flops to the circuit. The first Schmitt inverting flip-flop U1 is set between the input terminal of the MCU and the input terminal of the resistor R1. The second Schmitt inverting flip-flop U2 is set between the first Schmitt inverting flip-flop U1 and the first input terminal of the AND gate circuit U4. The third Schmitt inverting flip-flop U3 is set between the resistor R1 and the second input terminal of the NOR gate circuit U5. By setting three Schmitt inverters, the signal output by the MCU and the signals input to the AND gate circuit U4 and the NOR gate circuit U5 can be stabilized, thus ensuring the stability of the circuit.

[0057] This solution does not require a Schmitt trigger; its main function is to stabilize the signal level and improve the signal's anti-interference capability, but it has no effect on the main logic of level conversion.

[0058] Based on the above conclusion, the logic conversion circuit can convert the MCU's output SPWM / PWM signal into two SPWM1 / PWM1 and SPWM2 / PWM2 signals by phase inversion. The dead time between SPWM1 / PWM1 and SPWM2 / PWM2 can be adjusted by regulating the values ​​of R1 and C1. For details, see [link to documentation]. Figure 7 The following is a detailed explanation based on the potential logic at each point in the circuit:

[0059] Point A: The original SPWM / PWM signal passes through a Schmitt inverting flip-flop, stabilizes the signal, and then is inverted by a Schmitt inverter U1 to stabilize the signal and improve the circuit's anti-interference capability.

[0060] Point B: The phase of the signal at point A is reversed again by the Schmitt inverter U2 so that the logic potential meets the input requirements of the subsequent gate circuit;

[0061] Point C: After the RC delay of R1 and C1 creates a certain phase difference between waveform A′ and point B, the Schmitt inverter U3 reverses A′ to form point C. This phase difference is the dead time between the output SPWM1 / PWM1 and SPWM2 / PWM2, which is the dead time for the switching control of the upper and lower MOS of the half-bridge, preventing the upper and lower MOS from turning on at the same time and causing a short circuit in the power supply.

[0062] SPWM1 / PWM1: The waveforms at points B and C are passed through an AND gate circuit. SPWM1 / PWM1 will only output high when both points B and C are high at the same time.

[0063] SPWM2 / PWM2: The waveforms at points B and C pass through an NOR gate circuit. SPWM2 / PWM2 only outputs high when both points B and C are low at the same time.

[0064] Furthermore, after outputting two SPWM1 and SPWM2 through the logic conversion circuit, the driver chip drives the signal to meet the voltage and current requirements of the half-bridge MOS, and then drives the two half-bridges to obtain two sets of SPWM waveforms that meet the requirements of driving the dimming glass.

[0065] The upper half-bridge is formed by MOSFETs Q1 and Q2. The output of SPWM1 is connected to the gate (G) of MOSFET Q1, the source (S) of MOSFET Q1 is connected to the drain (D) of MOSFET Q2, the source (S) of MOSFET Q2 is grounded, and the output of SPWM1 is connected to the gate (G) of MOSFET Q2. After the two SPWM1 and SPWM2 signals pass through the half-bridge to obtain two sets of SPWM waveforms that satisfy the requirements for driving the dimming glass, they are then filtered by the filter circuit L1 to obtain the final output sine wave.

[0066] Furthermore, after the two PWM1 and PWM2 outputs are processed by the second logic conversion circuit, they are respectively input to the half-bridge of the lower bridge arm.

[0067] Here, the first and second ends of the lower bridge arm half-bridge are formed by the cooperation of P-channel MOSFET circuit and N-channel MOSFET circuit. The output end of PWM1 is connected to the P-channel MOSFET circuit and the output end of PWM1 is connected to the N-channel MOSFET circuit. The required commutation level is generated at the output end of the lower bridge arm through the conduction and cutoff relationship of the P-channel MOSFET circuit and the N-channel MOSFET circuit, and is directly transmitted to the PDLC dimming glass.

[0068] Furthermore, a P-channel MOSFET circuit is formed by MOSFET Q1-2, resistor R1-1, MOSFET Q1-1, resistor R1-2, resistor R1-2, and resistor R1-3.

[0069] In this configuration, the two ends of resistor R1-1 are connected to the PWM1 signal and the gate (G) of MOSFET Q1-1, respectively. The drain (D) of MOSFET Q1-1 is connected to the input of resistor R1-2. The source (S) of MOSFET Q1-1 is grounded. The output of resistor R1-2 is connected to the gate (G) of MOSFET Q1-2. The drain (D) of MOSFET Q1-2 is connected to the drain (D) of MOSFET Q1-3. The two ends of resistor R1-3 are connected to resistor R1-2 and the source (S) of MOSFET Q1-2, respectively.

[0070] Furthermore, resistors R1-1 and R1-2 are the current-limiting resistors for driving MOSFETs Q1-1 and Q1-2, respectively, and resistor R1-3 is the bias resistor for driving MOSFET Q1-2.

[0071] ① When PWM1 is high, MOSFET Q1-1 is turned on. Resistors R1-2 and R1-3 divide the voltage across the gate and source of MOSFET Q1-2, forming a turn-on voltage Vgs, which turns Q1-2 on. ② When PWM1 is low, Q1-1 is turned off, blocking the voltage divider circuit of R1-2 and R1-3, making the gate and source voltages of Q1-2 equal (Vgs = 0), and Q1-2 is turned off.

[0072] Furthermore, resistors R1-4 and MOSFETs Q1-3 are used together to form an N-channel MOSFET circuit.

[0073] The two ends of resistor R1-4 are connected to the PWM2 signal and the gate of MOSFET Q1-3, respectively. The drain of MOSFET Q1-3 is connected to the drain of MOSFET Q1-3, and the source of MOSFET Q1-3 is grounded.

[0074] Furthermore, R1-4 is the current-limiting resistor for driving MOSFET Q1-3. When PWM2 is high, MOSFET Q1-3 is turned on, and when PWM2 is low, MOSFET Q1-3 is turned off.

[0075] PWM1 and PWM2 are out of phase, and because SPWM1 / PWM1 and SPWM2 / PWM2 satisfy a certain dead time, PWM1 and PWM2 satisfy a certain dead time, avoiding the simultaneous conduction of the upper and lower MOSFETs. According to the conduction and cutoff relationship of MOSFETs Q1-2 and Q1-3, the required commutation level is generated at the output of the lower bridge arm and directly output to the PDLC dimming glass.

[0076] Example 2:

[0077] According to the structure described in Example 1, see Figures 8-10 Multiple AND gates can be added to the output of the second logic circuit of the lower bridge arm. The output stages of the AND gate U4 and the NOR gate U5 in each group of gates can be expanded to multiple AND gates. The first half-bridge terminal (P-channel MOSFET) and the second half-bridge terminal (N-channel MOSFET) are also set at the output of each group of AND gates to form a multi-zone control circuit.

[0078] By adding multiple sets of gate circuits to form a multi-zone control circuit, which is set in parallel at the output of the second logic circuit, the different zones of the PDLC film can be controlled separately and the fog level of different zones can be adjusted independently. This allows for the creation of striped patterns on the sunroof. By using different control methods of the controller, the sunroof can display different striped patterns, further enhancing the driving experience.

[0079] Secondly, each zone control circuit is also equipped with an enable signal control, which controls the switching of each zone control circuit of the PDLC (see [link]). Figure 10 The logic diagram shows that the output only follows the level changes of U4 and U5 when EN outputs a high level; otherwise, the output remains low. This has enabled the switching control of multi-zone PDLC skylights through a simple logic control circuit, greatly reducing the controller's dependence on MCU performance resources, allowing for the selection of more cost-effective MCUs and reducing hardware costs.

[0080] By controlling the enable of multiple lower bridge arms, the switching of multiple PDLCs can be controlled. The switching control of multi-zone PDLCs can be realized through a simple and flexible drive circuit. Regardless of the number of PDLC zones, this structure only requires one SPWM and one PWM. Individual control of multiple PDLC zones can be realized with only multiple EN controls, which greatly saves MCU resources.

[0081] Multi-zone PDLC dimming sunroofs divide the PDLC film into multiple zones, and use a multi-channel controller to control each zone individually, adjusting the fog level of each zone independently. This allows for the creation of striped patterns on the sunroof, with different control methods enabling different striped patterns to be displayed, further enhancing the driving experience.

[0082] The dimming glass multi-zone driving system constructed by the above scheme realizes dead-time control of the upper and lower MOS of the half-bridge through hardware logic circuits, thereby improving the reliability of control.

[0083] Secondly, the use of unipolar SPWM modulation saves LC filter circuits compared to bipolar SPWM modulation, reduces the operating frequency of half of the bridge arm drive circuit, reduces hardware losses, and improves EMC performance.

[0084] Meanwhile, considering the low switching frequency and the small current in each zone of the multi-zone PDLC sunroof glass, a half-bridge is constructed using PMOS and NMOS transistors, driven by simple transistors. Compared with dedicated half-bridge driver chips, this simplifies the hardware and reduces costs.

[0085] Finally, for the separate control of multi-zone PDLC sunroof glass, only a commutation bridge arm needs to be added, and the switching control of different zones can be controlled only by the enable signal, which greatly saves hardware resources and reduces costs.

[0086] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A dimming glass multi-zone driving system, comprising an MCU chip, characterized in that, It also includes a first logic conversion circuit, at least one set of second logic conversion circuits, a first half-bridge drive circuit, a second half-bridge drive circuit, and a filter circuit. The signal output terminal of the MCU chip outputs two pulse signals, SPWM and PWM, which are directly input to the first logic conversion circuit and the second logic conversion circuit, respectively. The first logic conversion circuit flips one pulse signal SPWM and directly outputs two pulse signals SPWM1 and SPWM2, which are then input to the first half-bridge drive circuit. The first half-bridge drive circuit filters the two pulse signals through a filter circuit and outputs them to the PDLC dimming glass. The second logic conversion circuit flips the other pulse signal PWM and outputs two pulse signals, PWM1 and PWM2, which are then input to the second half-bridge drive circuit. The second half-bridge drive circuit includes a first terminal and a second terminal. The PWM1 signal is input to the first terminal of the second half-bridge drive circuit, and the PWM2 signal is input to the second terminal of the second half-bridge drive circuit. The required commutation level is generated at the output terminal of the second half-bridge drive circuit through the conduction and cutoff relationship between the first and second terminals of the second half-bridge drive circuit, and is directly output to the PDLC dimming glass.

2. The dimming glass multi-zone driving system according to claim 1, characterized in that, The MCU chip generates SPWM signal and PWM signal in a time-division multiplexing manner. The SPWM signal is converted into SPWM1 signal and SPWM2 signal after phase inversion after passing through the first logic conversion circuit. The PWM signal is converted into PWM1 signal and PWM2 signal after phase inversion after passing through the second logic conversion circuit.

3. The dimming glass multi-zone driving system according to claim 1, characterized in that, The first logic conversion circuit and the second logic conversion circuit each include several gate circuits, which convert one pulse signal generated by the MCU chip into two pulse signals by flipping the pulse signal.

4. The dimming glass multi-zone driving system according to claim 3, characterized in that, The first logic conversion circuit and the second logic conversion circuit are further provided with delay circuits. The delay circuit includes a first resistor and a first capacitor. The output terminal of the first resistor is connected to the input terminal of the first capacitor and is set in the first logic conversion circuit. The second logic conversion circuit flips and outputs either of the two pulse signals to the circuit. The dead time between SPWM1 and SPWM2 and between PWM1 and PWM2 is adjusted by adjusting the values ​​of the first resistor and the first capacitor.

5. A dimming glass multi-zone driving system according to claim 3, characterized in that, The output lines of the first logic conversion circuit and the second logic conversion circuit are each provided with a number of Schmitt trigger inverters to stabilize the output signals in the output lines of the first logic conversion circuit and the second logic conversion circuit.

6. The dimming glass multi-zone driving system according to claim 1, characterized in that, The first half-bridge driving circuit includes a driving chip, a first MOSFET and a second MOSFET. The input terminal of the driving chip is connected to a first logic conversion circuit, and the output terminal is connected to the gate of the first MOSFET and the gate of the second MOSFET respectively. The source and drain of the first MOSFET and the second MOSFET are output to a filter circuit.

7. A dimming glass multi-zone driving system according to claim 3, characterized in that, The output of the second logic conversion circuit can be equipped with multiple AND gate circuits in parallel to realize the output of multiple commutation level output circuits.

8. A dimming glass multi-zone driving system according to claim 7, characterized in that, The multiple sets of commutation level output circuits are arranged in parallel at the output terminal of the second logic conversion circuit.

9. A dimming glass multi-zone driving system according to claim 1, characterized in that, The second half-bridge drive circuit includes an N-channel MOS transistor circuit and a P-channel MOS transistor circuit. The input terminals of the N-channel MOS transistor circuit and the P-channel MOS transistor circuit are respectively connected to the two signals after phase inversion by the second logic conversion circuit, and the output terminal outputs the commutation level directly to the dimming glass.

10. A vehicle, characterized in that, The vehicle is equipped with a dimming glass multi-zone drive system as described in any one of claims 1-9.

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