A power-on initialization control system and method for an SRAM-based FPGA chip

Abstract

The embodiment of the application provides an SRAM-based FPGA chip power-on initialization control system and method, first, the first power supply is connected by a data selector, two power supply enable signals of a gate switch are low, the gate switch is not connected to the second power supply, and initialization configuration of a configuration memory of the FPGA chip is completed at this time; then, the two power supply enable signals of the gate switch are high, the gate switch is connected to the second power supply, the first inverter, the second inverter and the negative feedback circuit part are powered, a stable power-on output is obtained, and the rest of the FPGA chip is powered on. In this way, the whole FPGA chip can be normally configured to function and does not need to be initialized in the power-on process, and the leakage from the VDD end to the GND end does not occur.

Description

Technical Field

[0001] This invention relates to the field of chip power management technology, specifically to a power-on initialization control system and method for an SRAM-based FPGA chip. Background Technology

[0002] FPGA (Field Programmable Gate Array) can be mainly divided into three types according to the way the logic units are programmed: SRAM-based FPGA, Flash-based FPGA, and antifuse FPGA. Among them, SRAM-based FPGA has the widest range of applications.

[0003] like Figure 1 As shown, the main circuit structure in the current FPGA internal power-on initialization design includes a data selector (Multiplexer, MUX) and two inverters. The data selector is a One-Hot MUX, meaning the sel bit of the data selector is one-hot encoded / one-bit valid encoded. In a One-Hot MUX, only one switch Sn is turned on at a time. The potential values ​​of switches S0, S1, S2, and S3 (switch Sn) are unstable during power-on, making the potential at the inverter input terminal (g terminal) uncertain, which can easily lead to leakage from VDD to GND. Summary of the Invention

[0004] To address this issue, this invention provides a power-on initialization control system and method for SRAM-based FPGA chips, thereby solving the technical problem in the prior art where leakage current from VDD to GND is easily caused by the uncertain potential at the inverter input terminal during the power-on initialization process of FPGA chips.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0006] According to a first aspect of the present invention, this application provides a power-on initialization control system for an SRAM-based FPGA chip, the system comprising: a first power supply, a second power supply, a data selector, a gate switch, a first inverter, a second inverter, and a negative feedback circuit section;

[0007] The first power supply is output to the control signal input terminal of the first inverter via the data selector. The second power supply is output to the power input terminals of the first inverter, the second inverter, and the negative feedback circuit via the gate switch. The power output terminal of the first inverter is connected to the control signal input terminal of the second inverter, and the power output terminal of the second inverter is connected to the control signal input terminal of the negative feedback circuit.

[0008] When a power enable high signal is received from one of the data selectors, the corresponding one is selected to connect the first power supply. The configuration bit of the gate switch is powered on. When both power enable signals of the gate switch are low, the gate switch is not connected to the second power supply, thus completing the initialization configuration of the FPGA chip's configuration memory.

[0009] Both power supply enable signals of the gate switch are high, and the gate switch connects to the second power supply. The second power supply powers the first inverter, the second inverter, and the negative feedback circuit, resulting in a stable power-on output and powering on the rest of the FPGA chip.

[0010] Furthermore, the data selector includes a first to a fourth NMOS crystal switch, the gates of the first to fourth NMOS crystal switches are connected to the first power supply, the drains of the first to fourth NMOS crystal switches are respectively connected to the first to fourth enable signal receiving terminals for controlling the power supply of the first power supply, the sources of the first to fourth NMOS crystal switches are connected and serve as the output terminals of the data selector, and the substrates of the first to fourth NMOS crystal switches are connected to the first ground terminal.

[0011] Further, the gate switch includes a first PMOS crystal switch, a second PMOS crystal switch, a third PMOS crystal switch, a fifth NMOS crystal switch, and a sixth NMOS crystal switch; the drains of the first PMOS crystal switch and the second PMOS crystal switch are respectively connected to the fifth and sixth enable signal receiving terminals for controlling the power supply of the second power supply; the drains of the fifth NMOS crystal switch and the sixth NMOS crystal switch are respectively connected to the fifth and sixth enable signal receiving terminals for controlling the power supply of the second power supply; the sources and substrates of the first PMOS crystal switch, the second PMOS crystal switch, and the third PMOS crystal switch are connected to the second power supply; the gates of the first PMOS crystal switch and the second PMOS crystal switch, and the drain of the third PMOS crystal switch are connected to the gate of the fifth NMOS crystal switch; the source of the fifth NMOS crystal switch is connected to the gate of the sixth NMOS crystal switch; the substrate of the fifth NMOS crystal switch, and the source and substrate of the sixth NMOS crystal switch are connected to the second ground terminal; and the gate of the third PMOS crystal switch serves as the output terminal of the gate switch.

[0012] Furthermore, the first inverter includes a fourth PMOS crystal switch and a seventh NMOS crystal switch. The drains of the fourth PMOS crystal switch and the seventh NMOS crystal switch are connected to the output terminal of the data selector. The source and substrate of the fourth PMOS crystal switch are connected to the output terminal of the gate switch. The gates of the fourth PMOS crystal switch and the seventh NMOS crystal switch are connected together to serve as the output terminal of the first inverter. The source and substrate of the seventh NMOS crystal switch are connected to the first ground terminal.

[0013] Furthermore, the second inverter includes a fifth PMOS crystal switch and an eighth NMOS crystal switch; the drains of the fifth PMOS crystal switch and the eighth NMOS crystal switch are connected to the output terminal of the first inverter, the source and substrate of the fifth PMOS crystal switch are connected to the output terminal of the gate switch, the gates of the fifth PMOS crystal switch and the eighth NMOS crystal switch are connected and serve as the output terminal of the second inverter, and the source and substrate of the eighth NMOS crystal switch are connected to the first ground terminal.

[0014] Furthermore, the negative feedback circuit includes a sixth PMOS crystal switch, a seventh PMOS crystal switch, a ninth NMOS crystal switch, and a tenth NMOS crystal switch; the drain of the ninth NMOS crystal switch is connected to the output terminal of the second inverter; the source and substrate of the sixth and seventh PMOS crystal switches are connected to the output terminal of the gate switch; the gates of the sixth and ninth NMOS crystal switches are connected to the drain of the seventh PMOS crystal switch; the source and substrate of the ninth NMOS crystal switch are connected to the first ground terminal; the drain and source of the tenth NMOS crystal switch are connected to the first ground terminal; the drain of the sixth PMOS crystal switch, the seventh PMOS crystal switch, and the gate of the tenth NMOS crystal switch are connected together to form the overall output terminal; and the substrate of the tenth NMOS crystal switch is connected to the output terminal of the first inverter.

[0015] According to a second aspect of the present invention, this application provides a power-on initialization control method for an SRAM-based FPGA chip, the method comprising:

[0016] The circuit includes a first power supply, a second power supply, a data selector, a gate switch, a first inverter, a second inverter, and a negative feedback circuit.

[0017] The first power supply is output to the control signal input terminal of the first inverter via the data selector. The second power supply is output to the power input terminals of the first inverter, the second inverter, and the negative feedback circuit via the gate switch. The power output terminal of the first inverter is connected to the control signal input terminal of the second inverter, and the power output terminal of the second inverter is connected to the control signal input terminal of the negative feedback circuit.

[0018] When a power enable high signal is received from one of the data selectors, the corresponding one is selected to connect the first power supply. The configuration bit of the gate switch is powered on. When both power enable signals of the gate switch are low, the gate switch is not connected to the second power supply, thus completing the initialization configuration of the FPGA chip's configuration memory.

[0019] Both power supply enable signals of the gate switch are high, and the gate switch connects to the second power supply. The second power supply powers the first inverter, the second inverter, and the negative feedback circuit, resulting in a stable power-on output and powering on the rest of the FPGA chip.

[0020] Furthermore, the data selector includes a first to a fourth NMOS crystal switch, the gates of the first to fourth NMOS crystal switches are connected to the first power supply, the drains of the first to fourth NMOS crystal switches are respectively connected to the first to fourth enable signal receiving terminals for controlling the power supply of the first power supply, the sources of the first to fourth NMOS crystal switches are connected and serve as the output terminals of the data selector, and the substrates of the first to fourth NMOS crystal switches are connected to the first ground terminal.

[0021] Further, the gate switch includes a first PMOS crystal switch, a second PMOS crystal switch, a third PMOS crystal switch, a fifth NMOS crystal switch, and a sixth NMOS crystal switch; the drains of the first PMOS crystal switch and the second PMOS crystal switch are respectively connected to the fifth and sixth enable signal receiving terminals for controlling the power supply of the second power supply; the drains of the fifth NMOS crystal switch and the sixth NMOS crystal switch are respectively connected to the fifth and sixth enable signal receiving terminals for controlling the power supply of the second power supply; the sources and substrates of the first PMOS crystal switch, the second PMOS crystal switch, and the third PMOS crystal switch are connected to the second power supply; the gates of the first PMOS crystal switch and the second PMOS crystal switch, and the drain of the third PMOS crystal switch are connected to the gate of the fifth NMOS crystal switch; the source of the fifth NMOS crystal switch is connected to the gate of the sixth NMOS crystal switch; the substrate of the fifth NMOS crystal switch, and the source and substrate of the sixth NMOS crystal switch are connected to the second ground terminal; and the gate of the third PMOS crystal switch serves as the output terminal of the gate switch.

[0022] Furthermore, the first inverter includes a fourth PMOS crystal switch and a seventh NMOS crystal switch. The drains of the fourth PMOS crystal switch and the seventh NMOS crystal switch are connected to the output terminal of the data selector. The source and substrate of the fourth PMOS crystal switch are connected to the output terminal of the gate switch. The gates of the fourth PMOS crystal switch and the seventh NMOS crystal switch are connected together to serve as the output terminal of the first inverter. The source and substrate of the seventh NMOS crystal switch are connected to the first ground terminal.

[0023] Furthermore, the second inverter includes a fifth PMOS crystal switch and an eighth NMOS crystal switch; the drains of the fifth PMOS crystal switch and the eighth NMOS crystal switch are connected to the output terminal of the first inverter, the source and substrate of the fifth PMOS crystal switch are connected to the output terminal of the gate switch, the gates of the fifth PMOS crystal switch and the eighth NMOS crystal switch are connected and serve as the output terminal of the second inverter, and the source and substrate of the eighth NMOS crystal switch are connected to the first ground terminal.

[0024] Furthermore, the negative feedback circuit includes a sixth PMOS crystal switch, a seventh PMOS crystal switch, a ninth NMOS crystal switch, and a tenth NMOS crystal switch; the drain of the ninth NMOS crystal switch is connected to the output terminal of the second inverter; the source and substrate of the sixth and seventh PMOS crystal switches are connected to the output terminal of the gate switch; the gates of the sixth and ninth NMOS crystal switches are connected to the drain of the seventh PMOS crystal switch; the source and substrate of the ninth NMOS crystal switch are connected to the first ground terminal; the drain and source of the tenth NMOS crystal switch are connected to the first ground terminal; the drain of the sixth PMOS crystal switch, the seventh PMOS crystal switch, and the gate of the tenth NMOS crystal switch are connected together to form the overall output terminal; and the substrate of the tenth NMOS crystal switch is connected to the output terminal of the first inverter.

[0025] Compared with existing technologies, the SRAM-based FPGA chip power-on initialization control system and method provided in this application firstly connects the first power supply via a data selector, and both power supply enable signals of the gate switch are low, while the gate switch does not connect the second power supply. At this time, the initialization configuration of the FPGA chip's configuration memory is completed. Then, both power supply enable signals of the gate switch are made high, and the gate switch connects the second power supply, supplying power to the first inverter, the second inverter, and the negative feedback circuit, resulting in a stable power-on output and completing the power-on of the remaining parts of the FPGA chip. In this way, the entire FPGA chip will be configured and complete its functions normally without initialization during the power-on process, and there will be no leakage current from the VDD terminal to the GND terminal. Attached Figure Description

[0026] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0027] The structures, proportions, sizes, etc. illustrated in this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0028] Figure 1This is a schematic diagram of the main circuit structure in the current FPGA internal power-on initialization design;

[0029] Figure 2 A schematic diagram of the circuit structure of a power-on initialization control system for an SRAM-based FPGA chip provided in an embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of the configuration memory cell circuit structure of an SRAM-based FPGA chip provided in an embodiment of the present invention. Detailed Implementation

[0031] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] The purpose of this application is to provide a power-on initialization control system and method for SRAM-based FPGA chips, so as to solve the technical problem in the prior art that leakage current from VDD to GND is easily caused by the uncertain potential of the inverter input terminal during the power-on initialization process of FPGA chips.

[0033] To address the aforementioned technical problems, embodiments of this application provide a power-on initialization control system for an SRAM-based FPGA chip, such as... Figure 2 As shown, it specifically includes: a first power supply 1, a second power supply 2, a data selector 3, a gate switch 4, a first inverter 5, a second inverter 6, and a negative feedback circuit section 7.

[0034] Furthermore, the first power supply 1 is a 1.2V DC power supply, and the second power supply 2 is a 0.9V DC power supply. The first power supply 1 is output to the control signal input terminal of the first inverter 5 via the data selector 3, and the second power supply 2 is output to the power input terminals of the first inverter 5, the second inverter 6, and the negative feedback circuit section 7 via the gate switch 4. The power output terminal of the first inverter 5 is connected to the control signal input terminal of the second inverter 6, and the power output terminal of the second inverter 6 is connected to the control signal input terminal of the negative feedback circuit section 7.

[0035] In this embodiment of the invention, the data selector 3 is a One-Hot MUX (multiplexer). One-Hot refers to One-Hot encoding, also known as one-bit valid encoding. It mainly uses an N-bit status register to encode N states. Each state has its own independent register bit, and only one bit is valid at any given time.

[0036] refer to Figure 2 In this embodiment of the invention, the data selector 3 is a 4-to-1 data selector. The data selector 3 includes a first NMOS crystal switch NM0, a second NMOS crystal switch NM1, a third NMOS crystal switch NM2, and a fourth NMOS crystal switch NM3. The gates of the first NMOS crystal switch NM0, the second NMOS crystal switch NM1, the third NMOS crystal switch NM2, and the fourth NMOS crystal switch NM3 are connected to the positive terminal of the first power supply 1, and the negative terminal of the first power supply is connected to the third ground terminal 10. The drain of the first NMOS crystal switch NM0 is connected to the receiving terminal of the first enable signal IN0, and the second NMOS crystal switch NM1... The drain of the first NMOS transistor NM0 is connected to the receiving terminal of the second enable signal IN1, the drain of the third NMOS transistor NM2 is connected to the receiving terminal of the third enable signal IN2, and the drain of the fourth NMOS transistor NM3 is connected to the receiving terminal of the fourth enable signal IN3. The sources of the first NMOS transistor NM0, the second NMOS transistor NM1, the third NMOS transistor NM2, and the fourth NMOS transistor NM3 are connected together and used as the output terminal of the data selector 3. The substrates of the first NMOS transistor NM0, the second NMOS transistor NM1, the third NMOS transistor NM2, and the fourth NMOS transistor NM3 are connected to the first ground terminal 8.

[0037] As described above, the first enable signal IN0, the second enable signal IN1, the third enable signal IN2, and the fourth enable signal IN3 are used to control the power supply of the first power source. In this embodiment of the invention, the first enable signal IN0, the second enable signal IN1, the third enable signal IN2, and the fourth enable signal IN3 originate from the FPGA. The FPGA includes the following four parts: configuration memory bit cell, LUT unit, special block unit (Special Block [dsp.emb.F0]), and clock unit. (Refer to...) Figure 3The configuration memory unit has three types of pins: WL, BL / BLB, and int / intb. The int / intb pin is used for control logic. The first enable signal IN0, the second enable signal IN1, the third enable signal IN2, and the fourth enable signal IN3 originate from the aforementioned int / intb pin. LUT stands for Display Look-Up Table, which is essentially a RAM. It pre-writes data into RAM, and each input signal is equivalent to inputting an address to look up the corresponding content in the table, which is then output. In this embodiment of the invention, the LUT unit selects a 6-input function and has a 64-to-1 selection function, capable of storing 64 bits of data. The specific implementation function of the LUT unit is controlled by the int / intb pin of the configuration memory unit.

[0038] In this embodiment of the invention, a single-transistor NMOS is used for the data selector instead of a composite CMOS transistor. This ensures that the circuit will not leak current when the mux is in an undefined state. Moreover, it is not just a 4-to-1 selection, but an n-to-1 selection. When the input bit width is 64, it is a 64-to-1 selection.

[0039] refer to Figure 2 The gate switch 4 includes a first PMOS crystal switch PM0, a second PMOS crystal switch PM1, a third PMOS crystal switch PM2, a fifth NMOS crystal switch NM4, and a sixth NMOS crystal switch NM5. The drains of the first PMOS crystal switch PM0 and the second PMOS crystal switch PM1 are respectively connected to the receiving terminals of the sixth enable signal B and the fifth enable signal A used to control the power supply of the second power supply 2. The fifth enable signal A and the sixth enable signal B also come from the FPGA. The drains of the fifth NMOS crystal switch NM4 and the sixth NMOS crystal switch NM5 are respectively connected to the receiving terminals of the fifth enable signal A and the sixth enable signal B used to control the power supply of the second power supply 2. The source and substrate of transistor PM0, second PMOS transistor PM1, and third PMOS transistor PM2 are connected to the positive terminal of the second power supply 2, and the negative terminal of the second power supply 2 is connected to the second ground terminal 9. The gate of first PMOS transistor PM0, second PMOS transistor PM1, and drain of third PMOS transistor PM2 are connected to the gate of fifth NMOS transistor NM4. The source of fifth NMOS transistor NM4 is connected to the gate of sixth NMOS transistor NM5. The substrate of fifth NMOS transistor NM4, the source and substrate of sixth NMOS transistor NM5 are connected to the second ground terminal 9. The gate of third PMOS transistor PM2 serves as the output terminal of gate switch 4.

[0040] In this embodiment of the invention, the fifth enable signal A, the sixth enable signal B, and the first enable signal IN0, the second enable signal IN1, the third enable signal IN2, and the fourth enable signal IN3 of the 4-to-1 data selector are all controlled by the FPGA's configuration memory. The overall process is as follows: When the switch is open, because the input and output signals are not fixed, to ensure that the signals do not interfere, the first enable signal IN0, the second enable signal IN1, the third enable signal IN2, the fourth enable signal IN3, and the output port are all in a high-impedance state, i.e., power off. All input ports are powered on after the first enable signal IN0, the second enable signal IN1, the third enable signal IN2, and the fourth enable signal IN3 are set to zero, and only one input port signal is turned on at a time.

[0041] refer to Figure 2 The first inverter 5 includes a fourth PMOS crystal switch PM3 and a seventh NMOS crystal switch NM6. The drains of the fourth PMOS crystal switch PM3 and the seventh NMOS crystal switch NM6 are connected to the output terminal of the data selector 3. The source and substrate of the fourth PMOS crystal switch PM3 are connected to the output terminal of the gate switch 4. The gates of the fourth PMOS crystal switch PM3 and the seventh NMOS crystal switch NM6 are connected together to serve as the output terminal of the first inverter 5. The source and substrate of the seventh NMOS crystal switch NM6 are connected to the first ground terminal 8.

[0042] refer to Figure 2 The second inverter 6 includes a fifth PMOS crystal switch PM4 and an eighth NMOS crystal switch NM7. The drains of the fifth PMOS crystal switch PM4 and the eighth NMOS crystal switch NM7 are connected to the output terminal of the first inverter 5. The source and substrate of the fifth PMOS crystal switch PM4 are connected to the output terminal of the gate switch 4. The gates of the fifth PMOS crystal switch PM4 and the eighth NMOS crystal switch NM7 are connected together to serve as the output terminal of the second inverter 6. The source and substrate of the eighth NMOS crystal switch NM7 are connected to the first ground terminal 8.

[0043] In this embodiment of the invention, not only is a gate switch used to control the second power supply, but a negative feedback circuit is also used to compensate for the voltage consumed by the input voltage. The former two, together with the n-to-one selection circuit of the one-hot mux, form the entire mux circuit, which is then applied to the FPGA chip as part of the entire system. Specifically, refer to... Figure 2The negative feedback circuit section 7 includes a sixth PMOS crystal switch PM5, a seventh PMOS crystal switch PM6, a ninth NMOS crystal switch NM8, and a tenth NMOS crystal switch NM9. The drain of the ninth NMOS crystal switch NM8 is connected to the output terminal of the second inverter 6. The source and substrate of the sixth PMOS crystal switch PM5 and the seventh PMOS crystal switch PM6 are connected to the output terminal of the gate switch 4. The gate of the sixth PMOS crystal switch PM5 and the ninth NMOS crystal switch NM8 is connected to the drain of the seventh PMOS crystal switch PM6. The source and substrate of the ninth NMOS crystal switch NM8 are connected to the first ground terminal 8. The drain and source of the tenth NMOS crystal switch NM9 are connected to the first ground terminal 8. The drain of the sixth PMOS crystal switch PM5, the gate of the seventh PMOS crystal switch PM6, and the gate of the tenth NMOS crystal switch NM9 are connected together to form the total output terminal. The substrate of the tenth NMOS crystal switch NM9 is connected to the output terminal of the first inverter 5.

[0044] refer to Figure 2 In this embodiment of the invention, firstly, one of the data selectors 3 receives a high power enable signal, selects the corresponding channel to connect the first power supply 1, and the configuration bit of the gate switch 4 is powered on. Both power enable signals of the gate switch 4 are low, and the gate switch 4 is not connected to the second power supply, thus completing the initialization configuration of the configuration memory of the FPGA chip. Afterwards, both power enable signals of the gate switch 4 are high, and the gate switch 4 connects to the second power supply 2. The second power supply 2 supplies power to the first inverter 5, the second inverter 6, and the negative feedback circuit 7, resulting in a stable power-on output, thus completing the power-on of the rest of the FPGA chip.

[0045] Compared with existing technologies, the SRAM-based FPGA chip power-on initialization control system provided in this application first connects the first power supply via a data selector, and both power supply enable signals of the gate switch are low, while the gate switch does not connect the second power supply. At this time, the initialization configuration of the FPGA chip's configuration memory is completed. Then, both power supply enable signals of the gate switch are made high, and the gate switch connects the second power supply, supplying power to the first inverter, the second inverter, and the negative feedback circuit, resulting in a stable power-on output and completing the power-on of the remaining parts of the FPGA chip. In this way, the entire FPGA chip will be configured and complete its functions normally without initialization during the power-on process, and there will be no leakage current from the VDD terminal to the GND terminal.

[0046] Corresponding to the power-on initialization control system for SRAM-based FPGA chips disclosed above, this invention also discloses a power-on initialization control method for SRAM-based FPGA chips. The following details a power-on initialization control method for SRAM-based FPGA chips disclosed in this invention, in conjunction with the power-on initialization control system for SRAM-based FPGA chips described above.

[0047] In one embodiment of the present invention, such as Figure 2 As shown below, the specific steps of a power-on initialization control method for an SRAM-based FPGA chip provided in this application embodiment will be described in detail below.

[0048] The circuit consists of a first power supply (1), a second power supply (2), a data selector (3), a gate switch (4), a first inverter (5), a second inverter (6), and a negative feedback circuit (7).

[0049] The first power supply 1 is output to the control signal input terminal of the first inverter 5 via the data selector 3. The second power supply 2 is output to the power input terminals of the first inverter 5, the second inverter 6, and the negative feedback circuit section 7 via the gate switch 4. The power output terminal of the first inverter 5 is connected to the control signal input terminal of the second inverter 6, and the power output terminal of the second inverter 6 is connected to the control signal input terminal of the negative feedback circuit section 7.

[0050] When a high power enable signal is received from one of the data selectors 3, the corresponding one is selected to connect the first power supply 1. The configuration bit of the gate switch 4 is powered on. Both power enable signals of the gate switch 4 are low. The gate switch 4 is not connected to the second power supply, and the initialization configuration of the FPGA chip's configuration memory is completed.

[0051] Both power supply enable signals of the gate switch 4 are high, and the gate switch 4 connects to the second power supply 2. The second power supply 2 supplies power to the first inverter 5, the second inverter 6, and the negative feedback circuit 7, resulting in a stable power-on output and completing the power-on of the rest of the FPGA chip.

[0052] Compared with existing technologies, the SRAM-based FPGA chip power-on initialization control method provided in this application first connects the first power supply via a data selector, and both power supply enable signals of the gate switch are low, while the gate switch does not connect the second power supply. At this time, the configuration memory of the FPGA chip is initialized. Then, both power supply enable signals of the gate switch are made high, and the gate switch connects the second power supply, supplying power to the first inverter, the second inverter, and the negative feedback circuit, resulting in a stable power-on output and completing the power-on of the rest of the FPGA chip. In this way, the entire FPGA chip will be configured and complete its functions normally without initialization during the power-on process, and there will be no leakage current from the VDD terminal to the GND terminal.

[0053] Although the present invention has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to it, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present invention fall within the scope of protection claimed by the present invention.

Claims

1. A power-on initialization control system for an SRAM-based FPGA chip, characterized in that, The system includes: a first power supply, a second power supply, a data selector, a gate switch, a first inverter, a second inverter, and a negative feedback circuit section; The first power supply is output to the control signal input terminal of the first inverter via the data selector. The second power supply is output to the power input terminal of the first inverter, the power input terminal of the second inverter, and the power input terminal of the negative feedback circuit via the gate switch. The power output terminal of the first inverter is connected to the control signal input terminal of the second inverter, and the power output terminal of the second inverter is connected to the control signal input terminal of the negative feedback circuit. When a power enable high signal is received from one of the data selectors, the corresponding one is selected to connect the first power supply. The configuration bit of the gate switch is powered on. When both power enable signals of the gate switch are low, the gate switch is not connected to the second power supply, thus completing the initialization configuration of the FPGA chip's configuration memory. Both power supply enable signals of the gate switch are high, and the gate switch connects to the second power supply. The second power supply powers the first inverter, the second inverter, and the negative feedback circuit, resulting in a stable power-on output and completing the power-on of the rest of the FPGA chip. The negative feedback circuit includes a sixth PMOS crystal switch, a seventh PMOS crystal switch, a ninth NMOS crystal switch, and a tenth NMOS crystal switch. The drain of the ninth NMOS crystal switch is connected to the output terminal of the second inverter. The source and substrate of the sixth PMOS crystal switch and the source and substrate of the seventh PMOS crystal switch are connected to the output terminal of the gate switch. The gates of the sixth PMOS crystal switch and the ninth NMOS crystal switch are connected to the drain of the seventh PMOS crystal switch. The source and substrate of the ninth NMOS crystal switch are connected to the first ground terminal. The drain and source of the tenth NMOS crystal switch are connected to the first ground terminal. The drain of the sixth PMOS crystal switch, the gate of the seventh PMOS crystal switch, and the gate of the tenth NMOS crystal switch are connected together to form the overall output terminal. The substrate of the tenth NMOS crystal switch is connected to the output terminal of the first inverter.

2. The SRAM-based FPGA chip power-on initialization control system as described in claim 1, characterized in that, The data selector includes a first to a fourth NMOS transistor. The gates of the first to fourth NMOS transistors are connected to the first power supply. The drains of the first to fourth NMOS transistors are respectively connected to the first to fourth enable signal receiving terminals for controlling the power supply of the first power supply. The sources of the first to fourth NMOS transistors are connected and serve as the output terminals of the data selector. The substrates of the first to fourth NMOS transistors are connected to the first ground terminal.

3. The SRAM-based FPGA chip power-on initialization control system as described in claim 2, characterized in that, The gate switch includes a first PMOS crystal switch, a second PMOS crystal switch, a third PMOS crystal switch, a fifth NMOS crystal switch, and a sixth NMOS crystal switch. The drains of the first and second PMOS crystal switches are respectively connected to a fifth enable signal receiver and a sixth enable signal receiver for controlling the second power supply. The drains of the fifth and sixth NMOS crystal switches are also connected to the fifth enable signal receiver and the sixth enable signal receiver for controlling the second power supply. The source and substrate of the first PMOS crystal switch are... The bottom, the source and substrate of the second PMOS crystal switch, and the source and substrate of the third PMOS crystal switch are connected to the second power supply. The gate of the first PMOS crystal switch, the gate of the second PMOS crystal switch, and the drain of the third PMOS crystal switch are connected to the gate of the fifth NMOS crystal switch. The source of the fifth NMOS crystal switch is connected to the gate of the sixth NMOS crystal switch. The substrate of the fifth NMOS crystal switch, the source and substrate of the sixth NMOS crystal switch are connected to the second ground terminal. The gate of the third PMOS crystal switch serves as the output terminal of the gate switch.

4. The SRAM-based FPGA chip power-on initialization control system as described in claim 3, characterized in that, The first inverter includes a fourth PMOS crystal switch and a seventh NMOS crystal switch. The drains of the fourth PMOS crystal switch and the seventh NMOS crystal switch are connected to the output terminal of the data selector. The source and substrate of the fourth PMOS crystal switch are connected to the output terminal of the gate switch. The gates of the fourth PMOS crystal switch and the seventh NMOS crystal switch are connected to serve as the output terminal of the first inverter. The source and substrate of the seventh NMOS crystal switch are connected to the first ground terminal.

5. The SRAM-based FPGA chip power-on initialization control system as described in claim 4, characterized in that, The second inverter includes a fifth PMOS crystal switch and an eighth NMOS crystal switch; the drains of the fifth PMOS crystal switch and the eighth NMOS crystal switch are connected to the output terminal of the first inverter, the source and substrate of the fifth PMOS crystal switch are connected to the output terminal of the gate switch, the gates of the fifth PMOS crystal switch and the eighth NMOS crystal switch are connected to serve as the output terminal of the second inverter, and the source and substrate of the eighth NMOS crystal switch are connected to the first ground terminal.

6. A power-on initialization control method for an SRAM-based FPGA chip, characterized in that, The method includes: The circuit includes a first power supply, a second power supply, a data selector, a gate switch, a first inverter, a second inverter, and a negative feedback circuit. The first power supply is output to the control signal input terminal of the first inverter via the data selector. The second power supply is output to the power input terminal of the first inverter, the power input terminal of the second inverter, and the power input terminal of the negative feedback circuit via the gate switch. The power output terminal of the first inverter is connected to the control signal input terminal of the second inverter, and the power output terminal of the second inverter is connected to the control signal input terminal of the negative feedback circuit. When a power enable high signal is received from one of the data selectors, the corresponding one is selected to connect the first power supply. The configuration bit of the gate switch is powered on. When both power enable signals of the gate switch are low, the gate switch is not connected to the second power supply, thus completing the initialization configuration of the FPGA chip's configuration memory. Both power supply enable signals of the gate switch are high, and the gate switch connects to the second power supply. The second power supply powers the first inverter, the second inverter, and the negative feedback circuit, resulting in a stable power-on output and completing the power-on of the rest of the FPGA chip. The negative feedback circuit includes a sixth PMOS crystal switch, a seventh PMOS crystal switch, a ninth NMOS crystal switch, and a tenth NMOS crystal switch. The drain of the ninth NMOS crystal switch is connected to the output terminal of the second inverter. The source and substrate of the sixth PMOS crystal switch and the source and substrate of the seventh PMOS crystal switch are connected to the output terminal of the gate switch. The gates of the sixth PMOS crystal switch and the ninth NMOS crystal switch are connected to the drain of the seventh PMOS crystal switch. The source and substrate of the ninth NMOS crystal switch are connected to the first ground terminal. The drain and source of the tenth NMOS crystal switch are connected to the first ground terminal. The drain of the sixth PMOS crystal switch, the gate of the seventh PMOS crystal switch, and the gate of the tenth NMOS crystal switch are connected together to form the overall output terminal. The substrate of the tenth NMOS crystal switch is connected to the output terminal of the first inverter.

7. The power-on initialization control method for an SRAM-based FPGA chip as described in claim 6, characterized in that, The gate switch includes a first PMOS crystal switch, a second PMOS crystal switch, a third PMOS crystal switch, a fifth NMOS crystal switch, and a sixth NMOS crystal switch. The drains of the first and second PMOS crystal switches are respectively connected to a fifth enable signal receiving terminal and a sixth enable signal receiving terminal for controlling the power supply of the second power source. The drains of the fifth and sixth NMOS crystal switches are respectively connected to the fifth enable signal receiving terminal and the sixth enable signal receiving terminal for controlling the power supply of the second power source. The source and substrate of the first PMOS crystal switch... The bottom, the source and substrate of the second PMOS crystal switch, and the source and substrate of the third PMOS crystal switch are connected to the second power supply. The gate of the first PMOS crystal switch, the gate of the second PMOS crystal switch, and the drain of the third PMOS crystal switch are connected to the gate of the fifth NMOS crystal switch. The source of the fifth NMOS crystal switch is connected to the gate of the sixth NMOS crystal switch. The substrate of the fifth NMOS crystal switch, the source and substrate of the sixth NMOS crystal switch are connected to the second ground terminal. The gate of the third PMOS crystal switch serves as the output terminal of the gate switch.

8. The power-on initialization control method for an SRAM-based FPGA chip as described in claim 7, characterized in that, The first inverter includes a fourth PMOS crystal switch and a seventh NMOS crystal switch. The drains of the fourth PMOS crystal switch and the seventh NMOS crystal switch are connected to the output terminal of the data selector. The source and substrate of the fourth PMOS crystal switch are connected to the output terminal of the gate switch. The gate of the fourth PMOS crystal switch and the gate of the seventh NMOS crystal switch are connected together to serve as the output terminal of the first inverter. The source and substrate of the seventh NMOS crystal switch are connected to the first ground terminal. The second inverter includes a fifth PMOS crystal switch and an eighth NMOS crystal switch. The drains of the fifth PMOS crystal switch and the eighth NMOS crystal switch are connected to the output terminal of the first inverter. The source and substrate of the fifth PMOS crystal switch are connected to the output terminal of the gate switch. The gates of the fifth PMOS crystal switch and the eighth NMOS crystal switch are connected together to serve as the output terminal of the second inverter. The source and substrate of the eighth NMOS crystal switch are connected to the first ground terminal.

9. The power-on initialization control method for an SRAM-based FPGA chip as described in claim 6, characterized in that, The negative feedback circuit includes a sixth PMOS crystal switch, a seventh PMOS crystal switch, a ninth NMOS crystal switch, and a tenth NMOS crystal switch. The drain of the ninth NMOS crystal switch is connected to the output terminal of the second inverter. The source and substrate of the sixth PMOS crystal switch and the source and substrate of the seventh PMOS crystal switch are connected to the output terminal of the gate switch. The gates of the sixth PMOS crystal switch and the ninth NMOS crystal switch are connected to the drain of the seventh PMOS crystal switch. The source and substrate of the ninth NMOS crystal switch are connected to the first ground terminal. The drain and source of the tenth NMOS crystal switch are connected to the first ground terminal. The drain of the sixth PMOS crystal switch, the gate of the seventh PMOS crystal switch, and the gate of the tenth NMOS crystal switch are connected together to form the overall output terminal. The substrate of the tenth NMOS crystal switch is connected to the output terminal of the first inverter.

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