A common input resistor and external clock dual mode frequency modulation oscillator circuit

Abstract

The application discloses a dual-mode frequency modulation oscillator circuit with shared input terminal, which is composed of a voltage reference circuit VREF, a current reference circuit IREF, a mode selection circuit MSC, a charge pump phase-locked loop CPPLL and a loop oscillator OSC. The circuit can adjust the oscillator frequency in two modes of resistance and external clock, and the two modes share the input terminal. The mode selection circuit automatically identifies the two frequency modulation modes according to the signal of the input terminal. The phase-locked loop circuit is composed of a phase-frequency detection circuit PFD, a charge pump CP and a low-pass filter LPF, and is used for outputting a voltage signal. In the external clock frequency modulation mode, the voltage signal can adjust the oscillator frequency, so that the oscillator signal is synchronized with the external signal. In the resistance mode, the output of the voltage reference circuit VREF can make the voltage across the resistance fixed, thereby generating a current related only to the resistance size, which can control the frequency of the oscillator.

Description

Technical Field

[0001] This invention relates to a dual-mode frequency-modulated oscillator circuit with a common input terminal resistor and an external clock, belonging to the field of analog integrated circuit technology. Background Technology

[0002] An oscillator is a conversion circuit that converts a DC signal into an AC signal with a certain frequency. A typical oscillator generates a periodic voltage signal. However, a poorly designed feedback amplifier can also cause problems. If the amplifier's output has an excessively large phase shift, causing the feedback to become positive feedback and the feedback gain to be greater than 1, then noise at frequency ω0 will be amplified and phase-shifted by 180 degrees and applied to the amplifier's input. This causes the circuit to enter a loop, continuously amplifying the signal at frequency ω0, and thus oscillate.

[0003] Oscillator frequency modulation methods mainly include changing the charging and discharging current, changing the load resistance value, using negative feedback technology, and using differential technology. Since the voltage that a capacitor can reach is constant, changing the charging and discharging current of the capacitor changes the charging and discharging time of the capacitor, thereby adjusting the frequency of the oscillator. For existing frequency-modulated oscillators, both methods generally require two input terminals or two oscillators, which requires a large layout area and power consumption.

[0004] A phase-locked loop (PLL) is a negative feedback control system that adjusts the phase of the output signal by comparing the phase of the target signal with that of the output signal. A Type I PLL typically consists of a phase detector, a low-pass filter, and a voltage-controlled oscillator (VCO). The average output of the phase detector is linearly proportional to the phase difference between its two inputs. This output, after filtering, serves as the input to the oscillator. The oscillator's output and the target signal then serve as the inputs to the phase detector, thus adjusting the oscillator's phase until it matches the target signal. A significant drawback of Type I PLLs is their limited frequency acquisition range.

[0005] An improvement upon the Type I phase-locked loop (PLL) yields a charge-pumped PLL (CPPLL). For periodic signals, a phase detector and a frequency detector can be combined; this circuit can detect both phase and frequency differences, and is called a phase-frequency detector. A charge pump is inserted between the phase-frequency detector and the loop filter. The output of the phase-frequency detector determines whether the charge is pumped into or out of the filter. The output voltage of the low-pass filter then adjusts the frequency and phase of the oscillator, ensuring that the oscillator's frequency matches the target signal. Summary of the Invention

[0006] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a dual-mode frequency modulation oscillator circuit with a shared input terminal and an external clock. The oscillator frequency can be adjusted using both a resistor and an external clock, sharing the same input terminal. Furthermore, it can automatically identify the two frequency modulation modes based on the signal at the input terminal. Both modes share the same oscillator, reducing circuit area and power consumption.

[0007] The technical solution of this invention is:

[0008] This invention discloses a dual-mode frequency-modulated oscillator circuit with a common input terminal and an external clock, comprising a voltage reference circuit VREF, a current reference circuit IREF, a mode selection circuit MSC, a charge pump phase-locked loop CPPLL, a loop oscillator OSC, and switches S1, S2, and S3; wherein,

[0009] The voltage reference circuit VREF generates a fixed voltage, which is output to the charge pump phase-locked loop CPPLL through switch S1.

[0010] The current reference circuit IREF is used to generate the fixed current required for the charge pump phase-locked loop (CPPLL) to charge and discharge, and to provide current to the mode selection circuit (MSC).

[0011] The loop oscillator (OSC) has its input terminal connected to the external input voltage V via switch S2. IN Connection, based on external input voltage V IN The phase-locked loop voltage signal output from the charge pump phase-locked loop (CPPLL) generates an oscillating voltage signal V. OSC The output is supplied to the charge pump phase-locked loop (CPPLL) and external circuitry.

[0012] Charge pump phase-locked loop (CPPLL) based on external input voltage V IN and oscillating voltage signal V OSC The frequency difference is used to output a phase-locked loop voltage signal to the mode selection circuit MSC; the output phase-locked loop voltage signal is then output to the loop oscillator OSC via switch S3.

[0013] The mode selection circuit MSC identifies the external input voltage V. IN And the phase-locked loop voltage signal, output voltage V C1 and V C2 Switches S1, S2, and S3 are controlled to control the frequency modulation mode of the loop oscillator OSC; the frequency modulation mode is an external clock frequency modulation mode and a resistor frequency modulation mode.

[0014] In the above oscillator circuit, the output voltage V C1 and V C2 The switches S1, S2, and S3 are controlled as follows:

[0015] When the input is the clock signal CLK, it is in external clock frequency modulation mode, and the output voltage V C1 The output is high, and the output voltage V C2 Low level; voltage V C1 When control switch S3 is closed, voltage V C2 Control switches S1 and S2 are open;

[0016] When the input port is a resistor R, it is in resistance frequency modulation mode, and the output voltage V C1 The output is low; V C2 When control switches S1 and S2 are closed, the voltage V C1 Control switch S3 is turned on.

[0017] In the above oscillator circuit, when the input is the clock signal CLK, the charge pump phase-locked loop (CPPLL) keeps the frequency of the loop oscillator OSC consistent with the external clock frequency; when the input port is a resistor R, the charge pump phase-locked loop (CPPLL) is multiplexed as an amplifier, transmitting the output signal of the voltage reference circuit VREF to the loop oscillator OSC.

[0018] In the above oscillator circuit, the charge pump phase-locked loop (CPPLL) includes: a frequency and phase detector (PFD), a charge pump (CP), and a low-pass filter (LPF); wherein, the output of the frequency and phase detector (PFD) is connected to the input of the charge pump (CP) to regulate the charging and discharging of the charge pump (CP); the output of the charge pump (CP) is connected to the input of the low-pass filter (LPF), and the output of the low-pass filter (LPF) is connected to the input of the loop oscillator (OSC) via switch S3, and is also connected to the mode selection circuit (MSC).

[0019] In the above oscillator circuit, the loop oscillator OSC, in external clock frequency modulation mode, has its bias current determined by the output voltage of the charge pump phase-locked loop (CPPLL), and in resistor frequency modulation mode, its bias current is determined by the current flowing through the external resistor. The bias current of the oscillator regulates the output frequency of the oscillator by charging and discharging the capacitor.

[0020] In the aforementioned oscillator circuit, the mode selection circuit MSC includes a hysteresis circuit SINV2, an inverter INV2, an SR latch, NMOS transistors M1 and M2, and a PMOS transistor M 203 In this circuit, the output of the charge pump phase-locked loop (CPPLL) is connected to the gate of M2; the drain voltage of NMOS transistor M1 is connected to the R terminal of the SR latch via SINV2 and INV2; the external input signal is connected to the S terminal of the SR latch; the source of NMOS transistor M2 is connected to ground; the drain of NMOS transistor M2 is connected to the source of NMOS transistor M1; the drain of NMOS transistor M1 is connected to the output of the current reference circuit IREF; and the positive output of the SR latch is connected to the gate of M1; PMOS transistor M... 203The drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M1 and the input of the hysteresis transistor SINV2; 203 The source and V DD connect.

[0021] The oscillator circuit described above also includes a hysteresis circuit SINV1 and an inverter INV1, with an external input signal V. IN After passing through hysteresis SINV1 and inverter INV1, the signal enters the charge pump phase-locked loop (CPPLL).

[0022] In the above oscillator circuit, the frequency and phase detector PFD includes D flip-flops D1 and D2 and a NAND gate; the D terminals of D flip-flops D1 and D2 are connected to the power supply V. DD External input signal V IN After passing through SINV1 and INV1, it is connected to the CK terminal of D flip-flop D1, and the oscillator outputs V. OSC The positive outputs of D1 and D2 are connected to the CK terminal of D2, and the positive outputs of D1 and D2 are connected to the inputs of the NAND gate. The outputs of the NAND gate are connected to the Reset terminals of D flip-flops D1 and D2.

[0023] In the above oscillator circuit, the charge pump CP includes a PMOS transistor M. 201 M 202 M 204 M 205 and M 206 With NMOS transistor M 207 M 208 and M 209 The positive output of the D flip-flop D1 is connected to the PMOS transistor M. 205 The gate terminal of the D flip-flop D1 is connected to the negative terminal of the PMOS transistor M. 204 The gate terminal of the D flip-flop D2 is connected to the positive output of the NMOS transistor M. 209 The gate terminal of the D flip-flop D2 is connected to the negative terminal of the NMOS transistor M. 208 The gate terminal of the PMOS transistor M 205 The source terminal is connected to the PMOS transistor M. 204 The drain terminal and PMOS transistor M 206 The source terminal, PMOS transistor M 205 The drain terminal of the PMOS transistor M 206 gate end, M 201 gate end, M 201 The drain end and M 202 The gate terminal is connected to the current source IREF, M 204 The source and V DD Connected.

[0024] In the above oscillator circuit, the loop oscillator OSC includes: an NMOS transistor M.303 ~M 307 M 310 M 311 M 314 and M 315 Capacitor C, PMOS transistor M 301 M 302 M 308 M 309 M 312 and M 313 ;in,

[0025] NMOS transistor M 303 The drain terminal is connected to the input V. OUT1 Enter V C2 Connect NMOS transistor M 303 and M 304 The gate terminal, input V C1 Connect NMOS transistor M 306 The gate terminal, input V CP Connect M 305 and M 307 The gate terminal, input V IN Connect the positive terminal of resistor R and M. 303 and M 304 The source terminal of resistor R is connected to ground, and the negative terminal of M is connected to ground. 304 The drain terminal is connected to the NMOS transistor M. 305 The source terminal and NMOS transistor M 306 The drain terminal of the NMOS transistor M 306 The source terminal is connected to the NMOS transistor M. 307 The drain end, M 307 The source terminal is connected to ground, and the power supply VDD is connected to the PMOS transistor M. 301 M 302 and M 312 The source terminal, PMOS transistor M 301 The gate terminal connection M 302 gate end, M 301 The drain end and M 305 The drain end, M 302 The drain end is connected to M 308 and M 309 The source terminal, PMOS transistor M 308 The gate terminal is connected to the output terminal of SINV1, the input terminal of INV1, and M. 312 The gate and M 315 The gate terminal, M 309 The gate terminal connects to the output terminal of INV1 and the output V. OSC M 308 The drain end is connected to M 310 The drain end, M 310 The gate terminal and NMOS transistor M 311 The gate terminal, M310 M 311 and M 315 The source terminal is connected to ground, and the PMOS transistor M 309 The drain terminal is connected to the NMOS transistor M. 311 The drain terminal, the input terminal of SINV1, and the M terminal. 313 gate end, M 314 The gate terminal and the positive terminal of capacitor C, M 312 The drain end is connected to M 313 The source terminal, PMOS transistor M 313 The drain terminal is connected to the negative terminal of capacitor C and NMOS transistor M. 314 The drain end, M 314 Source connection M 315 The leak end.

[0026] The advantages of this invention over the prior art are as follows:

[0027] (1) The present invention uses the same input terminal to perform frequency modulation in two modes. The circuit can automatically identify the frequency modulation mode according to the input signal, and can automatically switch the state when the input signal changes. There is no need to manually select the frequency modulation mode or switch the state by restarting.

[0028] (2) The two frequency modulation modes adopted in this invention control an oscillator to output signals of different frequencies, which helps to save circuit area and reduce the power consumption of the entire circuit.

[0029] (3) The present invention combines a charge pump phase-locked loop (CPPLL) and an amplifier, which play different roles in different modes, which helps to reduce the number of transistors and save circuit area. Attached Figure Description

[0030] Figure 1 This is a block diagram of the circuit structure of the present invention;

[0031] Figure 2 This is a schematic diagram of the phase-locked loop circuit and mode control circuit of the present invention;

[0032] Figure 3 This is a schematic diagram of the loop oscillator (OSC) circuit structure of the present invention;

[0033] Figure 4 This is the simulation curve for the present invention. Detailed Implementation

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] like Figure 1As shown, this invention discloses a dual-mode frequency-modulated oscillator circuit with a shared input terminal and an external clock. It comprises a voltage reference circuit (VREF), a current reference circuit (IREF), a mode selection circuit (MSC), a charge pump phase-locked loop (CPPLL), and a loop oscillator (OSC). This circuit can adjust the oscillator frequency using either a resistor or an external clock. Both modes share the same input terminal, and the mode selection circuit automatically identifies the two modulation modes based on the input signal. The PLL circuit consists of a phase-frequency discriminator (PFD), a charge pump (CP), and a low-pass filter (LPF), outputting a voltage signal. In external clock modulation mode, this voltage signal adjusts the oscillator frequency, synchronizing the oscillator signal with the external signal. In resistor mode, the output of the voltage reference circuit (VREF) keeps the voltage across the resistor constant, generating a current that depends only on the resistance value. This current controls the oscillator frequency. Since both modes share the same oscillator, and the signal output by the mode selection circuit controls the oscillator's input signal, using a single oscillator helps reduce circuit area and power consumption.

[0036] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0037] like Figure 1 As shown, the main components include a voltage reference circuit VREF, a current reference circuit IREF, a mode selection circuit MSC, a charge pump phase-locked loop CPPLL, and a loop oscillator OSC. NMOS transistors M1 and M2, hysteresis circuits SINV1 and SINV2, inverters INV1 and INV2, switches S1, S2 and S3, and an SR latch together constitute the mode selection circuit MSC. The frequency and phase detector PFD, the charge pump CP, and the low-pass filter LPF together constitute the charge pump phase-locked loop CPPLL.

[0038] The circuit has two input ports: a resistor R or a square wave signal CLK. When the input is CLK, the signal remains the same after passing through SINV1 and INV1. This signal, along with the output of OSC, acts on PFD. The output of PFD regulates the charging and discharging of the charge pump CP. The output of the charge pump, after being filtered by LPF, acts on the gate of M2, turning M2 on and setting the drain voltage low. The square wave signal acts on the S terminal of the SR latch. If V... C1 When the S terminal is low, the R terminal of the SR latch is high. When the S terminal is high, both terminals of the SR latch are high, which is an unstable state and will cause V to... C1 If the value at the S terminal is high, then the R terminal of the SR latch is low. At this time, the SR latch enters a holding state, regardless of whether the S terminal is high or low. C1 Both are high, V C2 It is low. In CLK state, V C1When control switch S3 is closed, the output of the low-pass filter, which is also the output of the phase-locked loop, controls the frequency of the output signal of the OSC module.

[0039] When the input is a resistor R, VREF is low. Regardless of whether S1 is open or not, the input is low after passing through SINV1 and INV1, meaning the S terminal of the SR latch is low. Assume the circuit was previously in CLK input mode, i.e., V... C1 If the value is high, the charge pump will continuously discharge, causing the gate of M2 to go low, turning off M2 and making the R terminal of the SR latch high. At this time, the output of the SR latch is determined by the S terminal. If the S terminal is low, then V... C1 For low, V C2 When the value is high, the SR latch output no longer changes. V C1 When control switches S1 and S2 are closed, VREF acts on the input resistor to form a current, which controls the frequency of the OSC module's output signal. Therefore, the input resistor and clock signal respectively cause V... C1 Different signals are output to control the frequency modulation mode of the oscillator.

[0040] Figure 1 In the middle, VREF is connected to the input port V via switch S1 and CPPLL. IN Connected, switch S1 is controlled by V C2 Control, V IN After being connected to the OSC input via S2, switch S2 is controlled by V. C2 Control, V IN After passing through SINV1 and INV1, it is connected to the input of PFD and the S terminal of SR latch. The output of OSC is connected to another input of PFD. The output of PFD is connected to the input of CP. IREF is connected to another input of CP and the drain terminal of M1. IREF is connected to the R terminal of SR latch via SINV2 and INV2. The output of CP is connected to the input of LPF. The output of LPF is connected to the gate terminal of M2. The output of LPF is connected to the input of OSC via S3. Switch S3 is connected to V C1 For control, the source terminal of M2 is connected to ground, the drain terminal of M2 is connected to the source terminal of M1, and the positive output of the SR latch is connected to the gate terminal of M1.

[0041] like Figure 2 The phase-locked loop circuit and mode control circuit shown use D flip-flops D1 and D2 and a NAND gate to form a PFD. When the input is a square wave signal CLK, the PMOS transistor M... 204 M 205 and M 206 With NMOS transistor M 207 M 208 and M 209 The resistor R1 and capacitors C1 and C2 form the capacitor CP, and the capacitor I forms the capacitor LPF. REFand PMOS transistor M 201 M 202 and M 203 To provide bias current to the circuit, when the input is a resistor, M 204 and M 208 Turn off, PMOS transistor M 210 M 211 and NMOS transistor M 207 M 209 M 212 M 213 This constitutes an amplifier, the function of which is to make V OUT1 and V REF Maintain consistency.

[0042] Figure 2 In the circuit, the D terminals of D flip-flops D1 and D2 are connected to the power supply VDD. IN After passing through SINV1 and INV1, it is connected to the CK terminal of D1 and the S terminal of the SR latch, and the oscillator outputs V. OSC Connect the CK terminal of D2 to the input of the NAND gate. Connect the positive outputs of D1 and D2 to the input of the NAND gate. Connect the output of the NAND gate to the Reset terminal of D1 and D2. Connect the positive output of D1 to the input of the NAND gate. 205 The gate terminal of D1, the negative terminal of D1 is connected to M. 204 The gate terminal of D2 and the positive terminal of D2 are connected to M. 209 The gate terminal of D2 and the negative terminal of D2 are connected to M. 208 The gate terminal, M 205 Source connection M 204 The drain end and M 206 The source end, M 205 The drain end and M 206 gate end, M 201 gate end, M 201 The drain end, M 202 gate end, M 203 Gate terminal, current source I REF Connected, M 204 The source end is connected to VDD, M 206 The drain end and M 207 The drain terminal, the positive terminal of resistor R1, the positive terminal of capacitor C2, and M 210 The drain terminal of M2, the gate terminal of M2, and the output V CP Connected, M 208 The drain end is connected to M 207 gate end, M 212 gate end, M 212 The drain end, M 211 The drain end, M 208 Source connection M 209 The drain end and M 207 The source end, M 209The source connection ground, M 201 M 202 M 203 and M 214 The source end is connected to VDD, M 202 The drain end is connected to M 210 The source and M 211 The source end, M 210 The gate terminal connection M 214 The drain and output V OUT1 M 211 The gate terminal is connected to the voltage reference V. REF M 212 Source connection M 213 The drain end, M 213 The gate terminal is connected to the power supply VDD, M 213 The drain of resistor R1 is connected to ground, the negative terminal of resistor R1 is connected to the positive terminal of capacitor C1, and the negative terminals of capacitors C1 and C2 are connected to ground. 214 The gate terminal connects to the negative terminal output and output V of the SR latch. C2 M 203 The drain of M1 is connected to the drain of M2, and after passing through SINV2 and INV2, it is connected to the R terminal of the SR latch. The source of M1 is connected to the drain of M2, and the source of M2 is connected to ground. The gate of M1 is connected to the positive output and output V of the SR latch. C1 A low-pass filter (LPF) consists of resistor R1 and capacitors C1 and C2.

[0043] like Figure 3 The loop oscillator (OSC) circuit shown has an NMOS transistor M. 303 It functions as a switch; when the input is a resistor, the output V... C2 Control M 303 When the circuit is turned on, the output V is turned on. C1 Control NMOS transistor M 306 Turn off, turn V OUT1 The voltage is transmitted across the input resistor, because V OUT1 M is led out from the gate terminal of the MOSFET. 303 There is almost no current between the drain and source, so the current through the input resistor R flows through the NMOS transistor M. 304 and M 305 For PMOS transistor M 301 and M 302 The current mirror is used for power supply, and the input resistance R determines the current magnitude. When the input is a clock signal, V C2 Control M 303 and M 304 Turn off, output V C1 Control NMOS transistor M 306 When the circuit is turned on, the output V is turned on. CP Voltage-controlled NMOS transistor M305 and M 307 The gate terminal, thereby controlling M 305 and M 307 The source and leakage current is the current mirror M. 301 and M 302 Power is supplied, and at this time the frequency of the input clock signal is affected by the charge pump phase-locked loop (CPPLL) V. CP The magnitude of the current is controlled by the size of the inverter SINV1. Assuming the output of the hysteresis circuit SINV1 is high, the output of the inverter INV1 is low, and the PMOS transistor M... 308 Turn off, PMOS transistor M 309 Turn on, NMOS transistor M 310 and M 311 Turn off, at this time M 301 and M 302 The current mirror formed is only for M 309 Power supply, current from M 309 When capacitor C is charged, due to the hysteresis threshold, the voltage at the positive terminal of capacitor C is not completely low. NMOS transistor M... 314 and M 315 Turn on, and at the same time, PMOS transistor M 312 and M 313 When the capacitor is turned off, the negative terminal of capacitor C discharges. When the voltage at the positive terminal of capacitor C rises, causing the output of SINV1 to flip low, the output of inverter INV2 becomes high, and M... 309 Off, M 308 On, M 310 and M 311 When M is turned on, 301 and M 302 The current in the constructed current mirror is the current flowing through M. 311 The current, the current from M 311 Discharging capacitor C to its positive terminal results in a non-high voltage due to the hysteresis's switching threshold. The PMOS transistor M... 312 and M 313 Turn on, and at the same time, NMOS transistor M 314 and M 315 When the circuit is off, the negative terminal of capacitor C is charged. When the voltage at the positive terminal of capacitor C drops, causing the SINV1 output to flip high, capacitor C completes one charging / discharging cycle. The magnitude of the charging / discharging current, i.e., the current mirror M... 301 and M 302 The output current determines the charging and discharging period of capacitor C. The loop oscillator (OSC) can charge both the positive and negative plates of the capacitor, thus generating an oscillation signal with a wider frequency range under the condition of a fixed capacitor value.

[0044] Figure 3 In the middle, M 303 The drain terminal is connected to the input V. OUT1Enter V C2 Connect M 303 and M 304 The gate terminal, input V C1 Connect M 306 The gate terminal, input V CP Connect M 305 and M 307 The gate terminal, input V IN Connect the positive terminal of resistor R and M. 303 and M 304 The source terminal of resistor R is connected to ground, and the negative terminal of M is connected to ground. 304 The drain end is connected to M 305 The source and M 306 The drain end, M 306 Source connection M 307 The drain end, M 307 The source terminal is connected to ground, and the power supply VDD is connected to M. 301 M 302 and M 312 The source end, M 301 The gate terminal connection M 302 gate end, M 301 The drain end, M 305 The drain end, M 302 The drain end is connected to M 308 and M 309 The source end, M 308 The gate terminal is connected to the output terminal of SINV1, the input terminal of INV1, and M. 312 The gate and M 315 The gate terminal, M 309 The gate terminal connects to the output terminal of INV1 and the output V. OSC M 308 The drain end is connected to M 310 The drain end, M 310 The gate and M 311 The gate terminal, M 310 M 311 and M 315 The source connection ground, M 309 The drain end is connected to M 311 The drain terminal, the input terminal of SINV1, and the M terminal. 313 gate end, M 314 The gate terminal and the positive terminal of capacitor C, M 312 The drain end is connected to M 313 The source end, M 313 The drain terminal is connected to the negative terminal of capacitor C and M. 314 The drain end, M 314 Source connection M 315 The leak end.

[0045] The mode selection circuit (MSC) identifies the input signal. When the input port is a resistor or a square wave signal, it outputs different control signals to determine the oscillator's output frequency. This circuit shares the same input terminal for both the resistor and the external clock frequency modulation, and the two modes can be switched without requiring a restart circuit.

[0046] In use, the dual-mode frequency-modulated oscillator circuit with a common input resistor and an external clock proposed in this invention provides an oscillator output signal as follows: Figure 4 As shown in (a), when the input signal is a frequency-sensitive signal, the frequency of the output signal follows the input signal; when the input is a fixed resistor, the frequency of the output signal is determined by the input resistance. Figure 4 (b) is the control signal V C1 Waveform, V C1 The signal will switch between high and low levels depending on the type of input signal, such as the input signal frequency. Figure 4 As shown in (c), an input signal frequency of zero indicates that the input is a fixed resistor. The circuit operates in a temperature range of -40 to 85°C. The loop oscillator OSC capacitor requires only 260fF. The external signal frequency modulation and resistor frequency modulation ranges from 300kHz to 2MHz. When the oscillator output signal frequency is 1MHz, the circuit power consumption is 10μA. The mode selection circuit switches the frequency modulation mode of the circuit according to the external input signal. The switching time between the two modes, external clock frequency modulation of 2MHz and resistor frequency modulation of 1MHz, is only 50μs.

[0047] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0048] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

[0049] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A dual-mode frequency-modulated oscillator circuit with a common input resistor and an external clock, characterized in that, It includes a voltage reference circuit VREF, a current reference circuit IREF, a mode selection circuit MSC, a charge pump phase-locked loop CPPLL, a loop oscillator OSC, and switches S1, S2, and S3; among which, The voltage reference circuit VREF generates a fixed voltage, which is output to the charge pump phase-locked loop CPPLL through switch S1. The current reference circuit IREF is used to generate the fixed current required for the charge pump phase-locked loop (CPPLL) to charge and discharge, and to provide current to the mode selection circuit (MSC). The loop oscillator (OSC) has its input terminal connected to the external input voltage V via switch S2. IN Connection, based on external input voltage V IN The phase-locked loop voltage signal output from the charge pump phase-locked loop (CPPLL) generates an oscillating voltage signal V. OSC The output is supplied to the charge pump phase-locked loop (CPPLL) and external circuitry. Charge pump phase-locked loop (CPPLL) based on external input voltage V IN and oscillating voltage signal V OSC The frequency difference is used to output a phase-locked loop voltage signal to the mode selection circuit MSC; the output phase-locked loop voltage signal is then output to the loop oscillator OSC via switch S3. The mode selection circuit MSC identifies the external input voltage V. IN And the phase-locked loop voltage signal, output voltage V C1 and V C2 Switches S1, S2, and S3 are controlled to control the frequency modulation mode of the loop oscillator OSC; the frequency modulation mode is an external clock frequency modulation mode and a resistor frequency modulation mode.

2. The dual-mode frequency-modulated oscillator circuit with a common input terminal resistor and an external clock according to claim 1, characterized in that: The output voltage V C1 and V C2 The switches S1, S2, and S3 are controlled as follows: When the input is the clock signal CLK, it is in external clock frequency modulation mode, and the output voltage V C1 The output is high, and the output voltage V C2 Low level; voltage V C1 When control switch S3 is closed, voltage V C2 Control switches S1 and S2 are open; When the input port is a resistor R, it is in resistance frequency modulation mode, and the output voltage V C1 The output is low; V C2 When control switches S1 and S2 are closed, the voltage V C1 Control switch S3 is turned on.

3. The dual-mode frequency-modulated oscillator circuit with a shared input terminal resistor and an external clock according to claim 2, characterized in that, When the input is a clock signal CLK, the charge pump phase-locked loop (CPPLL) keeps the frequency of the loop oscillator (OSC) consistent with the external clock frequency; when the input port is a resistor R, the CCPPLL is multiplexed as an amplifier, transmitting the output signal of the voltage reference circuit VREF to the loop oscillator (OSC).

4. The dual-mode frequency-modulated oscillator circuit with a shared input terminal resistor and an external clock according to claim 1, characterized in that, The charge pump phase-locked loop (CPPLL) includes: a frequency and phase detector (PFD), a charge pump (CP), and a low-pass filter (LPF); wherein, the output of the frequency and phase detector (PFD) is connected to the input of the charge pump (CP) to regulate the charging and discharging of the charge pump (CP); the output of the charge pump (CP) is connected to the input of the low-pass filter (LPF), and the output of the low-pass filter (LPF) is connected to the input of the loop oscillator (OSC) via switch S3, and is also connected to the mode selection circuit (MSC).

5. The dual-mode frequency-modulated oscillator circuit with a common input terminal resistor and an external clock as described in claim 1, characterized in that, In the external clock frequency modulation mode, the oscillator bias current of the loop oscillator (OSC) is determined by the output voltage of the charge pump phase-locked loop (CPPLL). In the resistor frequency modulation mode, the oscillator bias current is determined by the current flowing through the external resistor. The bias current of the oscillator regulates the output frequency of the oscillator by charging and discharging the capacitor.

6. The dual-mode frequency-modulated oscillator circuit with a common input terminal resistor and an external clock according to claim 1, characterized in that: The mode selection circuit MSC includes a hysteresis circuit SINV2, an inverter INV2, an SR latch, NMOS transistors M1 and M2, and a PMOS transistor M. 203 In this circuit, the output of the charge pump phase-locked loop (CPPLL) is connected to the gate of M2; the drain voltage of NMOS transistor M1 is connected to the R terminal of the SR latch via SINV2 and INV2; the external input signal is connected to the S terminal of the SR latch; the source of NMOS transistor M2 is connected to ground; the drain of NMOS transistor M2 is connected to the source of NMOS transistor M1; the drain of NMOS transistor M1 is connected to the output of the current reference circuit IREF; and the positive output of the SR latch is connected to the gate of M1; PMOS transistor M... 203 The drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M1 and the input of the hysteresis transistor SINV2; 203 The source and V DD connect.

7. The dual-mode frequency-modulated oscillator circuit with a common input terminal resistor and an external clock according to claim 1, characterized in that: It also includes a hysteresis circuit SINV1 and an inverter INV1, and an external input signal V. IN After passing through hysteresis SINV1 and inverter INV1, the signal enters the charge pump phase-locked loop (CPPLL).

8. The dual-mode frequency-modulated oscillator circuit with a common input terminal resistor and an external clock according to claim 4, characterized in that: The frequency and phase detector (PFD) includes D flip-flops D1 and D2 and a NAND gate; the D terminals of D flip-flops D1 and D2 are connected to the power supply V. DD External input signal V IN After passing through SINV1 and INV1, it is connected to the CK terminal of D flip-flop D1, and the oscillator outputs V. OSC The positive outputs of D1 and D2 are connected to the CK terminal of D2, and the positive outputs of D1 and D2 are connected to the inputs of the NAND gate. The outputs of the NAND gate are connected to the Reset terminals of D flip-flops D1 and D2.

9. The dual-mode frequency-modulated oscillator circuit with a common input terminal resistor and an external clock according to claim 4, characterized in that: The charge pump CP includes a PMOS transistor M 201 M 202 M 204 M 205 and M 206 With NMOS transistor M 207 M 208 and M 209 ; The positive output of D flip-flop D1 is connected to PMOS transistor M. 205 The gate terminal of the D flip-flop D1 is connected to the negative terminal of the PMOS transistor M. 204 The gate terminal of the D flip-flop D2 is connected to the positive output of the NMOS transistor M. 209 The gate terminal of the D flip-flop D2 is connected to the negative terminal of the NMOS transistor M. 208 The gate terminal of the PMOS transistor M 205 The source terminal is connected to the PMOS transistor M. 204 The drain terminal and PMOS transistor M 206 The source terminal, PMOS transistor M 205 The drain terminal of the PMOS transistor M 206 gate end, M 201 gate end, M 201 The drain end and M 202 The gate terminal is connected to the current source IREF, M 204 The source and V DD Connected.

10. The dual-mode frequency-modulated oscillator circuit with a common input terminal resistor and an external clock according to claim 1, characterized in that: The loop oscillator (OSC) includes: an NMOS transistor M 303 ~M 307 M 310 M 311 M 314 and M 315 Capacitor C, PMOS transistor M 301 M 302 M 308 M 309 M 312 and M 313 ;in, NMOS transistor M 303 The drain terminal is connected to the input V. OUT1 Enter V C2 Connect NMOS transistor M 303 and M 304 The gate terminal, input V C1 Connect NMOS transistor M 306 The gate terminal, input V CP Connect M 305 and M 307 The gate terminal, input V IN Connect the positive terminal of resistor R and M. 303 and M 304 The source terminal of resistor R is connected to ground, and the negative terminal of M is connected to ground. 304 The drain terminal is connected to the NMOS transistor M. 305 The source terminal and NMOS transistor M 306 The drain terminal of the NMOS transistor M 306 The source terminal is connected to the NMOS transistor M. 307 The drain end, M 307 The source terminal is connected to ground, and the power supply VDD is connected to the PMOS transistor M. 301 M 302 and M 312 The source terminal, PMOS transistor M 301 The gate terminal connection M 302 gate end, M 301 The drain end and M 305 The drain end, M 302 The drain end is connected to M 308 and M 309 The source terminal, PMOS transistor M 308 The gate terminal is connected to the output terminal of SINV1, the input terminal of INV1, and M. 312 The gate and M 315 The gate terminal, M 309 The gate terminal connects to the output terminal of INV1 and the output V. OSC M 308 The drain end is connected to M 310 The drain end, M 310 The gate terminal and NMOS transistor M 311 The gate terminal, M 310 M 311 and M 315 The source terminal is connected to ground, and the PMOS transistor M 309 The drain terminal is connected to the NMOS transistor M. 311 The drain terminal, the input terminal of SINV1, and the M terminal. 313 gate end, M 314 The gate terminal and the positive terminal of capacitor C, M 312 The drain end is connected to M 313 The source terminal, PMOS transistor M 313 The drain terminal is connected to the negative terminal of capacitor C and NMOS transistor M. 314 The drain end, M 314 Source connection M 315 The leak end.

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