A method for preparing a laminated superconducting structure, a laminated superconducting structure and a quantum chip

Abstract

The application discloses a preparation method of a laminated superconducting structure, the laminated superconducting structure and a quantum chip, and belongs to the field of quantum chip preparation. The preparation method of the laminated superconducting structure comprises the following steps: providing a substrate with a first superconducting metal layer on the surface; forming a protective layer on the first superconducting metal layer; forming a dielectric layer covering the protective layer on the first superconducting metal layer; etching the dielectric layer with the protective layer as an etching stop layer to form an opening exposing the protective layer; etching the protective layer with a large etching selectivity ratio of the protective layer to the first superconducting metal layer, so that the first superconducting metal layer is exposed; and forming a second superconducting metal layer connected with the first superconducting metal layer on the dielectric layer and in the opening. Through the above method, when tantalum, tin and other materials are used to manufacture superconducting layers in the manufacturing process of the quantum chip laminated structure, the application can effectively prevent the superconducting layer from being etched too much during the etching of the dielectric layer, so that the circuit is broken.

Description

Technical Field

[0001] This application belongs to the field of quantum chip fabrication technology, and in particular relates to a method for fabricating a stacked superconducting structure, the stacked superconducting structure, and a quantum chip. Background Technology

[0002] In quantum chips, due to the complex coupling between qubits and the requirement for high interconnectivity, the previous two-dimensional planar wiring technology can no longer meet the needs of current qubit development. To solve the wiring complexity problem in quantum chips, stacked superconducting structures have been gradually introduced; a stacked superconducting structure refers to the introduction of two or more parallel metal layers into the quantum chip, dividing the superconducting metal layers into multiple horizontal layers.

[0003] The process of stacked superconducting structures generally requires filling the superconducting layers with low-loss dielectric material. The stacked superconducting layers are connected by etched vias in the dielectric layers. Since the dielectric layer causes losses, the superconducting layers can be made of tantalum films, tin films, etc., which have better performance than traditional aluminum films. The quality factor and coherence time of tantalum films and tin films are better than those of aluminum films. The dielectric layer is usually made of materials such as silicon nitride, germanium, and single crystal silicon. Fluorine-based plasma etching is generally used for etching the dielectric layer. However, fluorine-based plasma can also etch the superconducting layer made of tantalum films and tin films, making it difficult to control the etching endpoint. This may result in the superconducting layer being etched during the etching of the dielectric layer, causing an open circuit. Summary of the Invention

[0004] The purpose of this application is to provide a method for fabricating a stacked superconducting structure, the stacked superconducting structure, and a quantum chip, in order to solve the problem in the prior art that the superconducting layer is easily etched during the etching of the dielectric layer by fluorine-based ions, resulting in a circuit break. This method can protect the superconducting layer from the effect of etching while ensuring that the dielectric layer is well etched.

[0005] To solve the above-mentioned technical problems, the present invention provides a method for preparing a stacked superconducting structure, comprising:

[0006] Provide a substrate having a first superconducting metal layer on its surface;

[0007] A protective layer is formed on the first superconducting metal layer;

[0008] A dielectric layer covering the protective layer is formed on the first superconducting metal layer;

[0009] The protective layer is used as an etching stop layer to etch the dielectric layer, forming an opening that exposes the protective layer;

[0010] The protective layer is etched with a selectivity ratio greater than 1 relative to the first superconducting metal layer to expose the first superconducting metal layer;

[0011] A second superconducting metal layer is formed on the dielectric layer and within the opening, connecting the first superconducting metal layer.

[0012] Preferably, the step of forming a protective layer on the first superconducting metal layer includes:

[0013] A first photoresist layer is formed on the first superconducting metal layer;

[0014] Photolithography is used to form vias in the first photoresist layer, exposing portions of the first superconducting metal layer.

[0015] A protective layer is deposited on the first superconducting metal layer through the via;

[0016] Remove the first photoresist layer.

[0017] Preferably, the through hole is frustum-shaped, and the size of the end closer to the first superconducting metal layer is larger than the size of the end farther away from the first superconducting metal layer.

[0018] Preferably, the step of etching the dielectric layer using the protective layer as an etching stop layer to form an opening exposing the protective layer includes:

[0019] A second photoresist layer is formed on the dielectric layer;

[0020] Using photolithography, a window is formed in the region of the second photoresist layer relative to the protective layer to expose the dielectric layer;

[0021] The opening is formed by etching the dielectric layer through the window;

[0022] Remove the second photoresist layer.

[0023] Preferably, the window and the opening are of the same size;

[0024] The size of the opening is no larger than the size of the protective layer.

[0025] Preferably, the etching of the dielectric layer is performed using fluorine-based plasma etching.

[0026] Preferably, the material of the protective layer is aluminum;

[0027] The material of the first superconducting metal layer is tantalum or tin;

[0028] The protective layer is removed by etching with a mixed acid etching solution.

[0029] Preferably, the step of forming a second superconducting metal layer connecting the first superconducting metal layer on the dielectric layer and within the opening includes:

[0030] Etch the oxide layer located on the first superconducting metal layer;

[0031] A second superconducting metal layer is formed on the dielectric layer and within the opening, connecting the first superconducting metal layer.

[0032] The present invention also provides a stacked superconducting structure, which is prepared by the method for preparing a stacked superconducting structure as described in any of the foregoing embodiments.

[0033] The present invention also provides a quantum chip comprising the aforementioned stacked superconducting structure.

[0034] Compared with the prior art, this application adds a protective layer between the dielectric layer and the first superconducting metal layer in advance. This protective layer is not affected by the etching when the dielectric layer is etched and can be removed by other processes. In this way, the problem of difficulty in controlling the etching endpoint when etching the dielectric layer in the traditional process is avoided, and the first superconducting metal layer is protected, thereby better realizing the fabrication of the quantum chip stacked wiring structure. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of a quantum chip stacked superconducting structure provided in an embodiment of the present invention;

[0036] Figure 2 This is a schematic diagram of the fabrication method of the quantum chip stacked superconducting structure provided in an embodiment of the present invention;

[0037] Figure 3 , Figure 4 and Figure 5 This is a schematic diagram illustrating the steps of a method for fabricating a quantum chip stacked superconducting structure according to an embodiment of the present invention.

[0038] Explanation of reference numerals in the attached figures: 1 - substrate, 2 - first superconducting metal layer, 3 - first photoresist layer, 31 - via, 4 - protective layer, 5 - dielectric layer, 51 - opening, 6 - second photoresist layer, 61 - window, 7 - second superconducting metal layer. Detailed Implementation

[0039] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0040] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0042] As disclosed in the background section, in the field of quantum chip fabrication technology, due to the complex coupling between qubits and the requirement for high interconnectivity, stacked superconducting structures have been gradually introduced. This involves introducing multiple parallel metal layers into the quantum chip, dividing the superconducting metal layers into multiple horizontal layers. During the fabrication process, due to the material properties of the superconducting layer and the dielectric layer, when etching the dielectric layer, the etching endpoint is difficult to control, which may lead to the etching of the superconducting layer and cause an open circuit.

[0043] Please refer to Figure 2 To address the aforementioned problems, this invention provides a method for fabricating a stacked superconducting structure, the stacked superconducting structure itself, and a quantum chip. A protective layer 4 is added between the dielectric layer 5 and the first superconducting metal layer 2. During etching of the dielectric layer 5, this protective layer 4 is unaffected by the etching process, thus protecting the first superconducting metal layer 2. Furthermore, this protective layer 4 can be completely removed using other techniques before subsequent processes, thereby achieving the fabrication of the quantum chip's stacked superconducting structure. The first superconducting metal layer 2 incorporates structures such as qubits and resonant cavities, while the second superconducting metal layer 7 incorporates structures such as control lines.

[0044] Please refer to Figure 1 This invention provides a method for preparing a stacked superconducting structure. This method can be used to prepare a stacked superconducting structure. The method controls the etching endpoint when etching the dielectric layer 5 to avoid etching the bottom superconducting layer, thereby preventing the first superconducting metal layer 2 from being open-circuited.

[0045] The method for preparing a stacked superconducting structure provided in this embodiment of the invention includes the following steps:

[0046] S1: Provide a substrate 1 with a first superconducting metal layer 2 on its surface.

[0047] Specifically, a substrate is first provided, which may be a substrate 1, such as a silicon substrate 1, a silicon dioxide substrate 1, or a sapphire substrate 1, and a first superconducting metal layer 2 is formed on the substrate 1 by processes such as electroplating, deposition, or mounting.

[0048] In this process, the first superconducting metal layer 2 located on the surface of the substrate 1 is photolithographically etched to form quantum devices such as transmission lines and resonators, and a portion of the area away from the quantum devices is left as a connection area with other superconducting metal layers.

[0049] S2: A protective layer 4 is formed on the first superconducting metal layer 2.

[0050] Please refer to Figure 3 The step of forming a protective layer 4 on the first superconducting metal layer 2 further includes:

[0051] A first photoresist layer 3 is formed on the first superconducting metal layer 2;

[0052] Photolithography is used to form a via 31 that exposes a portion of the first superconducting metal layer 2 in the first photoresist layer 3;

[0053] A protective layer 4 is deposited on the first superconducting metal layer 2 through the through-hole 31;

[0054] Remove the first photoresist layer 3.

[0055] Specifically, in the prior art, the endpoint of etching the dielectric layer 5 is not easy to control, and it is easy to continue etching the first superconducting metal layer 2 after etching through the dielectric layer 5, resulting in the first superconducting metal layer 2 being short-circuited by etching. Therefore, in this embodiment, a protective layer 4 is provided. In the etching direction, the protective layer 4 is located between the first superconducting metal layer 2 and the dielectric layer 5, and is used to protect the first superconducting layer from being etched after etching the dielectric layer 5. The material of the protective layer 4 can be aluminum.

[0056] In addition, the steps to form the protective layer 4 at the corresponding position on the first superconducting metal layer 2 are as follows:

[0057] First, a first photoresist layer 3 is deposited on the first superconducting metal layer 2. The first photoresist layer 3 is exposed and developed to form a through-hole 31. Then, an aluminum film is deposited on the first superconducting metal layer 2 through the through-hole 31. Finally, the first photoresist layer 3 is dissolved by soaking in an organic solvent. The aluminum film mentioned here is a protective layer 3.

[0058] It is worth noting that the first photoresist layer 3 is a negative photoresist, and the exposed areas of the negative photoresist are difficult to dissolve in the developer. Exposure of the negative photoresist causes the photoresist to cross-link, resulting in high exposure intensity and strong cross-linking in the upper region of the first photoresist layer 3, and low exposure intensity and weak cross-linking in the lower region. Therefore, the upper and lower regions of the first photoresist layer 3 have different dissolution rates in the developer, which means that the solubility of the first photoresist layer 3 gradually increases from top to bottom. This results in the formation of a structure that is narrow at the top and wide at the bottom after development of the first photoresist layer 3, which is conducive to peeling.

[0059] Regarding the via 31 formed by the exposure and development of the first photoresist layer 3, the via 31 is specifically frustum-shaped, that is, the aforementioned structure that is narrower at the top and wider at the bottom, meaning that the size at the end closer to the first superconducting metal layer 2 is larger than the size at the end farther away from the first superconducting metal layer 2. The aforementioned via 31 with a narrower top and wider bottom structure has advantages, specifically: when depositing the protective layer 4 on the first superconducting metal layer 2 through the via 31, the narrower top and wider bottom structure of the via 31 makes it difficult for the protective layer 4 film to be deposited on the photoresist sidewalls. This allows the organic solution to dissolve the first photoresist layer 3 through the sidewalls of the via 31 during subsequent stripping, and the aluminum film on the first photoresist layer 3 also detaches, leaving only the aluminum film attached to the first superconducting metal layer 2. If the via 31 of the first photoresist layer 3 has a vertical structure or a structure that is wider at the top and narrower at the bottom, the sidewalls of the via 31 will be more easily coated with aluminum film when the protective layer 4 is deposited, which will cause the solution to not be able to fully contact the first photoresist layer 3 when the organic solvent is immersed, thus affecting the peeling of the first photoresist layer 3.

[0060] S3: A dielectric layer 5 is formed on the first superconducting metal layer 2, which is covered with a protective layer 4.

[0061] Please refer to Figure 4 The dielectric layer 5 not only serves as a support layer between the first superconducting metal layer 2 and the second superconducting metal layer 7, but also prevents crosstalk between adjacent superconducting metal layers. Its thickness is generally 5 to 10 times that of the first superconducting metal layer, and can be specifically set to 1 μm. Its material is generally a dielectric material such as silicon nitride, germanium, or single crystal silicon, and it can be etched.

[0062] S4: Using the protective layer 4 as an etching stop layer, the dielectric layer 5 is etched to form an opening 51 that exposes the protective layer 4.

[0063] Specifically, the dielectric layer 5 is etched using a fluorine-based gas to form an opening 51 that penetrates the dielectric layer 5. It is worth noting that fluorine-based gas is generally used to etch the dielectric layer 5, and it cannot etch the protective layer 4 - aluminum film. Therefore, the protective layer 4 plays a role in protecting the first superconducting metal layer 2, preventing the first superconducting metal layer 2 from being etched due to the inability to control the etching endpoint of the dielectric layer 5, which would lead to an open circuit.

[0064] In this embodiment, the steps of etching the dielectric layer 5 using the protective layer 4 as an etching stop layer to form an opening 51 exposing the protective layer 4 are as follows:

[0065] A second photoresist layer 6 is formed on the dielectric layer 5;

[0066] Using photolithography, a window 61 is formed in the region of the second photoresist layer 6 relative to the protective layer 4 to expose the stop layer;

[0067] The dielectric layer 5 is etched through window 61 to form opening 51;

[0068] Remove the second photoresist layer 6.

[0069] Specifically, a second photoresist layer 6 is formed on the dielectric layer 5, and a window 61 exposing the dielectric layer 5 is formed in the region of the second photoresist layer 6 opposite to the protective layer 4 using photolithography. The purpose of this is to provide positioning for subsequent etching in the region where the second photoresist layer 6 and the protective layer 4 are opposite. It is worth noting that the opening 51 formed by etching the dielectric layer 5 through the window 61 has the same size as the window 61 of the first photoresist layer 3, and the size of the opening 51 and the window 61 is not larger than the size of the protective layer 4. The purpose is to ensure that the protective layer 4 can completely protect the first superconducting metal layer 2 when etching the dielectric layer 5. If the size of the opening 51 and the window 61 is larger than the size of the protective layer 4, part of the first superconducting metal layer 2 will be etched, resulting in an open circuit in the first superconducting metal layer 2. After the above process is completed, the second photoresist layer 6 is cleaned and removed using an organic solution.

[0070] S5: Etch the protective layer (4) with an etching selectivity greater than 1 relative to the first superconducting metal layer (2) to expose the first superconducting metal layer (2).

[0071] Please refer to Figure 5 After etching the dielectric layer 5, the function of the protective layer 4 has been fully achieved. To continue etching the dielectric layer 5, the protective layer 4 needs to be removed. In this embodiment, the material of the protective layer 4 is aluminum, and the material of the first superconducting metal layer 2 is tantalum or tin. Therefore, the protective layer 4 can be removed using an aluminum etching solution (a mixed acid, a mature semiconductor aluminum wet etching solution, the main component of which is nitric acid), exposing the portion of the first superconducting metal layer 2 covered by the protective layer 4, so as to carry out subsequent processes.

[0072] S6: A second superconducting metal layer 7 is formed on the dielectric layer 5 and inside the opening 51 to connect the first superconducting metal layer 2.

[0073] The steps are as follows: etching the oxide layer located on the first superconducting metal layer 2;

[0074] A second superconducting metal layer 7 is formed on the dielectric layer 5 and within the opening 51, connecting the first superconducting metal layer 2.

[0075] After the protective layer 4 is completely removed, an oxide layer will form on the surface of the first superconducting metal layer 2 when it comes into contact with oxygen. This oxide layer will reduce or even block the connection between the first superconducting metal layer 2 and the second superconducting metal layer 7. Therefore, after removing the protective layer 4, the surface of the first superconducting metal layer 2 needs to be etched with argon plasma to remove the surface oxide layer.

[0076] Finally, a second superconducting metal layer 7 is formed on the dielectric layer 5 and on the inner wall of the opening 51 etched in the dielectric layer 5, and the second superconducting metal layer 7 is electrically connected to the first superconducting metal layer 2 in the opening 51.

[0077] The present invention also provides a stacked superconducting structure, which is prepared by the method for preparing a stacked superconducting structure as described in any of the foregoing embodiments.

[0078] This invention also provides a quantum chip, including the aforementioned stacked superconducting structure. Further details are omitted here.

[0079] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0080] The above description, based on the embodiments shown in the drawings, details the structure, features, and effects of this application. The above description is only a preferred embodiment of this application, but this application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of this application, or modifications to equivalent embodiments, that do not exceed the spirit covered by the specification and drawings, should be within the protection scope of this application.

Claims

1. A method for preparing a stacked superconducting structure, characterized in that, include: A substrate (1) having a first superconducting metal layer (2) on its surface is provided; A protective layer (4) is formed on the first superconducting metal layer (2); A dielectric layer (5) covering the protective layer (4) is formed on the first superconducting metal layer (2). The protective layer (4) is used as an etching stop layer to etch the dielectric layer (5) to form an opening (51) that exposes the protective layer (4). The size of the opening (51) is not greater than the size of the protective layer (4). The protective layer (4) is etched with a selection ratio of greater than 1 relative to the first superconducting metal layer (2) to expose the first superconducting metal layer (2). A second superconducting metal layer (7) connecting the first superconducting metal layer (2) is formed on the dielectric layer (5) and in the opening (51).

2. The method for preparing the stacked superconducting structure according to claim 1, characterized in that, The step of forming a protective layer (4) on the first superconducting metal layer (2) includes: A first photoresist layer (3) is formed on the first superconducting metal layer (2); Photolithography is used to form a via (31) that exposes a portion of the first superconducting metal layer (2). A protective layer (4) is deposited on the first superconducting metal layer (2) through the through-hole (31). Remove the first photoresist layer (3).

3. The method for preparing the stacked superconducting structure according to claim 2, characterized in that, The through hole (31) is frustum shaped, and the size of the end near the first superconducting metal layer (2) is larger than the size of the end away from the first superconducting metal layer (2).

4. The method for preparing the stacked superconducting structure according to claim 1, characterized in that, The step of etching the dielectric layer (5) using the protective layer (4) as an etching stop layer to form an opening (51) exposing the protective layer (4) includes: A second photoresist layer (6) is formed on the dielectric layer (5); Using photolithography, a window (61) is formed in the region of the second photoresist layer (6) relative to the protective layer (4) to expose the dielectric layer (5). The dielectric layer (5) is etched through the window (61) to form the opening (51) with the same size as the window (61). Remove the second photoresist layer (6).

5. The method for preparing the stacked superconducting structure according to claim 4, characterized in that, The window (61) and the opening (51) are the same size; The size of the opening (51) is not greater than the size of the protective layer (4).

6. The method for preparing the stacked superconducting structure according to claim 4, characterized in that, The etching of the dielectric layer (5) is performed using fluorine-based plasma etching.

7. The method for preparing the stacked superconducting structure according to claim 1, characterized in that, The material of the protective layer (4) is aluminum; The material of the first superconducting metal layer (2) is tantalum or tin; The protective layer (4) is removed by etching with a mixed acid etching solution.

8. The method for preparing the stacked superconducting structure according to claim 1, characterized in that, The step of forming a second superconducting metal layer (7) connecting the first superconducting metal layer (2) on the dielectric layer (5) and within the opening (51) includes: Etch the oxide layer located on the first superconducting metal layer (2); A second superconducting metal layer (7) connecting the first superconducting metal layer (2) is formed on the dielectric layer (5) and in the opening (51).

9. A stacked superconducting structure, characterized in that, It is prepared using the method for preparing the stacked superconducting structure as described in any one of claims 1 to 8.

10. A quantum chip, characterized in that, Including the stacked superconducting structure as described in claim 9.

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