Cold data detector in memory system

Abstract

A cold data detector circuit includes a bubble burst register configured to detect cold data in a memory system including a primary memory and a secondary memory. The bubble burst register selectively shifts a received fragment address to fill empty time slots without having to wait until the empty time slots are shifted out of an end time slot, and can provide an indication of cold data in response to each time slot of the register being filled with a different respective fragment address.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Patent Application No. 17 / 200,421, filed March 12, 2021. This application is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] This disclosure generally relates to memory systems, and more specifically, to cold data detectors within memory systems. Background Technology

[0004] Hybrid memory systems can store frequently accessed data in lower-latency memory and move less frequently accessed data (e.g., cold data) to higher-latency memory as available storage space in the lower-latency memory decreases. However, the counters and other circuitry used to detect cold data in the lower-latency memory can consume additional power and space on the die, which can reduce storage capacity and degrade the performance of the low-latency memory. Summary of the Invention

[0005] An example device is described herein. One example device may include: a memory cell array comprising a plurality of rows, wherein each row contains a corresponding plurality of segments, each segment being associated with a corresponding segment address; and cold data detector circuitry corresponding to a row and including a register having a plurality of time slots configured to store received segment addresses. In response to detecting that each of the corresponding segments in the row has been subjected to at least one access operation, the cold data detector circuitry may be configured to provide the longest stored segment address from the register to an output as a cold address. Alternatively, during an access operation associated with a target segment among the corresponding segments, each of the plurality of time slots preceding a specific time slot in the plurality of time slots of the register that is indicated to be empty is shifted by one time slot to fill the specific time slot, such that a first end time slot among the plurality of time slots is available to receive the corresponding target segment address associated with the target segment. Alternatively, each of the plurality of time slots following the specific time slot retains the existing corresponding segment address. Alternatively, during an access operation associated with a target segment among the respective plurality of segments, the cold data detector circuitry is configured to compare the corresponding segment address stored in a register with the corresponding target segment address, and in response to determining that one of the corresponding segment addresses stored in the register matches the corresponding target segment address, the cold data detector circuitry is configured to invalidate said one of the corresponding segment addresses stored in the register and store the corresponding target segment address in the register. Alternatively, the example device may include cold data readout circuitry having a shift register configured to store a cold address in a specific location. Alternatively, the memory cell array further includes a second cold data detector circuitry corresponding to a second row of a plurality of rows, and the second cold data detector circuitry includes a second register having a second plurality of time slots configured to store received segment addresses associated with the respective plurality of segments of the second row. In response to detecting that each of the respective plurality of segments of the second row has been subjected to at least one access operation, the second cold data detector circuitry is configured to provide the longest stored segment address from the second register to an output as a second cold address. Alternatively, the example device may include a plurality of cold data detector circuits, each of the plurality of cold data detector circuits corresponding to a corresponding row in a plurality of rows, wherein in response to detecting that each of the respective plurality of segments in the corresponding row has been subjected to at least one access operation, and each of the plurality of cold data detector circuits may be configured to provide the address of the corresponding longest stored segment from the corresponding register as the corresponding cold address.Alternatively, the example device may further include cold data readout circuitry having a shift register with multiple time slots, each time slot configured to store a corresponding cold address from a specific one of a plurality of cold data detector circuits, and the cold data readout circuitry may be configured to initiate the transfer of cold data from the memory cell array to another memory in response to receiving a row fill signal from each of the plurality of cold data detectors. Alternatively, the cold data readout circuitry may be further configured to update a mode register in response to the transfer of cold data from the memory cell array to another memory. Alternatively, the memory cell array may include volatile memory cells. Alternatively, the other memory may include non-volatile memory.

[0006] A second example device may include: a first memory having a first access latency, and a second memory having a second access latency less than the first access latency. The second memory may include a memory cell array comprising a plurality of rows, each of the plurality of rows comprising a corresponding plurality of segments, each of the respective plurality of segments being associated with a corresponding segment address. The second memory may further include a plurality of cold data detector circuitry, each of the plurality of cold data detector circuitry corresponding to a corresponding one of the plurality of rows and each including a corresponding register. Each of the corresponding registers may be configured to store a segment address, and in response to detecting that each segment of a particular row has been targeted as at least one access operation, the corresponding cold data detector of the plurality of cold data detectors is configured to provide the address of the corresponding longest stored segment from the corresponding register to a cold data readout circuit. The cold data readout circuitry may provide an indication to transfer cold data from the first memory to the second memory in response to receiving the address of the corresponding longest stored segment from each of the plurality of cold data detectors. Alternatively or additionally, the depth of the corresponding register of one of the plurality of cold data detectors is less than the count of the corresponding plurality of segments in the rows of the plurality of rows corresponding to said one of the plurality of cold data detectors. Alternatively, the cold data readout circuitry includes a shift register having multiple time slots, each configured to store the address of a corresponding longest stored segment from a specific one of a plurality of cold data detectors. Alternatively, the first memory and the second memory are part of a memory module or a system-on-a-chip. Alternatively, the first memory is non-volatile memory, and the second memory is volatile memory.

[0007] An example method is described herein. One example method includes storing a segment address in a register of a cold data detector circuit during an access operation associated with a row of segments of a memory cell array. Each segment address may be associated with a corresponding segment among the multiple segments. The example method further includes, in response to detecting that each of the multiple segments of the row has been accessed, transmitting the address of the longest stored segment to a cold data readout circuit as a cold address. Alternatively, the method further includes, during an access operation associated with a target segment among the multiple segments, shifting each of the multiple time slots preceding a specific time slot indicating emptiness in the register by one time slot to fill the specific time slot, such that a first end time slot among the multiple time slots is available to receive the corresponding target segment address associated with the target segment. Alternatively, the method further includes, during an access operation associated with a target segment among the multiple segments, comparing the corresponding segment address stored in the register with the corresponding target segment address; and, in response to determining that one of the corresponding segment addresses stored in the register matches the corresponding target segment address, invalidating one of the corresponding segment addresses stored in the register and storing the corresponding target segment address in the register. Alternatively, the method further includes, in response to detecting that each of the plurality of segments in the row has been accessed, providing the address of the corresponding segment stored in the last time slot of the register as the address of the longest stored segment. Alternatively, the method further includes, in response to receiving the address of the longest stored segment from each of the plurality of registers corresponding to the plurality of rows of memory cell arrays, initiating the transfer of cold data from the memory cell array to another memory. Alternatively, the memory cell array comprises non-volatile memory cells, and the other memory comprises non-volatile memory. Attached Figure Description

[0008] Figure 1 This is a block diagram of a memory system according to an embodiment of the present disclosure.

[0009] Figure 2 This is a schematic block diagram of a semiconductor device memory system according to embodiments of the present disclosure.

[0010] Figure 3 This is a block diagram of the logic circuit of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 4 This is a schematic block diagram of a bubble break register circuit of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 5An exemplary timing diagram includes write accesses associated with a bubble burst register according to embodiments of this disclosure.

[0013] Figure 6 This is a block diagram of a cold data readout circuit according to an embodiment of the present disclosure.

[0014] Figure 7 This is a block diagram of a system-on-a-chip memory system according to an embodiment of the present disclosure. Detailed Implementation

[0015] This disclosure describes examples of systems for detecting cold data in a memory system comprising main memory (e.g., volatile memory, such as dynamic random access memory (DRAM)) and secondary memory (e.g., non-volatile memory, such as flash memory). In some memory systems, main memory may be initially used to store data due to its lower latency. When main memory is full of data, some of the stored data may be transferred to secondary memory for long-term storage. Secondary memory may have a longer access latency than main memory. One consideration in transferring data to secondary memory is the selection of the data to be transferred. That is, to mitigate the efficiency loss of transferring data to secondary memory, it is necessary to predict which data is most likely to be requested for additional processing (e.g., hot data) and which data is most likely not to experience an impending request for further processing (e.g., cold data). In one example, hot data may contain new and / or frequently accessed data, and cold data may contain older, less frequently accessed data. Another consideration in transferring data from main memory to secondary memory is ensuring that main memory is sufficiently filled with data points so that more space needs to be reserved for future processing.

[0016] In some instances addressing one or both of these considerations, the cold data detector described herein may include a bubble burst register or buffer architecture configured to capture and store access information indicating which segments or sections of main memory are currently storing cold data (e.g., older data). By its very nature, the bubble burst register architecture may be able to indicate both when a transfer should begin and which segment of main memory contains the cold data.

[0017] The bubble burst register architecture may include a shift register form, but can be fully utilized by selectively shifting received data to fill empty time slots without waiting for the empty time slots to be shifted out of the end time slot. The bubble burst register may include flag circuitry containing a corresponding flag for each time slot in the register. Each corresponding flag can be configured to indicate whether a particular time slot in the register currently holds a valid fragment address. Thus, for a particular time slot, the corresponding flag indicates whether the fragment address stored in the corresponding address circuitry is valid. When the corresponding flag for a particular time slot indicates that the fragment address is invalid (e.g., an empty time slot or bubble in the register), shifting a new fragment address into the register can cause an empty time slot to be filled by shifting the existing fragment address from the previous time slot by one time slot, making the first end time slot available to shift the new fragment address in, while subsequent time slots storing valid fragment addresses remain unaffected.

[0018] For example, a register can contain four fragment address slots, where all slots except the third slot hold valid fragment addresses. When a new fragment address is received, the fragment address from the second slot can be shifted to fill the empty third slot, the fragment address from the first slot can be shifted to replace the data in the second slot, and the new fragment address can be shifted into the first slot. In this example, the fourth slot remains unaffected by the shifts.

[0019] In some instances, a burst bubble register can be used to store a finite subset of fragment addresses in a semiconductor device. When a new fragment address matching a previously stored fragment address is received, the previously stored fragment address can be invalidated (e.g., by setting or clearing the corresponding flag), and the new fragment address can be shifted into the register. Invalidating a previously stored fragment address can cause it to be overwritten. In some instances, the size of the burst bubble register (e.g., the number of time slots) can be based on the number of segments in main memory. Thus, the register may be able to store the corresponding fragment address for each segment of main memory simultaneously. As each time slot of the register is filled, each flag can indicate that each time slot has a valid fragment address.

[0020] The control circuitry may be coupled to the bubble burst register and may cause the bubble burst register to provide cold address data at its output in response to detecting at least one access to each segment in the group. The control circuitry may include corresponding latching circuitry for each segment in the group, wherein each individual latch is set in response to receiving activation of the corresponding segment address.

[0021] Cold address data for a row of memory can be provided to and stored at a cold data readout circuit with a shift register. The shift register may contain time slots for each row of memory, and in response to each time slot being filled, logic circuitry can cause the shift register to initiate the transfer of the contents of data stored in a segment of memory to an auxiliary storage device, the segment corresponding to a segment address stored in the shift register. The shift register and / or bubble burst register control circuitry can be reset to begin detecting when the memory is full.

[0022] Certain details are set forth below to provide a full understanding of embodiments of this disclosure. However, those skilled in the art will understand that embodiments of this disclosure can be practiced without these specific details. Furthermore, the specific embodiments of this disclosure described herein are provided by way of example and should not be construed as limiting the scope of this disclosure to these specific embodiments. In other examples, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail to avoid unnecessarily obscuring this disclosure.

[0023] Figure 1 This is a block diagram of a memory system 100 according to an embodiment of the present disclosure. The memory system 100 may include a memory module 110 having a secondary memory 120 and a primary memory 130, and a module controller 140 configured to maintain visual memory pages to manage data storage locations between the secondary memory 120 and the primary memory 130 in order to route access requests to the correct memory. In some instances, the primary memory 130 may include volatile memory, and the secondary memory 120 may include non-volatile memory. The memory system 100 may be contained in a device, a memory module, a system-on-a-chip (SoC), or any other type of architecture configured to implement a memory system.

[0024] The memory system 100 can be configured to receive commands (CMD), addresses (ADD), and data from a host or memory controller (not shown) to perform access operations (e.g., read, write, etc.) to maintain data on the memory system 100. The auxiliary memory 120 may contain flash memory or another type of NVM, and the primary memory 130 may contain any type of DRAM, including dual data rate (DDR) 3, DDR4, DDR5, low-power DDR, graphics DDR, etc.

[0025] In some instances, when operating in a computing system, primary memory 130 may be configured as primary memory, configured to temporarily store data generated and consumed during processing tasks, and secondary memory 120 may be configured as secondary memory to provide supplemental and / or permanent storage in the event that primary memory 130 is full of stored data or in the event of a failure. In this example, primary memory 130 may be used to initially store data compared to secondary memory 120 due to its lower access latency, and when primary memory 130 is full of data, primary memory 130 may transfer some of the stored data directly or via module controller 140 to secondary memory 120 for long-term storage.

[0026] The primary memory 130 may include a cold data detector and readout circuitry configured to trigger a transfer of data to the secondary memory 120 based on a determination that the primary memory 130 is sufficiently full, thus freeing up more available space. At least two considerations for transferring data to the secondary memory 120 may include determining when to transfer data and determining which data to transfer. In some instances, the cold data detector and readout circuitry may also specify which data to transfer to the secondary memory 120. Selecting which data to transfer may involve identifying which data is likely to be accessed for further processing and which data is unlikely to be accessed for further processing. That is, to mitigate the efficiency loss caused by the increased access latency of the secondary memory 120, it may be necessary to predict which data is hot data (e.g., data most likely to be requested for additional processing) and which data is cold data (e.g., data most likely not to experience an upcoming request for further processing). In one instance, hot data may be new and / or frequently accessed data within the primary memory 130, and cold data may include older, less frequently accessed data.

[0027] The determination of when to transfer data from the main memory 130 to the auxiliary memory 120 can be based on the cold data detector and the readout circuitry's determination of when the main memory 130 is sufficiently filled with stored data (e.g., a threshold has been reached), making it necessary to reserve more memory space to accommodate future data storage.

[0028] In some instances addressing one or both of these considerations, the cold data detector and readout circuitry may include a bubble-bursting register or buffer architecture configured to capture and store access information indicating which segments or sections of a main memory bank are currently storing cold data (e.g., older data). By its very nature, the bubble-bursting register architecture may be able to indicate which segment of main memory contains cold data in response to control circuitry determining that each segment of the bank has been accessed at least once.

[0029] The bubble burst register of the cold data detector circuit may be in the form of a shift register, but the register can be fully utilized by selectively shifting received data to fill empty time slots without waiting for the empty time slots to be shifted out of the end time slot. The bubble burst register may include flag circuitry containing a corresponding flag for each time slot in the register. Each corresponding flag can be configured to indicate whether a particular time slot in the register currently holds a valid fragment address. Thus, for a particular time slot, the corresponding flag indicates whether the fragment address stored in the corresponding address circuitry is valid. When the corresponding flag for a particular time slot indicates that the fragment address is invalid (e.g., an empty time slot or bubble in the register), shifting a new fragment address into the register can cause an empty time slot to be filled by shifting the existing fragment address from the previous time slot by one time slot, making the first end time slot available to shift the new fragment address in, while subsequent time slots storing valid fragment addresses remain unaffected.

[0030] For example, a register can contain four fragment address slots, where all slots except the third slot hold valid fragment addresses. When a new fragment address is received, the fragment address from the second slot can be shifted to fill the empty third slot, the fragment address from the first slot can be shifted to replace the data in the second slot, and the new fragment address can be shifted into the first slot. In this example, the fourth slot remains unaffected by the shifts.

[0031] In some instances, the bubble burst register of a cold data detector circuit can be used to store a finite subset of segment addresses for rows of memory arrays used in a semiconductor device. When a new segment address matching a previously stored segment address is received, the previously stored segment address can be invalidated (e.g., by setting or clearing the corresponding flag), and the new segment address can be shifted into the register. Invalidating a previously stored segment address can cause it to be overwritten. In some instances, the size of the bubble burst register (e.g., the number of time slots) can be based on the number of segments in main memory.

[0032] As each time slot of the register is filled, each flag can indicate that each time slot has a valid segment address. Control circuitry can be coupled to the bubble burst register and can cause the bubble burst register to provide cold address data at its output in response to detecting at least one access to each segment in the group. The control circuitry may include corresponding latching circuitry for each segment in the group, logic gates for detecting when each latch is set, and a pulse generator for causing the bubble burst register to provide cold address data from the bubble burst register. Each individual latch can be set in response to receiving activation of the corresponding segment address. In some instances, the coldest data can be determined based on the segment address stored in the last time slot of the bubble burst register.

[0033] Cold address data output from the bubble burst register for each row group can be provided to and stored in a shift register of the cold data detector and readout circuitry. The shift register may contain time slots for each row group in the main memory 130, and in response to each time slot being filled, the logic circuitry of the cold data detector and readout circuitry can cause the shift register to initiate the transfer of the contents of data stored in a segment of the main memory 130 to the auxiliary memory 120, the segment corresponding to the segment address stored in the shift register. The shift register and / or bubble burst register control circuitry can be reset to begin detecting when the memory is full.

[0034] Using a bubble burst register architecture in the cold data detector circuit of the main memory 130 to determine when to trigger the transfer of data from the main memory 130 to the auxiliary memory 120, and to determine which data to transfer, provides a more efficient mechanism for managing storage at the main memory 130 compared to counters and other conventional circuit systems implemented for this purpose.

[0035] Figure 2 This is a schematic block diagram of a semiconductor device 200 according to an embodiment of the present disclosure. For example, the semiconductor device 200 may include a chip 235. Chip 235 may include a clock input circuit 205, an internal clock generator 207, an address command input circuit 215, an address decoder 220, a command decoder 225, a control circuit 221, a cold data detector circuit 222, multiple row decoders 230, a memory cell array 245 including a sense amplifier 250 and a transmission gate 295, multiple column decoders 240, multiple read / write amplifiers 265, an input / output (I / O) circuit 270, a cold data readout circuit 271, and a voltage generator circuit 290. The semiconductor device 200 may include multiple external terminals, including address and command terminals coupled to a command / address bus 210, clock terminals CK and / or CK, data terminals DQ, DQS, and DM, and power supply terminals VDD, VSS, VDDQ, and VSSQ. Chip 235 can be mounted on a substrate, such as a memory module substrate, motherboard, etc.

[0036] The memory cell array 245 comprises multiple rows BANK0-N, each row BANK0-N containing multiple word lines WL, multiple bit lines BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL. The rows BANK0-N may contain 2, 4, 8, 16, or any other number of rows. Each of the rows BANK0-N may be divided into two or more memory planes (e.g., column planes), which may be selected by a column selection CS signal from column decoder 240. In some instances, each of the rows BANK0-N may contain 2, 4, 8, 16, 32, etc., column planes. The selection of the word lines WL for each row is performed by the corresponding row decoder 230, and the selection of the bit lines BL is performed by the corresponding column decoder 240. Multiple sense amplifiers 250 are positioned for their corresponding bit lines BL and coupled to at least one corresponding local I / O line, which is further coupled to one of at least two main I / O line pairs via a transmission gate TG 295, which acts as a switch.

[0037] Address / command input circuit 215 can receive address signals and row / group address signals from outside the command / address terminal via command / address bus 210, and transmit the address signals and row / group address signals to address decoder 220. Address decoder 220 can decode the address signals received from address / command input circuit 215 and provide row address signal XADD to row decoder 230 and column address signal YADD to column decoder 240. Address decoder 220 can also receive row / group address signals and provide row / group address signal BADD to row decoder 230 and column decoder 240.

[0038] Address / command input circuitry 215 can receive command signals from external sources, such as a memory controller at the command / address terminal, via command / address bus 210, and provide the command signals to command decoder 225. Command decoder 225 can decode the command signals and provide and / or generate various internal command signals. For example, internal command signals may include row command signals for selecting word lines, column command signals for selecting bit lines, such as read or write commands, and / or low-latency enable bits for enabling the use of control circuitry 221 and / or cold data detector circuitry 222.

[0039] When a read command is issued and ACT and RW commands are supplied to the row and column addresses as appropriate, read data is read from the memory cells specified by the row and column addresses in the memory cell array 245. The read / write amplifier 265 receives the read data DQ and provides it to the I / O circuit 270. The I / O circuit 270 provides the read data DQ, along with a data strobe signal at DQS and / or a data mask signal at DM, to the external location via the data terminal DQ. Similarly, when a write command is issued and ACT and R / W commands are supplied to the row and column addresses as appropriate, the input / output circuit 270 receives the write data at the data terminal DQ, along with a data strobe signal at DQS and / or a data mask signal at DM, and provides the write data to the memory cell array 245 via the read / write amplifier 265. Therefore, write data can be written to the memory cells specified by the row and column addresses.

[0040] In some instances, when operating in a computing system, semiconductor device 200 may be configured as main memory, which is configured to temporarily store data generated and consumed during processing tasks. Semiconductor device 200 may be able to transfer data to auxiliary memory (not shown) (e.g., Figure 1 The auxiliary memory 120 can be configured to provide auxiliary and / or permanent storage in the event that the semiconductor device 200 is full of stored data or a failure occurs. In this example, the semiconductor device 200 can be used to initially store data compared to the auxiliary memory due to its lower access latency, and when the semiconductor device 200 is full of data, the semiconductor device 200 can transfer some of the stored data to the auxiliary memory for long-term storage.

[0041] Control circuitry 221, cold data detector circuitry 222, and cold data readout circuitry 271 can be configured to trigger data transfer to auxiliary memory based on determining that memory cell array 245 is sufficiently full, thus freeing up more available space. At least two considerations for transferring data to auxiliary memory may include determining when to transfer data and determining which data to transfer. In some instances, control circuitry 221 and cold data detector circuitry 222 may also specify which data to transfer to auxiliary memory. Selecting which data to transfer may involve identifying which data is likely to be accessed for further processing and which data is unlikely to be accessed for further processing. That is, to mitigate the efficiency loss caused by increased access latency to auxiliary memory, it may be necessary to predict which data is hot data and which data is cold data. In one instance, hot data may be new and / or frequently accessed data within memory cell array 245, and cold data may include older, less frequently accessed data.

[0042] The determination of when to transfer data from semiconductor device 200 to auxiliary memory can be based on the determination by control circuit 221 and cold data detector circuit 222 of when memory cell array 245 is sufficiently filled with stored data (e.g., a threshold has been reached), making it necessary to reserve more memory space to accommodate future data storage.

[0043] In some instances addressing one or both of these considerations, the cold data detector circuit 222 may include a bubble burst register or buffer architecture configured to capture and store access information indicating which segments or sections of a specific row within memory rows BANK0-N of the memory cell array 245 are currently storing cold data (e.g., older data). In some instances, the cold data detector circuit 222 may be configured to determine when the segment address of the corresponding row within memory rows BANK0-N of the memory cell array 245 should be provided to the cold data readout circuit 271, and which segment address of the corresponding row within memory rows BANK0-N of the memory cell array 245 contains cold data.

[0044] The bubble burst register of the cold data detector circuit 222 may be in the form of a shift register, but the register can be fully utilized by selectively shifting received data to fill empty time slots without waiting for the empty time slots to be shifted out of the end time slot. The cold data detector circuit 222 may be configured to receive a segment address SEG ADD and an LCLK signal, and may be configured to shift the SEG ADD into the bubble burst register in response to the LCLK signal. In response to each time slot in the bubble burst register being filled with a valid SEG ADD, the cold data detector circuit 222 may set the cold data signal COLD DATA to indicate that the bubble burst register is full. In response to the COLD DATA signal, the control circuit 221 may initiate the transfer of data from the memory cell array 245 to the auxiliary memory. In some instances, during access operations, the control circuit 221 may also set a mode register segment parameter to indicate which specific segment has been accessed based on the SEG ADD provided to the cold data detector circuit 222. In some instances, the COLD DATA signal can also indicate a segment address, which indicates the segment from which data should be transmitted. The segment address can be the address of the last time slot (e.g., the time slot with the oldest data) stored in the bubble burst register.

[0045] The bubble burst register of the cold data detector circuit 222 may include flag circuitry containing a corresponding flag for each time slot in the register. Each corresponding flag may be configured to indicate whether a specific time slot in the register currently holds a valid fragment address. Thus, for a specific time slot, the corresponding flag indicates whether the fragment address stored in the corresponding address circuitry is valid. When the corresponding flag for a specific time slot indicates that the fragment address is invalid (e.g., an empty time slot or bubble in the register), shifting a new fragment address into the register can cause an empty time slot to be filled by shifting an existing fragment address from a previous time slot by one time slot, making the first end time slot available to shift the new fragment address in, while subsequent time slots storing valid fragment addresses remain unaffected.

[0046] For example, in an implementation where the bubble burst register of the cold data detector circuit 222 contains four fragment address slots, all slots except the third slot retain valid fragment addresses. When a new fragment address SEG ADD is received, the fragment address from the second slot can be shifted to fill the empty third slot, the fragment address from the first slot can be shifted to replace the data in the second slot, and the new fragment address can be shifted into the first slot. In this example, the fourth slot remains unaffected by the shift.

[0047] In some instances, each of the memory rows BANK0-N of the semiconductor device 200 may be divided into multiple segments. Therefore, in some instances, the cold data detector circuit 222 may include a bubble-bursting register for each of the memory rows BANK0-N and the cold data detector circuit 222 itself. In instances with bubble-bursting registers for each memory row BANK0-N, the segment address may indicate the specific memory row targeted during a read or write access (e.g., it may include the row address BADD). In one instance, the cold data detector circuit 222 may be configured to provide a cold data segment address to the cold data readout circuit 271 in response to access to each segment within a specific memory row BANK0-N.

[0048] In some instances, the bubble burst register of the cold data detector circuit 222 can be used to store a finite subset of segment addresses for a specific memory bank BANK0-N in the semiconductor device 200. When a new segment address matching a previously stored segment address is received, the previously stored segment address can be invalidated (e.g., by setting or clearing the corresponding flag), and the new segment address can be shifted into the register. Invalidating a previously stored segment address can cause the previously stored segment address to be overwritten. In some instances, the size of the bubble burst register (e.g., the number of time slots) can be based on the number of segments in the main memory. Thus, the register may be able to store the corresponding segment address for each segment of the memory cell array 245 simultaneously.

[0049] As each time slot of the register is filled, each flag can indicate that each time slot has a valid segment address. Control circuitry can cause the bubble burst register to provide a cold address at its output in response to detecting at least one access to each segment in the group. The control circuitry may include corresponding latching circuitry for each segment in the group, logic gates for detecting when each latch is set, and a pulse generator for causing the bubble burst register to provide a cold address from the bubble burst register. Each individual latch can be set in response to receiving activation of the corresponding segment address. Determining from which segment data is transferred can be based on which segment address has the oldest (e.g., coldest) data. In some instances, the coldest data can be determined based on the segment address stored in the last time slot of the register.

[0050] The cold addresses BK0-N, output from the bubble burst register of the cold data detector circuit 222 for memory rows BANK0-N, can be provided to and stored in the shift register of the cold data readout circuit 271. The shift register may contain time slots for each row of memory rows BANK0-N in the memory cell array 245, and in response to each time slot being filled, the shift register can provide a fill signal. In response to the fill signal, the control circuit 221 can cause the cold data readout circuit 271 to provide a segment of data from the memory cell array 245 to the output data terminal DQ, the segment corresponding to the segment address stored in the shift register. In response to cold data being read from the memory cell array 245, the cold data detector circuit 222 and the cold data readout circuit 271 can be reset to begin detecting when the memory cell array is full.

[0051] Compared to counters and other conventional circuit systems implemented for this purpose, using the bubble burst register architecture in the cold data detector circuit 222 to help determine when to trigger the transmission of data from the semiconductor device 200, and to help determine which data to transmit, provides a more efficient mechanism for managing the storage at the semiconductor device 200.

[0052] Turning to the explanation of the external terminals included in semiconductor device 200, clock terminals CK and / CK can receive an external clock signal and a complementary external clock signal, respectively. The external clock signal (including the complementary external clock signal) can be supplied to clock input circuit 205. Clock input circuit 205 can receive the external clock signal and generate an internal clock signal ICLK. Clock input circuit 205 can provide the internal clock signal ICLK to internal clock generator 207. Internal clock generator 207 can generate a phase-controlled internal clock signal LCLK based on the received internal clock signal ICLK and a clock enable signal CKE from address / command input circuit 215. While not limited to this, a DLL circuit can be used as internal clock generator 207. Internal clock generator 207 can provide the phase-controlled internal clock signal LCLK to IO circuit 270. IO circuit 270 can use the phase-controlled internal clock signal LCLK as a timing signal to determine the output timing for reading data.

[0053] The power supply terminals can receive power supply voltages VDD and VSS. These power supply voltages VDD and VSS can be supplied to voltage generator circuit 290. Voltage generator circuit 290 can generate various internal voltages VPP, VOD, VARY, VPERI, etc., based on the power supply voltages VDD and VSS. The internal voltage VPP is mainly used in the line decoder 230, the internal voltages VOD and VARY are mainly used in the sense amplifier 250 contained in the memory cell array 245, and the internal voltage VPERI is used in many other circuit blocks. The power supply terminals can also receive power supply voltages VDDQ and VSSQ. I / O circuit 270 can receive power supply voltages VDDQ and VSSQ. For example, power supply voltages VDDQ and VSSQ can be the same voltages as power supply voltages VDD and VSS, respectively. However, dedicated power supply voltages VDDQ and VSSQ can be used in I / O circuit 270.

[0054] Figure 3 This is a block diagram of a cold data detection circuit 300 of a semiconductor device according to an embodiment of the present disclosure. The cold data detection circuit 300 includes BANK0-N cold data detectors 310(0)-(N) coupled to a cold data readout circuit 311. In some instances, Figure 1 The main memory 130 cold data detector circuit and / or Figure 2 The cold data detector circuit 222 can implement a BANK0-N cold data detector 310(0)-(N), and Figure 2 The cold data readout circuit 271 can implement the cold data readout circuit 311.

[0055] Each of the BANK0-N cold data detectors 310(0)-(N) may include: a control circuit configured to receive the corresponding segment activation signal ACTSEG0-N<k:0>and the RESET signal; and the bubble burst register, which is configured to receive the clock signal LCLK and the fragment address SEG ADD. <x>。ACTSEG0-N <k:0>Signals and SEG ADD <n:0>It can indicate that a segment of the corresponding group is being accessed.

[0056] The bubble burst register of each of the BANK0-N cold data detectors 310(0)-(N) may contain a shift register, but the register can be fully utilized by selectively shifting the received data to fill empty time slots without having to wait for the empty time slots to be shifted out of the end time slot.

[0057] The control circuitry of a specific one of the BANK0-N cold data detectors 310(0)-(N) enables the corresponding bubble burst register to provide a BK0-N cold address and a corresponding fill-the-batch signal FULLBKF at the output in response to detecting at least one access to each segment in the memory bus. <n:0>The control circuitry may include corresponding latching circuitry for each segment in the group, logic gates for detecting when each latch is set, and a pulse generator for providing a cold address from the bubble burst register to the bubble burst register. Each individual latch may respond via corresponding ACTSEG0-N <k:0>The signal is received and activated at the corresponding segment address, thus setting the latch. In response to each latch being set, the control circuit can trigger the corresponding BK0-N cold address and the fill signal FULLBKF. <n:0>The signal is supplied to the cold data readout circuit 311.

[0058] Each of the bubble burst registers in the BANK0-N cold data detectors 310(0)-(N) may include flag circuitry containing a corresponding flag for each time slot in the register. Each corresponding flag may be configured to indicate whether a particular time slot in the register currently holds a valid fragment address. Thus, for a particular time slot, the corresponding flag indicates whether the fragment address stored in the corresponding address circuitry is valid. When the corresponding flag for a particular time slot indicates that the fragment address is invalid (e.g., an empty time slot or bubble in the register), shifting a new fragment address into the register can cause an empty time slot to be filled by shifting an existing fragment address from a previous time slot by one time slot, making the first end time slot available to shift the new fragment address in, while subsequent time slots storing valid fragment addresses remain unaffected.

[0059] For example, in an implementation where the bubble burst register of each of the BANK0-N cold data detectors 310(0)-(N) contains four fragment address slots, all slots except the third slot retain valid fragment addresses. When a new fragment address SEG ADD is received, the fragment address from the second slot can be shifted to fill the empty third slot, the fragment address from the first slot can be shifted to replace the data in the second slot, and the new fragment address can be shifted into the first slot. In this example, the fourth slot remains unaffected by the shift.

[0060] When the control circuitry of one of the BANK0-N cold data detectors 310(0)-(N) detects that each segment has been accessed at least once, the control circuitry may cause the bubble burst register to shift the segment address to the output of the last time slot of the bubble burst register until a valid segment address has been provided as the BK0-N cold address.

[0061] The BK0-N cold address output from the bubble burst register of the BANK0-N cold data detectors 310(0)-(N) can be provided to and stored in the shift register of the cold data readout circuit 311. The shift register may contain time slots for each of the N memory rows of the memory cell array and is responsive to FULLNKF. <n:0>Each of the signals indicates that the corresponding memory bank BANK0-N is filled, and the shift register can generate a fill signal. In response to the fill signal, the cold data read circuit 311 provides data corresponding to the cold addresses BK0-N received from the cold data detectors 310(0)-(N). In response to the cold data being read from the memory cell array, a reset signal received at the cold data detectors 310(0)-(N) can be set to reset the cold data detectors 310(0)-(N) and begin detecting whether the corresponding memory bank is filled.

[0062] In operation, the bubble burst register of each of the BANK0-N cold data detectors 310(0)-(N) can be used to store a finite subset of segment addresses for memory rows of a memory cell array for a semiconductor device. When a new segment address matching a previously stored segment address is received, the previously stored segment address may be invalidated (e.g., by setting or clearing the corresponding flag), and the new segment address may be shifted into the register. Invalidating a previously stored segment address can cause the previously stored segment address to be overwritten. In some instances, the size of the bubble burst register (e.g., the number of time slots) may be based on the number of segments in main memory. Thus, the register may be able to store the corresponding segment address for each segment of main memory simultaneously. As each time slot of the bubble burst register of one of the BANK0-N cold data detectors 310(0)-(N) is filled, each flag may indicate that each time slot has a valid segment address.

[0063] When the control circuitry of one of the BANK0-N cold data detectors 310(0)-(N) detects that each segment has been accessed at least once, the control circuitry may cause the bubble burst register to shift the segment address to the output of the last time slot of the bubble burst register until a valid segment address has been provided as a BK0-N cold address. In some instances, the coldest data may be determined based on the segment address stored in the last time slot of the bubble burst register.

[0064] When the cold data readout circuit 311 has received the BK0-N cold address and FULLBKF from each of the BANK0-N cold data detectors 310(0)-(N) <n:0>When a signal is received, the cold data readout circuit 311 can provide an indication that the memory is full and can initiate the transfer of data from memory bus segments corresponding to cold addresses BK0-N stored in a shift register. In response to data being transferred from the memory array, a reset signal received at cold data detectors 310(0)-(N) can be set to reset cold data detectors 310(0)-(N) and begin detecting whether the corresponding memory bus is full.

[0065] Compared to counters and other conventional circuit systems implemented for this purpose, using the bubble burst register architecture in the BANK0-N cold data detector 310(0)-(N) to determine when to trigger the transfer of data from the corresponding memory cell array and to determine which data to transfer provides a more efficient mechanism for managing storage at the memory cell array.

[0066] Figure 4 This is a schematic block diagram of a cold data detector 400 of a semiconductor device according to an embodiment of the present disclosure. The cold data detector 400 includes control circuitry 402 and a bubble bursting register having input circuitry 410; flag path circuitry 430, address matching logic circuitry 440, and address path circuitry 450. In some instances, Figure 1 Any one of the cold data detector circuits 132 Figure 2 The cold data detector circuit 222 and / or Figure 3 Any one of the BANK0-N cold data detectors 310(0)-(N) can implement a cold data detector 400.

[0067] The control circuit 402 may include a set of latch circuits 404(0)-(K), an AND gate 406, an inverter 405, and a pulse generator 408, each corresponding to a segment in the K+1 segments of the memory array. Each of the latch circuits 404(0)-(K) may be configured to receive a corresponding segment activation signal ACTSEG. <k:0>and reset signal. The output of each of the latch circuits 404(0)-(K) can be provided to the AND gate 406. Each individual latch can respond to the corresponding ACSTEG0-N <k:0>The signal is activated upon receiving the corresponding segment address and is set. In response to each of the latch circuits 404(0)-(K) being set, the AND gate 406 can fill the signal FULLBK. <x>Provided to pulse generator 408 and inverter 405, the inverter will FULLBKF <x>A signal is provided to the output to initiate the output of the cold address from the address path circuit 450 in response to the READOUTBx clock signal provided to 453. The pulse generator 408 can use FLG. <3> The signal determines when a valid cold address has been output from address path circuit 450. That is, if the bubble burst register is not filled, the first valid data can be stored in address flip-flops other than address flip-flop 3452(3). Therefore, pulse generator 408 can pulse the READOUTBx clock signal until a valid cold address is output from address flip-flop 3452(3), and can stop providing pulses on the READOUTBx clock signal after the cold address has been output. The RESET signal can reset latch circuits 404(0)-(K) after data has been transferred from the memory array. In response to each of latch circuits 404(0)-(K) being set, AND gate 406 can also FULLBK <x>Provided to inverter 405, the inverter inverts FULLBK <x>The signal is used to provide FULLBKF at the output. <x>Signal.

[0068] Input circuitry 410 may include NAND gate 411 coupled to an AND gate formed by NAND gate 412 and inverter 413. NAND gate 411 is configured to receive flag bits FLG<3:0> from flag path circuitry 430, each indicating whether a specific time slot of the cold data detector 400 holds valid data, and is configured to apply NAND logic to provide an output to NAND gate 412 (e.g., the output of NAND gate 411 is set to a low logic value when all FLG<3:0> bits are set; otherwise, it is set to a high logic value). In addition to the output of NAND gate 411, NAND gate 412 is also configured to receive a clock signal CLK. Based on the output of NAND gate 411 and the CLK signal, NAND gate 412 is configured to provide an output to inverter 413, which inverts the output to provide a write clock signal CLKW to flag path circuitry 430 and address path circuitry 450.

[0069] Flag path circuit 430 includes a set of flag flip-flops 432(0)-(3), and address path circuit 450 includes a set of corresponding address flip-flops 452(0)-(3). In addition to the set of flag flip-flops 432(0)-(3), flag path circuit 430 further includes an inverter 434, a set of NAND gates 435(1)-(2), and a set of selector circuits SEL 436(0)-(2). Each of the set of flag flip-flops 432(1)-(3) is configured to receive, via selector circuit SEL 436(0)-(2), the output of the previous one of the set of flag flip-flops 432(0)-(2) or the output of the corresponding flag flip-flop 432(1)-(3), wherein flag flip-flop 432(0) is configured to receive a high-level active flag signal FLGX and may provide a corresponding FLG<3:0> signal at the output. Each of the flag triggers 432(0)-(3) can respond to the CLKW signal and convert the corresponding input signal into the corresponding FLG<3:0> signal at the output.

[0070] Inverter 434 can be configured to receive FLG. <0> The signal can be configured to invert the FLG signal. <0> Signal to FLGPSS <0> The signal is provided to the selector circuit SEL 436(0). The selector circuit SEL 436(0) can be configured based on FLGPSS. <0> The value of the signal will affect FLG <0> Signals (e.g., when FLGPSS) <0> (When the signal has a first value) or FLG <1> Signals (e.g., when FLGPSS) <0> When the signal has a second value, it is selectively provided to the input of the flag trigger 432(1).

[0071] NAND gate 435(1) can be configured to receive FLG <1> Signals and FLG <0> Signals, and can be configured to be based on FLG <1> Signals and FLG <0> The signal is then processed using NAND logic to convert FLGPSS <1> The signal is provided to the selector circuit SEL 436(1) and the NAND gate 435(2). The selector circuit SEL 436(1) can be configured based on FLGPSS. <1> The value of the signal will affect FLG <1> Signals (e.g., when FLGPSS) <1> (When the signal has a first value) or FLG <2> Signals (e.g., when FLGPSS) <1> When the signal has a second value, it is selectively provided to the input of the flag trigger 432(2).

[0072] The NAND gate 435(2) can be configured to receive FLGPSS active low (via inverter). <1> Signals and FLG <2> The signal can be configured to be active low (FLGPSS). <1> Signals and FLG <2> The signal is applied using NAND logic to convert FLGPSS <2> The signal is provided to the selector circuit SEL 436(2). The selector circuit SEL 436(2) can be configured to be based on FLGPSS. <2> The value of the signal will affect FLG <2> Signals (e.g., when FLGPSS) <2> (When the signal has a first value) or FLG <3> Signals (e.g., when FLGPSS) <2> When the signal has a second value, it is selectively provided to the input of the flag trigger 432(3).

[0073] The address matching logic circuit 440 of the cold data detector 400 includes a set of XNOR gates 442(0)-(3), a set of AND gates 444(0)-(3), and a set of delay circuits 446(0)-(4). Each of the XNOR gates 442(0)-(3) is configured to compare the received address bit ADDX with the output address bit ADD<3:0> from the corresponding one of the address flip-flops 452(0)-(3) (e.g., using exclusive NOR logic), and provide the result of the comparison to the corresponding one of the AND gates 444(0)-(3). Each of the AND gates 444(0)-(3) is configured to apply AND logic to compare the output of the corresponding one of the XNOR gates 442(0)-(3) with the corresponding FLG<3:0> signal to provide the corresponding read enable signals RDEN0-RDEN3. Therefore, each of the RDEN0-RDEN3 signals indicates that the corresponding ADD<3:0> bit is valid and matches the received ADDX bit. Each of the RDEN0-RDEN3 signals can be passed through the corresponding one of the delay circuits 446(0)-(3) to reset the corresponding one of the set of flag triggers 432(0)-(3).

[0074] The first address flip-flop 452(0) can be configured to receive a new address ADDX. In addition to the set of address flip-flops 452(0)-(3), the address path circuit 450 further includes a set of selector circuits 454(0)-(2). Each of the selector circuits 454(0)-(2) can be configured to selectively provide either the corresponding ADD<2:0> address from the output of the address flip-flops 452(0)-(2) or the corresponding address ADD<3:1> from the output of the address flip-flops 452(1)-(3) to the input of the corresponding one of the address flip-flops 452(1)-(3) in response to the corresponding FLGPSS<3:0> signal. The selector circuit SEL 452(0) can be configured based on FLGPSS... <0> The value of the signal will cause ADD <0> Signals (e.g., when FLGPSS) <0> (When the signal has a first value) or ADD <1> Signals (e.g., when FLGPSS) <0> When the signal has a second value, it is selectively provided to the input of the address flip-flop 452(1). The selector circuit SEL 452(1) can be configured based on FLGPSS. <1> The value of the signal will cause ADD <1> Signals (e.g., when FLGPSS) <1> (When the signal has a first value) or ADD <2> Signals (e.g., when FLGPSS) <1> When the signal has a second value, it is selectively provided to the input of the address flip-flop 452(2). The selector circuit SEL 452(2) can be configured based on FLGPSS. <2> The value of the signal will cause ADD <2> Signals (e.g., when FLGPSS) <2> (When the signal has a first value) or ADD <3> Signals (e.g., when FLGPSS) <2> When the signal has a second value, it is selectively provided to the input of the address flip-flop 452 (3). The selector circuits SEL452 (0)-(2) can each be configured to receive the corresponding FLGPSS<2:0> signal and the corresponding active-low FLGPSS<2:0> signal via the corresponding inverter 455 (0)-(2).

[0075] Each address flip-flop 452(0)-(3) can provide a corresponding ADD<3:0> address at the output based on the received input address. Each of the address flip-flops 452(0)-(3) can convert the corresponding input signal into the corresponding ADD<3:0> signal at the output in response to the CLKW signal or the READOUTBx clock signal (e.g., to send a cold address in response to the row being filled).

[0076] During a write operation, the FLG<3:0> signal indicates whether the corresponding ADD<3:0> address is valid. Therefore, NAND gates 435(0)-(2) and selector circuit SEL 436(0)-(2) control whether the FLG<2:0> provided from the output of the previous one of the flag flip-flops 432(0)-(2) is provided to the input of the subsequent one of the flag flip-flops 432(1)-(3) based on the value of the FLG<3:0> signal. Additionally, selector circuit SEL 454(0)-(2) controls whether the ADD<2:0> bit provided from the output of the previous one of the address flip-flops 452(0)-(2) or the address bit from the instantaneous output of the address flip-flops 452(0)-(2) is provided to the input of the instantaneous one of the address flip-flops 452(1)-(3). For example, inverter 434 receives FLG... <0> The signal, and the selector circuit 436(0) receives the FLG. <0> and FLG <1> Signal.

[0077] If FLG <0> Signal indicates ADD <0> If the bit is valid, inverter 434 can enable selector circuit 436(0) and selector circuit 454(0) respectively, so as to select FLG respectively. <0> Signals and Add <0> The bits are provided as inputs to the flag flip-flop 432(1) and the address flip-flop 452(1), respectively. In this case, the flag signal and the address are passed to the right because all addresses are valid. Otherwise, the FLG output from the flag flip-flop 432(1) and the address flip-flop 452(1) is... <1> and ADD <1> The signal is fed back to its corresponding input.

[0078] If the FLG<1:0> signal indicates that the ADD<1:0> address is valid, then NAND gate 435(1) can enable selector circuit 436(1) and selector circuit 454(1) respectively to select the FLG<1:0> address. <1> Signals and Add <1> The bits are provided as inputs to the flag flip-flop 432(2) and the address flip-flop 452(2), respectively. In this case, the flag signal and the address are passed to the right because all addresses are valid. Otherwise, the FLG output from the flag flip-flop 432(2) and the address flip-flop 452(2) is... <2> and ADD <2> The signal is fed back to its corresponding input.

[0079] If the FLG<2:1> signal indicates that the ADD<2:1> address is valid, then NAND gate 435(2) can enable selector circuit 436(2) and selector circuit 454(2) respectively, so as to select the FLG<2:1> address respectively. <2> Signals and Add <2> The bits are provided as inputs to the flag flip-flop 432(3) and the address flip-flop 452(3), respectively. In this case, the flag signal and the address are passed to the right because all addresses are valid. Otherwise, the FLG output from the flag flip-flop 432(3) and the address flip-flop 452(3) is... <3> and ADD <3> The signal is fed back to its corresponding input.

[0080] Reference read enable / reset logic circuit 470, XNOR gate 442(1) can compare whether the new address ADDX is the same as ADD. <1> The address matches, and if so, the flag trigger 432(1) can be reset to FLG. <1> Signal to make ADD <1> Addresses are marked as invalid to prevent duplicate addresses from being stored in the cold data detector 400. It should be understood that the same principle used for the read enable / reset logic 570 applies to other similar logic circuits in the address matching logic 440, causing the corresponding FLG<3:0> signal to be reset in response to the detection of a matching address.

[0081] Although Figure 4 The cold data detector 400 depicted herein uses only a single address flip-flop and a single logic bit comparison for each time slot. However, it should be understood that, without departing from the scope of this disclosure, the flag path circuit 430 and the address matching logic circuit 440 may include additional circuitry to store and compare each bit or subset of the address to detect matches between addresses. Additionally, without departing from the scope of this disclosure, the address path circuit 450 may also include additional flip-flops for each time slot to store each data bit corresponding to the address. Although Figure 4 The cold data detector 400 contains four time slots, but it should be understood that the cold data detector 400 can be extended to contain any number of time slots without departing from the scope of this disclosure.

[0082] Figure 5 An exemplary timing diagram 500 includes write accesses associated with a bubble burst register according to embodiments of the present disclosure. Timing diagram 500 may be derived from... Figure 1 Cold data detector circuit 132 Figure 2 Cold data detector circuit 222 Figure 3 Any one and / or bank0-N cold data detector 310(0)-(N) Figure 4 The cold data detector 400 is implemented. The ADDX signal, CLKW signal, FLG<3:0> signal, and AddFF0-3 trigger can respectively correspond to Figure 4 The ADDX, CLKW, FLG<3:0> signals, ADDX address, and address flip-flops 452(0)-(3) are described. Time T0-T7 depicts the write operations associated with the bubble burst register.

[0083] Between times T0 and T1, in response to the CLKW signal, the first address ADD0 is received on the ADDX signal at the input of the first trigger time slot (e.g., AddFF0) of the bubble burst register, and FLG <0> The signal transitions to a high logic value. Between times T1 and T2, ADD0 begins to transition to the output of the first flip-flop time slot / input of the second flip-flop time slot (e.g., ADDFF1) based on the CLKW signal, and therefore, FLG <1> The signal transitions to a high logic value.

[0084] Furthermore, between times T1 and T2, in response to the CLKW signal, the second address ADD1 is received on the ADDX signal at the input of the first flip-flop time slot. FLG <0> The signal remains at a high logic value because the corresponding time slot continues to hold valid data. Between times T2 and T3, ADD0 begins to transition to the output of the second flip-flop time slot / input of the third flip-flop time slot (e.g., ADDFF2), and ADD1 begins to transition to the output of the first flip-flop time slot / input of the second flip-flop time slot (e.g., ADDFF1) based on the CLKW signal. Therefore, FLG <2> The signal transitions to a high logic value.

[0085] Furthermore, between times T2 and T3, in response to the CLKW signal, the third address ADD2 is received on the ADDX signal at the input of the first flip-flop time slot. FLG <0> Signal, FLG <1> Signals and FLG <2> All signals remain at high logic values ​​because the corresponding time slots continue to hold valid data. Between times T3 and T4, ADD0 begins to transition to the output of the third flip-flop time slot / input of the fourth flip-flop time slot (e.g., ADDFF3), ADD1 begins to transition to the output of the second flip-flop time slot / input of the third flip-flop time slot, and ADD2 begins to transition to the output of the first flip-flop time slot / input of the second flip-flop time slot based on the CLKW signal. Therefore, FLG <3> The signal transitions to a high logic value.

[0086] Furthermore, between times T3 and T4, in response to the CLKW signal, the fourth address ADD3 is received on the ADDX signal at the input of the first flip-flop time slot. FLG <0> Signal, FLG <1> Signal, FLG <2> and FLG <3> All signals remain at high logic values ​​because the corresponding time slots continue to hold valid data.

[0087] Between times T4 and T5, in response to the CLKW signal, the ADD2 address is received on the ADDX signal at the input of the first trigger time slot. A match is detected by ADD2 stored in the ADDFF1 time slot, and therefore, FLG is cleared. <1> Signal.

[0088] Between times T5 and T6, in response to the CLKW signal, the ADD1 address is received on the ADDX signal at the input of the first trigger time slot. A match is detected by ADD1 stored in the ADDFF2 time slot, and therefore, FLG is cleared. <2> Signal.

[0089] Between times T6 and T7, in response to the CLKW signal, the ADD4 address is received on the ADDX signal at the input of the first flip-flop time slot. In response to the ADD4 address, ADD3 begins to transition to the output of the first flip-flop time slot / input of the second flip-flop time slot (e.g., ADDFF1), and a new ADD4 begins to transition into the first flip-flop time slot. Therefore, FLG <1> The signal transitions to a high logic value. A match is detected via ADD1 stored in the ADDFF2 time slot, and therefore, FLG is cleared. <2> Signal. After time T7, ADD3 begins to transition to the output of the second flip-flop time slot / input of the third flip-flop time slot (e.g., ADDFF2), ADD2 begins to transition to the output of the first flip-flop time slot / input of the second flip-flop time slot (e.g., ADDFF1), and a new ADD1 begins to transition into the first flip-flop time slot. Therefore, FLG <2> The signal transitions to a high logic value.

[0090] Between times T7 and T8, in response to the CLKW signal, the ADD5 address is received on the ADDX signal at the input of the first flip-flop time slot. In response to the ADD5 address, ADD3 begins to transition to the output of the second flip-flop time slot / input of the third flip-flop time slot (e.g., ADDFF2), ADD4 begins to transition to the output of the first flip-flop time slot / input of the second flip-flop time slot (e.g., ADDFF1), and a new ADD4 begins to transition into the first flip-flop time slot. Therefore, FLG... <2> The signal transitions to a high logic value. After time T8, in response to the CLKW signal, the address ADD6 is received on the ADDX signal at the input of the first flip-flop time slot, but the bubble burst register is full, so the address is ignored.

[0091] As previously noted, timing diagram 500 is exemplary. The timing relationships are not intended to be drawn to scale, and it should be understood that other timing relationships may be implemented without departing from the scope of this disclosure.

[0092] Figure 6 This is a block diagram of a cold data readout circuit 600 according to an embodiment of the present disclosure. The cold data readout circuit 600 includes a shift register having series-coupled latch circuits 620(0)-(3), each latch circuit configured to store a corresponding memory row cold address BK0-3 COLD ADD. In some instances, the shift register of the cold data readout circuit 600 may contain a time slot for each row of the memory cell array. While the cold data readout circuit 600 is depicted with four series-coupled latch circuits 620(0)-(3) to support a four-row memory array, it should be understood that the cold data readout circuit 600 may be extended to accommodate memory arrays with more than four rows without departing from the scope of the present disclosure. The shift register may contain a time slot for each of the N memory rows of the memory cell array. In some instances, Figure 1 The cold data detector circuit of the main memory 130 Figure 2 Cold data readout circuit 271 and / or Figure 3 The cold data readout circuit 311 can implement the cold data readout circuit 600.

[0093] The cold data readout circuit 600 may further include multiplexers 610(0)-(3) that are selectively configured to provide one of the outputs of the previous one of the corresponding BK0-3 COLD ADD or series-coupled latch circuits 620(0)-(2) to the subsequent one of the series-coupled latch circuits 620(1)-(3) (e.g., where the input to the multiplexer 610(3) is null or zero). The multiplexers 610(0)-(3) may be controlled by a memory fill signal FULL. The FULL signal may be set by a NOR gate 604 in response to each of the FULLBKF<3:0> signals indicating that the corresponding BANK0-3 is filled. Cold data can be detected from the corresponding BANK0-3 cold data detector (e.g., Figure 3 The BANK0-N cold data detector 310(0)-(N)) receives the BK0-3 cold address.

[0094] The cold data readout circuit 600 may further include multiplexers 630(0)-(3) that are selectively configured to provide either a corresponding READOUTB0-3 or a shift clock signal SHIFTCLK to a corresponding one of the series-coupled latch circuits 620(0)-(3). The multiplexers 630(0)-(3) may be controlled by a FULL signal. Therefore, when the FULL signal indicates that the memory is not yet full, the multiplexer 610(0)-(3) can provide the corresponding BK0-3 cold address to the input of the corresponding one of the series-coupled latch circuits 620(1)-(3), and the multiplexer 630(0)-(3) can be configured to provide the corresponding READOUTB0-3 clock signal to the corresponding one of the series-coupled latch circuits 620(1)-(3) so that the corresponding one of the series-coupled latch circuits 620(1)-(3) latches the corresponding BK0-3 cold address.

[0095] The cold data readout circuit 600 may further include a pulse generator 640 configured to provide a SHIFTCLK signal based on the value of the FULL signal. The pulse generator 640 may be configured to cause the series-coupled latch circuits 620(0)-(3) to shift the stored BK0-3 cold addresses from left to right, such that each of the stored BK0-3 cold addresses is ultimately provided in the cold address output COLDADD. <x>Therefore, when the FULL signal indicates that the memory is full, multiplexer 610(0)-(3) can series-couple the output of series-coupled latch circuit 620(0)-(2) to the input of series-coupled latch circuit 620(1)-(3), and multiplexer 630(0)-(3) can be configured to provide a SHIFTCLK signal to each of the series-coupled latch circuits 620(1)-(3) so that each of the series-coupled latch circuits 620(1)-(3) is re-latched by each pulse on the SHIFTCLK signal. Pulse generator 640 can be configured to provide a number of pulses on the SHIFTCLK signal equal to the number of series-coupled latch circuits 620(0)-(3).

[0096] Figure 7 This is a block diagram of a system-on-a-chip (SoC) memory system 700 according to embodiments of the present disclosure. The memory system 700 may include a semiconductor chip 710 having an auxiliary memory 720 and a primary memory 730, and an SoC controller 740 configured to use a translation backstop (TLB) 742 to manage data storage locations between the auxiliary memory 720 and the primary memory 730, in order to route access requests to the correct memory. In some instances, the primary memory 730 may include volatile memory, and the auxiliary memory 720 may include non-volatile memory. In some instances, Figure 1 The memory module 110 may implement a semiconductor chip 710. The main memory 730 may implement... Figure 1 Main memory 130, and / or Figure 2 The semiconductor device 200 may implement the main memory 730, and Figure 1 The auxiliary memory 120 may be implemented as auxiliary memory 720.

[0097] The SoC controller 740 can be configured to receive commands (CMD), addresses (ADD), and data from a host or memory controller (not shown) to perform access operations (e.g., read, write, etc.) to maintain data on the memory system 700. The auxiliary memory 720 may contain flash memory or another type of NVM, and the primary memory 730 may contain any type of DRAM, including dual data rate (DDR) 3, DDR4, DDR5, low-power DDR, graphics DDR, etc.

[0098] In some instances, when operating in a computing system, primary memory 730 may be configured as primary memory, configured to temporarily store data generated and consumed during processing tasks, and secondary memory 720 may be configured as secondary memory to provide supplementary and / or permanent storage in the event that primary memory 730 is full of stored data or in the event of a failure. In this example, primary memory 730 may be used to initially store data compared to secondary memory 720 due to its lower access latency, and when primary memory 730 is full of data, primary memory 730 may transfer some of the stored data to secondary memory 720 directly or via commands received from SoC controller 740 for long-term storage.

[0099] The primary memory 730 may include a cold data detector and a readout circuit 732, which are configured to trigger a transfer of data to the secondary memory 720 based on determining that the primary memory 730 is sufficiently full, thus freeing up more available space. In some instances, Figure 1 The main memory 130 includes a cold data detector and readout circuit. Figure 2 The cold data detector circuit 222 and / or the cold data readout circuit 271, Figure 3 BANK0-N cold data detector 301(0)-(N) and / or cold data readout circuit 311, Figure 4 A cold data detector 400 and / or cold data readout circuitry 600 may be implemented within the cold data detector and readout circuitry 732. At least two considerations for transferring data to the secondary memory 720 may include determining when to transfer data and determining which data to transfer. In some instances, the cold data detector and readout circuitry 732 may also specify which data to transfer to the secondary memory 720. Selecting which data to transfer may involve identifying which data is likely to be accessed for further processing and which data is unlikely to be accessed for further processing. That is, to mitigate the efficiency loss caused by the increased access latency of the secondary memory 720, it may be necessary to predict which data is hot data (e.g., data most likely to be requested for additional processing) and which data is cold data (e.g., data most likely not to experience an upcoming request for further processing). In one instance, hot data may be new and / or frequently accessed data within the primary memory 730, and cold data may include older, less frequently accessed data.

[0100] The determination of when to transfer data from the main memory 730 to the auxiliary memory 720 can be based on the cold data detector and the readout circuit 732's determination of when the main memory 730 is sufficiently filled with stored data (e.g., a threshold has been reached), making it necessary to reserve more memory space to accommodate future data storage.

[0101] In some instances that address one or two of these considerations, the cold data detector and readout circuitry 732 may include a bubble burst register or buffer architecture (e.g., Figure 4 The bubble burst register (or buffer architecture) of the cold data detector 400 is configured to capture and store access information indicating which segments or sections of a row of main memory are currently storing cold data (e.g., older data). By its very nature, the bubble burst register architecture may be able to indicate which segment of main memory contains cold data in response to control circuitry determining that each segment of the row has been accessed at least once.

[0102] The bubble burst register of the cold data detector and readout circuit 732 may comprise a shift register, but can be fully utilized by selectively shifting received data to fill empty time slots without waiting for the empty time slots to be shifted out of the end time slot. The bubble burst register may include flag circuitry containing a corresponding flag for each time slot in the register. Each corresponding flag can be configured to indicate whether a particular time slot in the register currently holds a valid fragment address. Thus, for a particular time slot, the corresponding flag indicates whether the fragment address stored in the corresponding address circuitry is valid. When the corresponding flag for a particular time slot indicates that the fragment address is invalid (e.g., an empty time slot or bubble in the register), shifting a new fragment address into the register can cause an empty time slot to be filled by shifting the existing fragment address from the previous time slot by one time slot, making the first end time slot available to shift the new fragment address in, while subsequent time slots storing valid fragment addresses remain unaffected.

[0103] For example, a register can contain four fragment address slots, where all slots except the third slot hold valid fragment addresses. When a new fragment address is received, the fragment address from the second slot can be shifted to fill the empty third slot, the fragment address from the first slot can be shifted to replace the data in the second slot, and the new fragment address can be shifted into the first slot. In this example, the fourth slot remains unaffected by the shifts.

[0104] In some instances, the bubble burst register of the cold data detector and readout circuit 732 can be used to store a finite subset of segment addresses for rows of memory arrays used in a semiconductor device. When a new segment address matching a previously stored segment address is received, the previously stored segment address can be invalidated (e.g., by setting or clearing the corresponding flag), and the new segment address can be shifted into the register. Invalidating a previously stored segment address can cause the previously stored segment address to be overwritten. In some instances, the size of the bubble burst register (e.g., the number of time slots) can be based on the number of segments in main memory.

[0105] As each time slot of the register is filled, each flag can indicate that each time slot has a valid segment address. Control circuitry can be coupled to the bubble burst register and can cause the bubble burst register to provide cold address data at its output in response to detecting at least one access to each segment in the group. The control circuitry may include corresponding latching circuitry for each segment in the group, logic gates for detecting when each latch is set, and a pulse generator for causing the bubble burst register to provide cold address data from the bubble burst register. Each individual latch can be set in response to receiving activation of the corresponding segment address. In some instances, the coldest data can be determined based on the segment address stored in the last time slot of the bubble burst register.

[0106] Cold address data output from the bubble burst register for each row group can be provided to and stored in a shift register of the cold data detector and readout circuit 732. The shift register may contain time slots for each row group in the main memory 730, and in response to each time slot being filled, the logic circuitry of the cold data detector and readout circuit 732 can send a fill signal FULL along with the cold data address. <x>The data is sent to the SoC controller 740. In response, the SoC controller 740 issues a transfer command to the main memory 730 to initiate the transfer with the cold data addressee. <x>The associated cold data is directly transferred from the main memory 730 to the auxiliary memory 720. The SoC controller 740 can also update the TLB 742 to reference the location of the transferred cold data in the auxiliary memory 720.

[0107] Compared to counters and other conventional circuit systems implemented for this purpose, the bubble burst register architecture in the cold data detector circuit of the main memory 730 provides a more efficient mechanism for managing storage at the main memory 730 to determine when to trigger the transfer of data from the main memory 730 to the auxiliary memory 720 and to determine which data to transfer.

[0108] While preferred embodiments and examples are described in detail, those skilled in the art will understand that the scope of this disclosure extends from the specifically disclosed embodiments to other alternative embodiments and / or the use of said embodiments and their obvious modifications and equivalents. Furthermore, other modifications within the scope of this disclosure will be apparent to those skilled in the art. Various combinations or sub-combinations of specific features and aspects of the embodiments are also prudently considered and remain within the scope of this disclosure. It should be understood that various features and aspects of the disclosed embodiments may be combined with or substituted for each other to form variations of the disclosed embodiments. Therefore, it is contemplated that the scope of at least some of this disclosure should not be limited to the specific disclosed embodiments described above.< / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x>

Claims

1. A device for a memory system, comprising: A memory cell array comprising multiple rows, wherein each row contains multiple segments, and each segment is associated with a corresponding segment address. as well as A cold data detector circuit, corresponding to one of the plurality of rows, includes a register having a plurality of time slots configured to store the address of a received segment, wherein in response to detecting that each of the respective plurality of segments of the row has been subjected to at least one access operation, the cold data detector circuit is configured to provide the address of the longest stored segment from the register to an output as a cold address, wherein each of the plurality of rows corresponds to a corresponding cold data detector circuit.

2. The device of claim 1, wherein during an access operation associated with a target segment among the respective plurality of segments, each of the plurality of time slots preceding a specific time slot indicated as empty in the register is shifted by one time slot to fill the specific time slot, such that a first end time slot among the plurality of time slots is available to receive the address of the corresponding target segment associated with the target segment.

3. The device of claim 2, wherein each of the plurality of time slots following the specific time slot retains the existing corresponding segment address.

4. The apparatus of claim 2, wherein during the access operation associated with the target segment among the respective plurality of segments, the cold data detector circuitry is configured to compare the address of the respective segment stored in the register with the address of the respective target segment, wherein in response to determining that one of the corresponding segment addresses stored in the register matches the address of the respective target segment, the cold data detector circuitry is configured to invalidate the matching segment address among the corresponding segment addresses stored in the register and store the address of the respective target segment in the register.

5. The device of claim 1, further comprising a cold data readout circuit having a shift register configured to store the cold address in a specific location.

6. The device of claim 1, wherein the memory cell array further includes a second cold data detector circuit corresponding to a second row of the plurality of rows, wherein the second cold data detector circuit includes a second register having a second plurality of time slots configured to store received segment addresses associated with corresponding plurality of segments of the second row, wherein in response to detecting that each of the corresponding plurality of segments of the second row has been subjected to at least one access operation, the second cold data detector circuit is configured to provide the longest stored segment address from the second register to an output as a second cold address.

7. The device according to claim 1, further comprising: A plurality of cold data detector circuits, each of the plurality of cold data detector circuits corresponding to a corresponding row in the plurality of rows and each including a corresponding register, wherein in response to detecting that each of the respective plurality of segments in the corresponding row has been subjected to at least one access operation, each of the plurality of cold data detector circuits is configured to provide the address of the corresponding longest stored segment from the corresponding register as the corresponding cold address. as well as A cold data readout circuit having a shift register having a plurality of time slots, each of the plurality of time slots being configured to store the corresponding cold address from a particular one of the plurality of cold data detector circuits, wherein the cold data readout circuit is configured to initiate the transfer of cold data from the memory cell array to another memory in response to receiving a row fill signal from each of the plurality of cold data detector circuits.

8. The device of claim 7, wherein the cold data readout circuitry is further configured to update a mode register in response to the transfer of cold data from the memory cell array to another memory.

9. The device of claim 7, wherein the memory cell array comprises volatile memory cells.

10. The device of claim 7, wherein the other memory comprises non-volatile memory.

11. A device for a memory system, comprising: A first memory having a first access delay; A second memory having a second access latency less than the first access latency, wherein the second memory includes a memory cell array comprising a plurality of rows, each of the plurality of rows containing a corresponding plurality of segments, each of the respective plurality of segments being associated with a corresponding segment address, the second memory further including a plurality of cold data detector circuits, each of the plurality of cold data detector circuits corresponding to a corresponding one of the plurality of rows and each including a corresponding register, wherein each of the corresponding registers is configured to store a segment address, wherein in response to detecting that each segment of a particular row has been targeted as at least one access operation, the corresponding cold data detector circuit of the plurality of cold data detector circuits is configured to provide a corresponding longest stored segment address from the corresponding register to a cold data readout circuit, wherein the cold data readout circuit is configured to provide an indication to transfer cold data from the first memory to the second memory in response to receiving the corresponding longest stored segment address from each of the plurality of cold data detector circuits.

12. The device of claim 11, wherein the depth of the corresponding register of one of the plurality of cold data detectors is less than the count of the corresponding plurality of segments in the plurality of rows corresponding to the one of the plurality of cold data detectors.

13. The device of claim 11, wherein the cold data readout circuitry includes a shift register having a plurality of time slots, each of the plurality of time slots being configured to store the address of the corresponding longest stored segment from a particular one of the plurality of cold data detectors.

14. The device of claim 11, wherein the first memory and the second memory are part of a memory module or a system on a chip.

15. The device of claim 11, wherein the first memory is a non-volatile memory and the second memory is a volatile memory.

16. A method of operating a memory system, comprising: During an access operation associated with a row of multiple segments of a memory cell array, a segment address is stored in a register with multiple time slots of a cold data detector circuit, wherein each segment address is associated with a corresponding segment among the multiple segments. In response to detecting that each of the plurality of segments in the row has been accessed, the address of the longest stored segment is transmitted to the cold data readout circuit as a cold address; as well as In response to receiving the address of the longest stored segment from each of the multiple registers corresponding to the multiple rows of the memory cell array, the transfer of cold data from the memory cell array to another memory is initiated.

17. The method of claim 16, further comprising, during an access operation associated with a target segment among the plurality of segments, shifting each of a plurality of time slots preceding a specific time slot indicated as empty in the plurality of time slots of the register by one time slot to fill the specific time slot, such that a first end time slot among the plurality of time slots is available to receive a corresponding target segment address associated with the target segment.

18. The method of claim 17, further comprising during the access operation associated with the target segment among the plurality of segments: Compare the fragment address stored in the register with the corresponding target fragment address; and In response to determining that one of the fragment addresses stored in the register matches the corresponding target fragment address, the matching fragment address stored in the register is invalidated, and the corresponding target fragment address is stored in the register.

19. The method of claim 16, further comprising, in response to the detection that each of the plurality of segments of the row has been accessed, providing the address of the segment stored in the last time slot of the register as the address of the longest stored segment.

20. The method of claim 16, wherein the memory cell array comprises non-volatile memory cells, and the other memory comprises non-volatile memory.

Images