A test structure based on odd-level and even-level layout separation and a method thereof

Abstract

The application provides a test structure based on odd-level and even-level layout separation and a method thereof. The layout of a chip is divided into odd-level and even-level parts, and the two parts are tested respectively. The specific implementation is as follows: first, the layout of the chip is divided into odd-level and even-level parts; then, each circuit in the odd-level and even-level parts is tested respectively. The test structure includes two parts: one is a test signal generator for generating test signals; the other is a test signal collector for collecting output signals of the tested circuit. The test signal generator and the test signal collector can adopt a conventional scan chain or boundary scan. Finally, the test results of the odd-level and even-level parts are combined to obtain the test result of the whole chip.

Description

Technical Field

[0001] This invention relates to the field of single-event irradiation testing of integrated circuits, and more specifically, to a test structure and method based on odd-level and even-level layout separation. Background Technology

[0002] With the continuous development of integrated circuit technology, the complexity and density of integrated circuits are constantly increasing, making reliable and efficient testing under single-event irradiation conditions increasingly difficult. Existing single-event testing structures often cannot distinguish whether heavy ions are affecting NMOS or PMOS transistors in integrated circuits, making it difficult to meet the testing requirements of high-density integrated circuits, and the testing cost is also high. Therefore, we propose an improvement based on odd-level and even-level layout separation and its method. Summary of the Invention

[0003] The purpose of this invention is to address the problems raised in the existing background technology. To achieve the above-mentioned objective, this invention provides the following technical solution: a test structure based on odd-level and even-level layout separation, which divides the chip layout into odd-level and even-level layouts, and designs test structures for each part. The test structures employ either a traditional scan chain or a boundary scan chain. (Scan); The test signal generator can be implemented using any suitable circuit, including but not limited to multivibrators and Gray code generators; The test signal acquisition unit can be implemented using any suitable circuit, including but not limited to comparators and inverters; Different test strategies are used for odd-numbered and even-numbered test structures to improve test efficiency and accuracy; Test structure circuit and layout; The circuit inputs are connected in series through NAND gates, and each NAND gate is cascaded through a port, leaving one port as the excitation input port, i.e., IN0, IN1, IN2, IN3, and IN4 in the figure. These ports can be connected to fixed inputs or other signal sources and circuits to generate test excitations; The changes in the signals of odd-numbered and even-numbered levels are different. If the output signal of the odd-numbered level is always 1 under normal circumstances, then the output signal of the even-numbered level is always 0, and vice versa; By analyzing whether the output data flips from 0 to 1 or from 1 to 0, it can be determined whether the fault or flipping circuit occurs in the odd-numbered or even-numbered level.

[0004] As a preferred technical solution of the present invention, control logic and data processing circuits are connected in odd-level and even-level layouts. The test controller uses a counter or state machine to control the allocation order and time interval to allocate test sequences to odd-level and even-level layouts. The test controller will send the corresponding test sequences to the odd-level and even-level layouts according to the test sequence allocation logic.

[0005] As a preferred technical solution of the present invention, corresponding data interface circuits are added in the odd-level layout and even-level layout to connect with the data transmission channel; these interface circuits include data input buffers and data output buffers for receiving and sending data; the interface logic of the data transmission channel is implemented in the odd-level layout and even-level layout respectively; this includes transmitting data from the input buffer to the channel, and transmitting data from the channel to the output buffer.

[0006] As a preferred technical solution of the present invention, the data transmission channel transmits the received data to the input buffers of the odd-level layout and the even-level layout; the odd-level layout and the even-level layout receive the data from the input buffers and perform corresponding processing and operations; after processing, the odd-level layout and the even-level layout transmit the result data to the output buffer; the data transmission channel transmits the data in the output buffers of the odd-level layout and the even-level layout to the test controller.

[0007] A test method based on odd-level and even-level layout separation, step 1: provide odd-level layout and even-level layout; wherein, the odd-level layout is used to test odd-level logic circuits, and the even-level layout is used to test even-level logic circuits; the odd-level layout and even-level layout are independent of each other;

[0008] Step 2: Pre-set the test sequence; the test sequence includes a series of test stimuli and test data, used to test the functionality and performance of the logic circuit;

[0009] Step 3: Control the testing process of odd-level and even-level layouts through a test controller; the test controller tests the odd-level and even-level layouts according to a pre-set test sequence; the test controller allocates the test sequence to the odd-level and even-level layouts as needed to achieve parallel testing;

[0010] Step 4: Set up a data transmission channel between odd-level and even-level layouts; the data transmission channel is used to transmit test data between odd-level and even-level layouts; test data is transmitted from odd-level to even-level layouts, or from even-level to odd-level layouts, through the data transmission channel.

[0011] As a preferred technical solution of the present invention, step 1: providing odd-level layout and even-level layout, the specific steps are as follows:

[0012] S11. Based on the test requirements and circuit design, determine the structure and function of odd-level and even-level logic circuits;

[0013] S12. Design the logic circuit diagrams for odd-level and even-level layouts, including combinational logic units, flip-flops, and clock elements;

[0014] S13. Based on the logic circuit diagram, perform layout design, and place the positions and connections of logic elements;

[0015] S14. Use appropriate circuit design software for layout and routing;

[0016] S15. Complete the layout design and routing for odd-level and even-level layouts, and generate the corresponding layout files.

[0017] As a preferred technical solution of the present invention, step 2: pre-setting the test sequence, the specific steps are as follows:

[0018] S21. Analyze the functional and performance requirements of the logic circuit, and determine the functional and performance parameters that need to be tested;

[0019] S22. Design a test sequence based on functional and performance requirements, including test stimuli and test data;

[0020] S23. Based on the design of the test sequence, write the test program or generate the test sequence file;

[0021] S24. Store the test sequence file in the test controller for use in subsequent testing processes.

[0022] As a preferred technical solution of the present invention, step 3: the specific process of controlling the testing of odd-level and even-level layouts through a test controller is as follows:

[0023] S31. Connect the test controller to the odd-level and even-level layouts to ensure normal communication;

[0024] S32. Set the test mode and parameters in the test controller, including clock frequency and test sequence selection;

[0025] S33. Start the test controller and send test commands and test data to the odd-level and even-level layouts;

[0026] S34. Monitor the output signals of odd-level and even-level layouts, and perform data acquisition and analysis through the test controller;

[0027] S35. Based on the test results, determine whether the functions and performance of odd-level and even-level layouts meet the requirements.

[0028] As a preferred technical solution of the present invention, step 4: set up a data transmission channel between odd-level layouts and even-level layouts; the specific process of the data transmission channel for transmitting test data between odd-level layouts and even-level layouts is as follows: S41. Determine the data transmission requirements between odd-level layouts and even-level layouts, including the data type and transmission rate to be transmitted;

[0029] S42. Design the structure and interface of the data transmission channel, including the data input and output ports, the width of the data bus, and realize the circuit connection and signal transmission of the data transmission channel. Add corresponding data interface circuits in the odd-level and even-level layouts to connect with the data transmission channel.

[0030] S43. Set the parameters of the data transmission channel in the test controller, including the transmission mode and clock frequency; start the test controller and send test data to the odd-level and even-level layouts through the data transmission channel;

[0031] S44. Monitor the data interfaces in odd-level and even-level layouts, exchange and transmit data through the data transmission channel, and determine whether the performance and reliability of the data transmission channel meet the requirements based on the transmission results.

[0032] As a preferred technical solution of the present invention, S44. The specific steps for determining whether the performance and reliability of the data transmission channel meet the requirements are as follows: S441. Data integrity: Check whether the receiving end has successfully received all the data sent by the sending end and is completely consistent with the data sent by the sending end; verify by comparing the data of the sending end and the receiving end.

[0033] S442. Timing correctness: Verify whether the data transmission channel can transmit data on time at the specified clock frequency; determine whether there are timing deviations or clock cycle instability by checking the arrival time of the data and the stability of the clock signal;

[0034] S443. Transmission Rate: Based on the design requirements, compare the actual transmission rate with the expected transmission rate; if the actual transmission rate is significantly lower than the expected transmission rate, there may be problems such as insufficient transmission bandwidth or excessive transmission delay.

[0035] S444. Interference immunity: Check whether the data transmission channel is affected by interference from other signals or the environment; test the interference immunity of the data transmission channel by introducing external interference or simulated noise;

[0036] S445. Error Rate: Count the number of errors that may occur during transmission and compare it with the design tolerance error rate; if the error rate exceeds the design tolerance range, there may be errors or noise problems in the transmission process.

[0037] S446. Reliability Analysis: Verify the reliability of the data transmission channel through long-term operation tests or large-volume data transmission tests; if no abnormalities or errors occur during long-term or large-volume data transmission tests, the data transmission channel is considered to have high reliability.

[0038] As a preferred technical solution of the present invention, the beneficial effects of the present invention compared with the prior art are as follows:

[0039] 1. By adopting an odd-level and even-level layout separation method, the test structure is distributed to different parts of the chip, reducing the chip area occupied by the test structure and improving chip performance and production cost.

[0040] 2. Employ multiple testing strategies to improve testing efficiency and accuracy, ensuring chip quality.

[0041] 3. The test structure is designed to be flexible and diverse, and can be adjusted and optimized according to the different requirements of the chip. Attached Figure Description

[0042] Figure 1 The test structure circuit diagram provided by this invention;

[0043] Figure 2 The test structure layout provided for this invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0045] Therefore, the following detailed description of the embodiments of the present invention is not intended to limit the scope of the claimed invention, but merely illustrates some embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention. It should be noted that, in the absence of conflict, the embodiments and features and technical solutions in the embodiments of the present invention can be combined with each other. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0046] Example 1: Please refer to Figure 1-2A test structure based on odd-level and even-level layout separation is proposed. The chip layout is divided into odd-level and even-level layouts, and test structures are designed for each. The test structures employ either a traditional ScanChain or a Boundary test chain. Scan chain; the test signal generator can be implemented using any suitable circuit, including but not limited to multivibrators and Gray code generators; the test signal acquisition unit can be implemented using any suitable circuit, including but not limited to comparators and inverters; different test strategies are used for odd-numbered and even-numbered test structures to improve test efficiency and accuracy; test structure circuit and layout; the circuit inputs are connected in series through NAND gates, each NAND gate is cascaded through a port, and one port is reserved as the excitation input port, i.e., IN0, IN1, IN2, IN3, IN4 in the figure. These ports are both fixed inputs and connected to other signal sources and circuits to generate test excitations; the changes in signals at odd-numbered and even-numbered levels are different. If the output signal of the odd-numbered level is always 1 under normal circumstances, then the output signal of the even-numbered level is always 0, and vice versa; by analyzing whether the output data flips from 0 to 1 or from 1 to 0, it can be determined whether the fault or flipping circuit occurs at the odd-numbered or even-numbered level.

[0047] The control logic and data processing circuits are connected in the odd-level and even-level layouts. The test controller uses a counter or state machine to control the allocation order and time interval to allocate test sequences to the odd-level and even-level layouts. The test controller will send the corresponding test sequences to the odd-level and even-level layouts according to the test sequence allocation logic.

[0048] Add corresponding data interface circuits in the odd-level and even-level layouts to connect to the data transmission channel; these interface circuits include data input buffers and data output buffers for receiving and sending data; implement the interface logic of the data transmission channel in the odd-level and even-level layouts respectively; this includes transferring data from the input buffer to the channel and transferring data from the channel to the output buffer.

[0049] The data transmission channel transmits the received data to the input buffers of the odd-level and even-level layouts; the odd-level and even-level layouts receive the data from the input buffers, perform corresponding processing and operations; after processing, the odd-level and even-level layouts transmit the result data to the output buffer; the data transmission channel transmits the data in the output buffers of the odd-level and even-level layouts to the test controller.

[0050] A test method based on odd-level and even-level layout separation, step 1: provide odd-level layout and even-level layout; wherein, the odd-level layout is used to test odd-level logic circuits, and the even-level layout is used to test even-level logic circuits; the odd-level layout and even-level layout are independent of each other;

[0051] Step 2: Pre-set the test sequence; the test sequence includes a series of test stimuli and test data, used to test the functionality and performance of the logic circuit;

[0052] Step 3: Control the testing process of odd-level and even-level layouts through a test controller; the test controller tests the odd-level and even-level layouts according to a pre-set test sequence; the test controller allocates the test sequence to the odd-level and even-level layouts as needed to achieve parallel testing;

[0053] Step 4: Set up a data transmission channel between odd-level and even-level layouts; the data transmission channel is used to transmit test data between odd-level and even-level layouts; test data is transmitted from odd-level to even-level layouts, or from even-level to odd-level layouts, through the data transmission channel.

[0054] Step 1: Provide odd-level and even-level layouts. The specific steps are as follows:

[0055] S11. Based on the test requirements and circuit design, determine the structure and function of odd-level and even-level logic circuits;

[0056] S12. Design the logic circuit diagrams for odd-level and even-level layouts, including logic gates, flip-flops, and clock elements;

[0057] S13. Based on the logic circuit diagram, perform layout design, and place the positions and connections of logic elements;

[0058] S14. Use appropriate circuit design software for layout and routing;

[0059] S15. Complete the layout design and routing for odd-level and even-level layouts, and generate the corresponding layout files.

[0060] Step 2: Pre-set the test sequence. The specific steps are as follows:

[0061] S21. Analyze the functional and performance requirements of the logic circuit, and determine the functional and performance parameters that need to be tested;

[0062] S22. Design a test sequence based on functional and performance requirements, including test stimuli and test data;

[0063] S23. Based on the design of the test sequence, write the test program or generate the test sequence file;

[0064] S24. Store the test sequence file in the test controller for use in subsequent testing processes.

[0065] Step 3: The specific process of controlling the testing of odd-level and even-level layouts through a test controller is as follows:

[0066] S31. Connect the test controller to the odd-level and even-level layouts to ensure normal communication;

[0067] S32. Set the test mode and parameters in the test controller, including clock frequency and test sequence selection;

[0068] S33. Start the test controller and send test stimuli and test data to the odd-level and even-level layouts;

[0069] S34. Monitor the output signals of odd-level and even-level layouts, and perform data acquisition and analysis through the test controller;

[0070] S35. Based on the test results, determine whether the functions and performance of odd-level and even-level layouts meet the requirements.

[0071] Step 4: Set up a data transmission channel between odd-level and even-level layouts; the specific process of using the data transmission channel to transmit test data between odd-level and even-level layouts is as follows: S41. Determine the data transmission requirements between odd-level and even-level layouts, including the data type and transmission rate to be transmitted;

[0072] S42. Design the structure and interface of the data transmission channel, including the data input and output ports, the width of the data bus, and realize the circuit connection and signal transmission of the data transmission channel. Add corresponding data interface circuits in the odd-level and even-level layouts to connect with the data transmission channel.

[0073] S43. Set the parameters of the data transmission channel in the test controller, including the transmission mode and clock frequency; start the test controller and send test data to the odd-level and even-level layouts through the data transmission channel;

[0074] S44. Monitor the data interfaces in odd-level and even-level layouts, exchange and transmit data through the data transmission channel, and determine whether the performance and reliability of the data transmission channel meet the requirements based on the transmission results.

[0075] S44. The specific steps to determine whether the performance and reliability of the data transmission channel meet the requirements are as follows: S441. Data integrity: Check whether the receiving end has successfully received all the data sent by the sending end and whether it is completely consistent with the data sent by the sending end; verify by comparing the data of the sending end and the receiving end.

[0076] S442. Timing correctness: Verify whether the data transmission channel can transmit data on time at the specified clock frequency; determine whether there are timing deviations or clock cycle instability by checking the arrival time of the data and the stability of the clock signal;

[0077] S443. Transmission Rate: Based on the design requirements, compare the actual transmission rate with the expected transmission rate; if the actual transmission rate is significantly lower than the expected transmission rate, there may be problems such as insufficient transmission bandwidth or excessive transmission delay.

[0078] S444. Interference immunity: Check whether the data transmission channel is affected by interference from other signals or the environment; test the interference immunity of the data transmission channel by introducing external interference or simulated noise;

[0079] S445. Error Rate: Count the number of errors that may occur during transmission and compare it with the design tolerance error rate; if the error rate exceeds the design tolerance range, there may be errors or noise problems in the transmission process.

[0080] S446. Reliability Analysis: Verify the reliability of the data transmission channel through long-term operation tests or large-volume data transmission tests; if no abnormalities or errors occur during long-term or large-volume data transmission tests, the data transmission channel is considered to have high reliability.

[0081] This invention proposes a test structure based on odd-level and even-level layout separation, dividing the chip layout into odd-level and even-level parts, and designing test structures for each. The specific implementation is as follows: First, the chip layout is divided into odd-level and even-level parts. Then, a test structure is added to each circuit in both the odd-level and even-level parts. Each test structure consists of two parts: a test signal generator to generate test signals and a test signal acquisition unit to acquire the output signals of the circuit under test. Finally, the odd-level and even-level test structures are connected to form a complete test structure.

[0082] This invention proposes a testing method based on odd-level and even-level layout separation, dividing the chip layout into odd-level and even-level parts for separate testing. The specific implementation is as follows: First, the chip layout is divided into odd-level and even-level parts; then, each circuit in both the odd-level and even-level parts is tested separately. The test structure includes two parts: a test signal generator to generate test signals and a test signal acquisition unit to acquire the output signals of the circuit under test. The test signal generator and test signal acquisition unit can employ a traditional scan chain or bounded scan. Finally, the test results from the odd-level and even-level parts are combined to obtain the overall chip test result.

[0083] The present invention adopts the following embodiments:

[0084] 1. Divide the chip layout into odd-numbered and even-numbered levels, and design test structures for each level. The test structures adopt traditional scan chains or bounded scans.

[0085] 2. The test signal generator may be implemented using any suitable circuit, including but not limited to a multi-frequency oscillator or a Gray code generator.

[0086] 3. The test signal acquisition unit can be implemented using any suitable circuit, including but not limited to comparators and inverters.

[0087] 4. Different testing strategies are used for odd-numbered and even-numbered test structures to improve testing efficiency and accuracy.

[0088] The test circuit structure and layout diagram are shown in the figure below. The circuit inputs are connected in series through NAND gates. Each NAND gate is cascaded through a port, leaving one port as the excitation input port, namely IN0, IN1, IN2, IN3, and IN4 in the figure. These ports are used for both fixed inputs and connection to other signal sources and circuits to generate test excitations. The changes in signals at odd-numbered and even-numbered stages are different. If the output signal of the odd-numbered stage is always 1 under normal circumstances, then the output signal of the even-numbered stage is always 0, and vice versa. By analyzing whether the output data flips from 0 to 1 or from 1 to 0, it can be determined whether the fault or flipping circuit occurs at the odd-numbered stage or the even-numbered stage.

[0089] The above embodiments are only used to illustrate the present invention and are not intended to limit the technical solutions described in the present invention. Although the present invention has been described in detail with reference to the above embodiments, the present invention is not limited to the specific embodiments described above. Therefore, any modifications or substitutions to the present invention, and all technical solutions and improvements that do not depart from the spirit and scope of the invention, are covered within the scope of the claims of the present invention.

Claims

1. A test structure based on odd-level and even-level layout separation, characterized in that, The chip layout is divided into odd-level and even-level layouts, and test structures are designed for each. The test structures adopt traditional Scan Chain or Boundary. Scan chain; the test signal generator can be implemented using any suitable circuit, including but not limited to multivibrators and Gray code generators; the test signal acquisition unit can be implemented using any suitable circuit, including but not limited to comparators and inverters; different test strategies are used for odd-numbered and even-numbered test structures to improve test efficiency and accuracy; test structure circuit and layout; the circuit inputs are connected in series through NAND gates, each NAND gate is cascaded through a port, and one port is reserved as the excitation input port, i.e., IN0, IN1, IN2, IN3, IN4 in the figure. These ports are both fixed inputs and connected to other signal sources and circuits to generate test excitations; the changes in signals at odd-numbered and even-numbered levels are different. If the output signal of the odd-numbered level is always 1 under normal circumstances, then the output signal of the even-numbered level is always 0, and vice versa; by analyzing whether the output data flips from 0 to 1 or from 1 to 0, it can be determined whether the fault or flipping circuit occurs at the odd-numbered or even-numbered level.

2. The test structure based on odd-level and even-level layout separation according to claim 1, characterized in that, Connect control logic and data processing circuits in odd-level and even-level layouts. Use a counter or state machine controlled by a test controller to allocate test sequences to odd-level and even-level layouts according to the order and time interval. The test controller will send the corresponding test sequences to the odd-level and even-level layouts based on the test sequence allocation logic.

3. The test structure based on odd-level and even-level layout separation according to claim 2, characterized in that, Add corresponding data interface circuits in the odd-level and even-level layouts to connect to the data transmission channel; these interface circuits include data input buffers and data output buffers for receiving and sending data; implement the interface logic of the data transmission channel in the odd-level and even-level layouts respectively; this includes transferring data from the input buffer to the channel and transferring data from the channel to the output buffer.

4. The test structure based on odd-level and even-level layout separation according to claim 3, characterized in that, The data transmission channel transmits the received data to the input buffers of the odd-level and even-level layouts; the odd-level and even-level layouts receive the data from the input buffers and perform corresponding processing and operations. After processing, the odd-level and even-level layouts transfer the result data to the output buffer. The data transmission channel transmits data from the output buffers of the odd-level and even-level layouts to the test controller.

5. A test method based on odd-level and even-level layout separation, wherein the method is implemented using the test structure based on odd-level and even-level layout separation as described in claim 1, characterized in that, Step 1: Provide odd-level and even-level layouts; the odd-level layout is used to test odd-level logic circuits, and the even-level layout is used to test even-level logic circuits; the odd-level and even-level layouts are independent of each other; Step 2: Pre-set the test sequence; the test sequence includes a series of test stimuli and test data, used to test the functionality and performance of the logic circuit; Step 3: Control the testing process of odd-level and even-level layouts through a test controller; the test controller tests the odd-level and even-level layouts according to a pre-set test sequence; the test controller allocates the test sequence to the odd-level and even-level layouts as needed to achieve parallel testing; Step 4: Set up a data transmission channel between odd-level and even-level layouts; the data transmission channel is used to transmit test data between odd-level and even-level layouts; test data is transmitted from odd-level to even-level layouts, or from even-level to odd-level layouts, through the data transmission channel.

6. The test method based on odd-level and even-level layout separation according to claim 5, characterized in that, Step 1: Provide odd-level and even-level layouts. The specific steps are as follows: S11. Based on the test requirements and circuit design, determine the structure and function of odd-level and even-level logic circuits; S12. Design the logic circuit diagrams for odd-level and even-level layouts, including logic gates, flip-flops, and clock elements; S13. Based on the logic circuit diagram, perform layout design, and place the positions and connections of logic elements; S14. Use appropriate circuit design software for layout and routing; S15. Complete the layout design and routing for odd-level and even-level layouts, and generate the corresponding layout files.

7. The test method based on odd-level and even-level layout separation according to claim 6, characterized in that, Step 2: Pre-set the test sequence. The specific steps are as follows: S21. Analyze the functional and performance requirements of the logic circuit, and determine the functional and performance parameters that need to be tested; S22. Design a test sequence based on functional and performance requirements, including test stimuli and test data; S23. Based on the design of the test sequence, write the test program or generate the test sequence file; S24. Store the test sequence file in the test controller for use in subsequent testing processes.

8. The test method based on odd-level and even-level layout separation according to claim 7, characterized in that, Step 3: The specific process of controlling the testing of odd-level and even-level layouts through a test controller is as follows: S31. Connect the test controller to the odd-level and even-level layouts to ensure normal communication; S32. Set the test mode and parameters in the test controller, including clock frequency and test sequence selection; S33. Start the test controller and send test stimuli and test data to the odd-level and even-level layouts; S34. Monitor the output signals of odd-level and even-level layouts, and perform data acquisition and analysis through the test controller; S35. Based on the test results, determine whether the functions and performance of odd-level and even-level layouts meet the requirements.

9. The test method based on odd-level and even-level layout separation according to claim 8, characterized in that, Step 4: Set up a data transmission channel between odd-level and even-level layouts; the specific process of using the data transmission channel to transmit test data between odd-level and even-level layouts is as follows: S41. Determine the data transmission requirements between odd-level and even-level layouts, including the data type and transmission rate to be transmitted; S42. Design the structure and interface of the data transmission channel, including the data input and output ports, the width of the data bus, and realize the circuit connection and signal transmission of the data transmission channel. Add corresponding data interface circuits in the odd-level and even-level layouts to connect with the data transmission channel. S43. Set the parameters of the data transmission channel in the test controller, including the transmission mode and clock frequency; start the test controller and send test data to the odd-level and even-level layouts through the data transmission channel; S44. Monitor the data interfaces in odd-level and even-level layouts, exchange and transmit data through the data transmission channel, and determine whether the performance and reliability of the data transmission channel meet the requirements based on the transmission results.

10. A test method based on odd-level and even-level layout separation according to claim 9, characterized in that, S44. The specific steps to determine whether the performance and reliability of the data transmission channel meet the requirements are as follows: S441. Data integrity: Check whether the receiving end has successfully received all the data sent by the sending end and whether it is completely consistent with the data sent by the sending end; verify by comparing the data of the sending end and the receiving end. S442. Timing correctness: Verify whether the data transmission channel can transmit data on time at the specified clock frequency; determine whether there are timing deviations or clock cycle instability by checking the arrival time of the data and the stability of the clock signal; S443. Transmission Rate: Based on the design requirements, compare the actual transmission rate with the expected transmission rate; if the actual transmission rate is significantly lower than the expected transmission rate, there may be problems such as insufficient transmission bandwidth or excessive transmission delay. S444. Interference immunity: Check whether the data transmission channel is affected by interference from other signals or the environment; The anti-interference performance of the data transmission channel is tested by introducing external interference or simulated noise. S445. Error Rate: Statistically calculate the number of errors that may occur during transmission and compare it with the design tolerance error rate; If the error rate exceeds the design tolerance range, there may be errors or noise problems during transmission; S446. Reliability Analysis: Verify the reliability of the data transmission channel through long-term operation tests or large-volume data transmission tests; If no abnormalities or errors occur during long-term or large-scale data testing, the data transmission channel is considered to have high reliability.

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