Multi-data lane backplane, multi-data lane management method and system

Abstract

The application relates to the technical field of vehicle-mounted control equipment, and particularly provides a multi-data-channel backboard, a multi-data-channel management method and system.The multi-data-channel backboard comprises a plurality of control chips and a plurality of network switch chips;the plurality of control chips are connected with a plurality of slots through respective corresponding communication chips;the plurality of network switch chips are connected with the plurality of slots; and the plurality of slots are respectively connected with external processing board cards.The application improves the overall stability and reliability of the vehicle-mounted control equipment.

Description

Technical Field

[0001] This invention belongs to the field of vehicle control equipment technology, specifically relating to a multi-data channel backplane, a multi-data channel management method and system. Background Technology

[0002] In the field of autonomous driving vehicles, highly reliable controllers are required to ensure vehicle and personal safety. Therefore, controllers are typically designed with dual or multiple backups. For example, some controllers use master-slave backup, with the interface limited to a direct connection between the master and slave CPUs. Others use gigabit networks for dual network backup.

[0003] However, backup modules don't necessarily have two identical interfaces. For example, in a dual-gigabit network, additional conversion circuits from other interfaces to this one are needed, increasing complexity. In a master-slave backup architecture, asymmetrical functional modules, inconsistent development, and inconsistent interfaces lead to poor scalability; for instance, it cannot implement triple backup. Multiple backups with the same interface, such as dual-gigabit network backup, have a high probability of encountering the same problem due to their identical circuit signal structures, rendering the backup ineffective. Summary of the Invention

[0004] To address the problems of existing technologies, such as the need for conversion circuits or poor dual backup performance, this invention provides a multi-data-channel backplane, a multi-data-channel management method, and a system to solve the aforementioned technical problems.

[0005] In a first aspect, the present invention provides a multi-data-channel backplane, comprising:

[0006] Multiple control chips and multiple network switch chips;

[0007] Multiple control chips are connected to multiple slots through their respective communication chips;

[0008] Multiple network switch chips are connected to multiple slots respectively;

[0009] Each of the slots is respectively connected to an external processing board.

[0010] In one optional implementation, the multiple control chips include a first control chip and a second control chip. The first control chip acts as a PCIe master device and is connected to a PCIe conversion chip. The PCIe conversion chip is connected to multiple slots, and a processing board inserted into the slot acts as a PCIe slave device. The second control chip is connected to a USB interface chip, which is connected to multiple slots.

[0011] In one optional implementation, the first control chip and the second control chip are connected via a UPI bus.

[0012] Secondly, the present invention provides a multi-data channel management method, comprising:

[0013] Each control chip monitors the number of pending tasks in its own task queue;

[0014] The control chips negotiate to determine the first target chip with the largest number of tasks to be processed and the second target chip with the smallest number of tasks to be processed.

[0015] Transfer the processing board managed by the first target chip to the second target chip;

[0016] If a faulty control chip is confirmed, the processing board managed by the faulty control chip will be transferred to the normal control chip.

[0017] In one optional implementation, each control chip monitors the number of pending tasks in its own task queue, including:

[0018] A task queue is created in the control chip, which is used to cache and process the service requests of the board;

[0019] Create a monitoring thread that periodically collects the number of tasks in the task queue.

[0020] In an optional implementation, each control chip negotiates to determine a first target chip with the largest number of tasks to be processed and a second target chip with the smallest number of tasks to be processed, including:

[0021] The control chip saves the number of tasks to be processed and the IP address to the negotiation list, and sends the negotiation list to the next control chip that does not have a corresponding mark, until all control chips have been traversed.

[0022] Finally, the control chip that receives the negotiation list selects the first IP of the first target chip corresponding to the maximum number of pending tasks and the second IP of the second target chip corresponding to the minimum number of pending tasks from the negotiation list.

[0023] Send a first notification message to the first IP address, the first notification message including instructions to transfer the processing board and the second IP address;

[0024] Send a second notification message to the second IP address, the second notification message including instructions for receiving the processing board and the first IP address.

[0025] In an optional implementation, transferring the processing board managed by the first target chip to the second target chip includes:

[0026] The first target chip and the second target chip establish a dialogue based on the first notification information and the second notification information. The second target chip sends the number of processing boards it manages to the first target chip through the dialogue.

[0027] The first target chip calculates the average of the number of processing boards it manages and the number of processing boards managed by the second target chip, and selects a target processing board based on the number of processing boards it manages and the average value.

[0028] The first target chip sends the target slot number and device information of the target processing board to the second target chip;

[0029] The second target chip sends a takeover request to the target processing board based on the target slot number and device information. The takeover request includes the second IP.

[0030] In an optional implementation, if a fault control chip is identified, the processing board managed by the fault control chip is transferred to a normal control chip, including:

[0031] The first control chip and the second control chip share a processing board management list, which includes the master control chip, the slot number, and the processing board device information.

[0032] The first control chip and the second control chip exchange heartbeat signals;

[0033] If the first control chip does not receive a heartbeat signal from the second control chip within a specified period, the second control chip is deemed to be faulty.

[0034] The first control chip selects the processing board whose master chip is the second control chip from the processing board management list as the target object, and reads the slot number and processing board device information of the target object.

[0035] The first control chip sends a takeover request to the target object based on the target object's slot number and processing board device information, and takes over the target object's business after the request is approved.

[0036] Thirdly, the present invention also provides a multi-data channel management system, comprising:

[0037] The task monitoring module is used by each control chip to monitor the number of pending tasks in its own task queue.

[0038] The target negotiation module is used by the control chips to negotiate the first target chip with the largest number of tasks to be processed and the second target chip with the smallest number of tasks to be processed.

[0039] The service transfer module is used to transfer the processing board managed by the first target chip to the second target chip;

[0040] The fault handling module is used to confirm the existence of a faulty control chip and transfer the processing board managed by the faulty control chip to the normal control chip.

[0041] In one optional implementation, the task monitoring module includes:

[0042] A queue creation unit is used to create a task queue in the control chip, the task queue being used to cache and process service requests from the processing board.

[0043] The quantity monitoring unit is used to create monitoring threads, which periodically collect the number of tasks in the task queue.

[0044] In one optional implementation, the target negotiation module includes:

[0045] The list generation unit is used to control the chip to save the number of tasks to be processed and the IP address to the negotiation list, and to mark the negotiation list and send it to the next control chip that does not have a corresponding mark, until all control chips are traversed.

[0046] The target filtering unit is used by the control chip that last received the negotiation list to filter out the first IP of the first target chip corresponding to the maximum number of pending tasks and the second IP of the second target chip corresponding to the minimum number of pending tasks from the negotiation list.

[0047] The first notification unit is used to send a first notification message to a first IP address, the first notification message including instructions for transferring the processing board and a second IP address;

[0048] The second notification unit is used to send a second notification message to a second IP address. The second notification message includes instructions for receiving the processing board and the first IP address.

[0049] In one optional implementation, the service transfer module includes:

[0050] The dialogue establishment unit is used for the first target chip and the second target chip to establish a dialogue based on the first notification information and the second notification information. The second target chip sends the number of processing boards it manages to the first target chip through the dialogue.

[0051] The board selection unit is used to calculate the average number of processing boards managed by the first target chip and the number of processing boards managed by the second target chip, and select a target processing board based on the number of processing boards managed by itself and the average number.

[0052] The information transmission unit is used by the first target chip to send the target slot number and device information of the target processing board to the second target chip.

[0053] The request sending unit is used for the second target chip to send a takeover request to the target processing board based on the target slot number and device information, wherein the takeover request includes the second IP.

[0054] In one optional implementation, the fault handling module includes:

[0055] An information sharing unit is used for the first control chip and the second control chip to share a processing board management list, wherein the processing board management list includes the master control chip to which it belongs, the slot number to which it belongs, and the processing board device information.

[0056] The heartbeat monitoring unit is used to enable the first control chip and the second control chip to exchange heartbeat signals.

[0057] The fault confirmation unit is used to determine that the second control chip is faulty if the first control chip does not receive the heartbeat signal from the second control chip within a specified period.

[0058] The object determination unit is used by the first control chip to filter out the processing board whose master chip is the second control chip from the processing board management list as the target object, and to read the slot number and processing board device information of the target object.

[0059] The service takeover unit is used by the first control chip to send a takeover request to the target object based on the target object's slot number and processing board device information, and to take over the target object's services after the request is approved.

[0060] Fourthly, a terminal is provided, comprising:

[0061] Processor, memory, among which,

[0062] This memory is used to store computer programs.

[0063] The processor is used to retrieve and run the computer program from memory, causing the terminal to perform the terminal method described above.

[0064] Fifthly, a computer storage medium is provided, wherein instructions are stored therein, which, when executed on a computer, cause the computer to perform the methods described in the above aspects.

[0065] The beneficial effects of this invention are as follows: The multi-data-channel backplane provided by this invention features dual network switch chips on the backplane for connecting and networking various processing boards to provide network communication functionality. In addition, it includes a PCIe Switch chip and CPU for communication between PCIe slave devices, and a USB hub chip and CPU for forwarding data between USB slave devices. From the perspective of pluggable modules, all slots share the same communication link. For interfaces with master-slave relationships (USB and PCIe), this solution places the master device on the backplane, ensuring that all slave devices in the slot are slave devices. This means that the number of modules can be quickly expanded from one to N depending on the application. For communication, there are three different communication links, which are independent of each other and can serve as backups for each other. Compared to backups of the same link, due to different implementation mechanisms and designs, the probability of simultaneous failure due to the same interference factor is reduced. More importantly, for commonly used processing board modules, general-purpose AI processors come with three interfaces by default, reducing the complexity of the processing board (by placing the complexity on the backplane). This approach becomes increasingly advantageous as the number of processing boards increases, allowing for flexible implementation of multiple backups or N+1 redundancy backups. Regarding development workload, once the initial backplane development is complete, the communication mechanism of the boards allows for rapid replication after development of one board, similar to a distributed architecture, without needing to consider changes in master-slave relationships and communication mechanisms between multiple boards.

[0066] The multi-data channel management method and system provided by this invention considers load balancing between different CPU services, realizes the switching of slave processing boards, achieves automatic service adjustment and fault handling, and improves control stability.

[0067] Furthermore, the design principle of this invention is reliable, the structure is simple, and it has a very wide range of application prospects. Attached Figure Description

[0068] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0069] Figure 1 This is a schematic architecture diagram of a multi-data-channel backplane according to an embodiment of the present invention.

[0070] Figure 2 This is an example diagram of the processing board interface according to an embodiment of the present invention.

[0071] Figure 3 This is a schematic flowchart of a method according to an embodiment of the present invention.

[0072] Figure 4 This is a schematic block diagram of a system according to an embodiment of the present invention.

[0073] Figure 5 This is a schematic diagram of the structure of a terminal provided in an embodiment of the present invention. Detailed Implementation

[0074] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0075] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0076] like Figure 1 As shown, the multi-data-channel backplane includes the following structure:

[0077] Multiple control chips and multiple network switch chips; the multiple control chips are connected to multiple slots through their respective corresponding communication chips; the multiple network switch chips are connected to multiple slots; the multiple slots are respectively plugged into external processing boards.

[0078] To improve the link independence and overall stability of different control chips, multiple control chips are used, including a first control chip and a second control chip. The first control chip acts as a PCIe master device and is connected to a PCIe conversion chip. The PCIe conversion chip is connected to multiple slots, and the processing board inserted into the slots acts as a PCIe slave device. The second control chip is connected to a USB interface chip, which is connected to multiple slots.

[0079] Specifically, the multi-data-channel backplane is equipped with dual network switch chips, forming two sets of network interfaces, which connect to each processing board respectively, enabling networking between the processing boards. It should be noted that there can be one or more switch chips, depending on the actual application requirements. The more chips there are, the more redundancy and the higher the reliability.

[0080] It is equipped with a PCIe switch chip and a CPU. The CPU acts as a PCIe master device, and its main function is to configure the PCIe switch chip to enable communication between PCIe slave devices.

[0081] It is equipped with a USB hub chip and a CPU. The CPU acts as the USB master device, handling data forwarding between USB slave devices. It's important to note that the CPUs related to the USB interface and the PCIe interface are different, using CPUs from different manufacturers. Due to their different architectures, the overall CPU hardware architecture differs, which helps avoid simultaneous failures caused by the same CPU or hardware design flaws, thus increasing system reliability.

[0082] Processing board interfaces such as Figure 2 As shown, each processing board has two network ports, one PCIe interface, and one USB interface for connecting to the backplane. It's important to emphasize that the communication interfaces of each processing board are identical, and the slots A, B, C, etc., on the backplane are also identical. This allows each processing board to be inserted into any backplane interface. The advantage of this design is a unified interface, facilitating expansion. If different processing boards are added, they can be inserted into any backplane as long as the interfaces remain the same.

[0083] The following is a specific example of a multi-data-channel backplane. The RTL8309N is an 8-port switch network chip from RELTEK, used to form a gigabit Ethernet network. It connects to four ORIN modules through network signals on the slots to form a local area network inside the device for communication.

[0084] The PM50068 is a PCIe switch chip from Microchip Technology, providing a PCIe Gen4 x16 data interface for each slot. It works in conjunction with the RK3568 to connect and communicate with various PCIe devices. The RK3568 is an ARM CPU from Rising Microelectronics, including a PCIe controller and a quad-core ARM A55 core.

[0085] The TUSB8041 is a 4-port USB hub from TI, while the RK3358 is an ARM CPU from Rockchip. It has a USB interface and can connect up to 4 USB devices via a USB hub.

[0086] The Orin module is a type of NVIDIA Jetson AGX ORIN Series, including AI modules with computing power ranging from 200 TOPS to 275 TOPS. It has external ports such as USB, PCIe, and Gigabit Ethernet, which can be connected to the back panel slot.

[0087] In addition, communication is established between the two CPUs, and the communication link is selected from the UPI bus.

[0088] This multi-channel backplane features dual network switch chips for connecting and networking various processing boards to provide network communication capabilities. Additionally, it includes a PCIe switch chip and CPU for communication between PCIe slave devices, and a USB hub chip and CPU for forwarding data between USB slave devices.

[0089] Regarding the number of switch chips, one or more can be selected based on actual application requirements. The more chips there are, the higher the redundancy and reliability. The configuration can be selected according to specific system requirements.

[0090] It is important to note that the CPUs associated with USB interfaces and the CPUs associated with PCIe interfaces are different. Using CPUs from different manufacturers and different hardware architectures can reduce the risk of simultaneous system failures due to the same hardware malfunction, thereby increasing the overall system reliability.

[0091] The multi-data channel management method provided in this embodiment of the invention is executed by a computer device, and correspondingly, the multi-data channel management system runs on the computer device.

[0092] Figure 3 This is a schematic flowchart illustrating a method according to an embodiment of the present invention. Wherein, Figure 3 The executing entity can be a multi-data-channel management system. Depending on different needs, the order of the steps in this flowchart can be changed, and some can be omitted.

[0093] like Figure 3 As shown, the method includes:

[0094] Step 310: Each control chip monitors the number of pending tasks in its own task queue.

[0095] Step 320: Each control chip negotiates to determine the first target chip with the largest number of tasks to be processed and the second target chip with the smallest number of tasks to be processed.

[0096] Step 330: Transfer the processing board managed by the first target chip to the second target chip;

[0097] Step 340: Confirm the existence of a faulty control chip, and transfer the processing board managed by the faulty control chip to the normal control chip.

[0098] To facilitate understanding of the present invention, the following description further illustrates the multi-data channel management method provided by the present invention, based on the principle of the multi-data channel management method and the process of managing multiple data channels in the embodiments.

[0099] Specifically, the multi-data channel management method includes:

[0100] S1. Each control chip monitors the number of pending tasks in its own task queue.

[0101] A task queue is created in the control chip to cache and process the service requests of the board; a monitoring thread is created to periodically collect the number of tasks in the task queue.

[0102] The tasks of the control chip are quantified using a task queue approach.

[0103] S2. Each control chip negotiates to determine the first target chip with the largest number of tasks to be processed and the second target chip with the smallest number of tasks to be processed.

[0104] Specifically, the control chip saves its number of pending tasks and IP addresses to a negotiation list, marks the negotiation list, and sends it to the next control chip without a corresponding mark, until all control chips have been traversed. Finally, the control chip that receives the negotiation list selects the first IP address of the first target chip corresponding to the largest number of pending tasks and the second IP address of the second target chip corresponding to the smallest number of pending tasks from the negotiation list; sends a first notification message to the first IP address, which includes an instruction to transfer the processing board and the second IP address; and sends a second notification message to the second IP address, which includes an instruction to receive the processing board and the first IP address.

[0105] S3. Transfer the processing board managed by the first target chip to the second target chip.

[0106] Specifically, the first target chip and the second target chip establish a dialogue based on the first and second notification information. The second target chip sends the number of processing boards it manages to the first target chip through the dialogue. The first target chip calculates the average of the number of processing boards it manages and the number of processing boards managed by the second target chip, and selects a target processing board based on its own number of managed processing boards and the average value. The first target chip sends the target slot number and device information of the target processing board to the second target chip. The second target chip sends a takeover request to the target processing board based on the target slot number and device information. The takeover request includes a second IP address. After receiving the takeover request, the target processing board returns a notification message indicating that the request has been approved to the second target chip and sends subsequent service data to the second target chip.

[0107] S4. Confirm the existence of a faulty control chip and transfer the processing board managed by the faulty control chip to the normal control chip.

[0108] The first control chip and the second control chip share a processing board management list, which includes the master control chip, the slot number, and the processing board device information. The first and second control chips exchange heartbeat signals. If the first control chip does not receive a heartbeat signal from the second control chip within a specified period, the second control chip is deemed faulty. The first control chip selects the processing board whose master chip is the second control chip from the processing board management list as the target object, and reads the slot number and processing board device information of the target object. Based on the slot number and processing board device information of the target object, the first control chip sends a takeover request to the target object, and takes over the target object's services after the request is approved.

[0109] In some embodiments, the multi-data channel management system 400 may include multiple functional modules composed of computer program segments. The computer programs for each program segment in the multi-data channel management system 400 may be stored in the memory of a computer device and executed by at least one processor to perform (see details). Figure 1 (Description) Functionality of multi-data channel management.

[0110] In this embodiment, the multi-data channel management system 400 can be divided into multiple functional modules according to its functions, such as... Figure 4 As shown. The functional modules may include: a task monitoring module 410, a target negotiation module 420, a service transfer module 430, and a fault handling module 440. The module referred to in this invention is a series of computer program segments that can be executed by at least one processor and perform a fixed function, and are stored in memory. In this embodiment, the functions of each module will be described in detail in subsequent embodiments.

[0111] The task monitoring module is used by each control chip to monitor the number of pending tasks in its own task queue.

[0112] The target negotiation module is used by the control chips to negotiate the first target chip with the largest number of tasks to be processed and the second target chip with the smallest number of tasks to be processed.

[0113] The service transfer module is used to transfer the processing board managed by the first target chip to the second target chip;

[0114] The fault handling module is used to confirm the existence of a faulty control chip and transfer the processing board managed by the faulty control chip to the normal control chip.

[0115] Optionally, as an embodiment of the present invention, the task monitoring module includes:

[0116] A queue creation unit is used to create a task queue in the control chip, the task queue being used to cache and process service requests from the processing board.

[0117] The quantity monitoring unit is used to create monitoring threads, which periodically collect the number of tasks in the task queue.

[0118] Optionally, as an embodiment of the present invention, the target negotiation module includes:

[0119] The list generation unit is used to control the chip to save the number of tasks to be processed and the IP address to the negotiation list, and to mark the negotiation list and send it to the next control chip that does not have a corresponding mark, until all control chips are traversed.

[0120] The target filtering unit is used by the control chip that last received the negotiation list to filter out the first IP of the first target chip corresponding to the maximum number of pending tasks and the second IP of the second target chip corresponding to the minimum number of pending tasks from the negotiation list.

[0121] The first notification unit is used to send a first notification message to a first IP address, the first notification message including instructions for transferring the processing board and a second IP address;

[0122] The second notification unit is used to send a second notification message to a second IP address. The second notification message includes instructions for receiving the processing board and the first IP address.

[0123] Optionally, as an embodiment of the present invention, the service transfer module includes:

[0124] The dialogue establishment unit is used for the first target chip and the second target chip to establish a dialogue based on the first notification information and the second notification information. The second target chip sends the number of processing boards it manages to the first target chip through the dialogue.

[0125] The board selection unit is used to calculate the average number of processing boards managed by the first target chip and the number of processing boards managed by the second target chip, and select a target processing board based on the number of processing boards managed by itself and the average number.

[0126] The information transmission unit is used by the first target chip to send the target slot number and device information of the target processing board to the second target chip.

[0127] The request sending unit is used for the second target chip to send a takeover request to the target processing board based on the target slot number and device information, wherein the takeover request includes the second IP.

[0128] Optionally, as an embodiment of the present invention, the fault handling module includes:

[0129] An information sharing unit is used for the first control chip and the second control chip to share a processing board management list, wherein the processing board management list includes the master control chip to which it belongs, the slot number to which it belongs, and the processing board device information.

[0130] The heartbeat monitoring unit is used to enable the first control chip and the second control chip to exchange heartbeat signals.

[0131] The fault confirmation unit is used to determine that the second control chip is faulty if the first control chip does not receive the heartbeat signal from the second control chip within a specified period.

[0132] The object determination unit is used by the first control chip to filter out the processing board whose master chip is the second control chip from the processing board management list as the target object, and to read the slot number and processing board device information of the target object.

[0133] The service takeover unit is used by the first control chip to send a takeover request to the target object based on the target object's slot number and processing board device information, and to take over the target object's services after the request is approved.

[0134] Figure 5 This is a schematic diagram of the structure of a terminal 500 provided in an embodiment of the present invention. The terminal 500 can be used to execute the multi-data channel management method provided in the embodiment of the present invention.

[0135] The terminal 500 may include a processor 510, a memory 520, and a communication module 530. These components communicate via one or more buses. Those skilled in the art will understand that the server structure shown in the figure does not constitute a limitation of the present invention. It may be a bus topology or a star topology, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0136] The memory 520 can be used to store the execution instructions of the processor 510. The memory 520 can be implemented using any type of volatile or non-volatile storage terminal or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. When the execution instructions in the memory 520 are executed by the processor 510, the terminal 500 is able to perform some or all of the steps in the above method embodiments.

[0137] The processor 510 serves as the control center of the storage terminal, connecting various parts of the electronic terminal via various interfaces and lines. It executes software programs and / or modules stored in the memory 520, and calls data stored in the memory to perform various functions of the electronic terminal and / or process data. The processor can be composed of integrated circuits (ICs), such as a single packaged IC or multiple packaged ICs with the same or different functions connected together. For example, the processor 510 may consist only of a central processing unit (CPU). In this embodiment of the invention, the CPU may have a single processing core or include multiple processing cores.

[0138] The communication module 530 is used to establish a communication channel, enabling the storage terminal to communicate with other terminals. It receives user data sent by other terminals or sends user data to other terminals.

[0139] The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, which, when executed, may include some or all of the steps provided in the embodiments of the present invention. The storage medium may be a magnetic disk, an optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0140] Those skilled in the art will clearly understand that the techniques in the embodiments of the present invention can be implemented using software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, or any other medium capable of storing program code. It includes several instructions to cause a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0141] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the terminal embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.

[0142] In the embodiments provided by this invention, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between systems or modules may be electrical, mechanical, or other forms.

[0143] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0144] In addition, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0145] Although the present invention has been described in detail with reference to the accompanying drawings and preferred embodiments, the invention is not limited thereto. Various equivalent modifications or substitutions can be made to the embodiments of the invention by those skilled in the art without departing from the spirit and essence of the invention, and such modifications or substitutions should all be within the scope of the invention. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the invention should also be covered within the protection scope of the invention. Therefore, the protection scope of the invention should be determined by the scope of the claims.

Claims

1. A multi-data-channel backplane, characterized in that, include: Multiple control chips and multiple network switch chips, with the multiple network switch chips being dual network switch chips; Multiple control chips are connected to multiple slots through their respective communication chips; Multiple network switch chips are connected to multiple slots respectively; Multiple slots are respectively connected to external processing boards. Each slot has the same interface. Each processing board is provided with 2 network ports, 1 PCIe interface, and 1 USB interface for connecting to the backplane, so that the processing board can be inserted into any slot. The multiple control chips include a first control chip and a second control chip. The first control chip acts as a PCIe master device and is connected to a PCIe conversion chip. The PCIe conversion chip is connected to multiple slots, and the processing board inserted into the slots acts as a PCIe slave device. The second control chip is connected to a USB interface chip, which is connected to multiple slots; The first control chip and the second control chip are connected via a UPI bus, and both the first control chip and the second control chip are online at the same time. Each processing board is equipped with 2 network ports, 1 PCIe interface, and 1 USB interface for connecting to the backplane; The processing board communicates with the corresponding control chip through three independent communication links: network channel, PCIe channel and USB channel, and the three communication links serve as backups for each other.

2. A multi-data channel management method, based on the multi-data channel backplane of claim 1, characterized in that, include: Each control chip monitors the number of pending tasks in its own task queue; The control chips negotiate to determine the first target chip with the largest number of tasks to be processed and the second target chip with the smallest number of tasks to be processed. Transfer the processing board managed by the first target chip to the second target chip; If a faulty control chip is confirmed, the processing board managed by the faulty control chip will be transferred to the normal control chip.

3. The method according to claim 2, characterized in that, Each control chip monitors the number of pending tasks in its own task queue, including: A task queue is created in the control chip, which is used to cache and process the service requests of the board; Create a monitoring thread that periodically collects the number of tasks in the task queue.

4. The method according to claim 2, characterized in that, The control chips negotiate to determine the first target chip with the largest number of tasks to be processed and the second target chip with the smallest number of tasks to be processed, including: The control chip saves the number of tasks to be processed and the IP address to the negotiation list, and sends the negotiation list to the next control chip that does not have a corresponding mark, until all control chips have been traversed. Finally, the control chip that receives the negotiation list selects the first IP of the first target chip corresponding to the maximum number of pending tasks and the second IP of the second target chip corresponding to the minimum number of pending tasks from the negotiation list. Send a first notification message to the first IP address, the first notification message including instructions to transfer the processing board and the second IP address; Send a second notification message to the second IP address, the second notification message including instructions for receiving the processing board and the first IP address.

5. The method according to claim 4, characterized in that, Transferring the processing board managed by the first target chip to the second target chip includes: The first target chip and the second target chip establish a dialogue based on the first notification information and the second notification information. The second target chip sends the number of processing boards it manages to the first target chip through the dialogue. The first target chip calculates the average of the number of processing boards it manages and the number of processing boards managed by the second target chip, and selects a target processing board based on the number of processing boards it manages and the average value. The first target chip sends the target slot number and device information of the target processing board to the second target chip; The second target chip sends a takeover request to the target processing board based on the target slot number and device information. The takeover request includes the second IP.

6. The method according to claim 2, characterized in that, Once a faulty control chip is confirmed, the processing boards managed by the faulty control chip will be transferred to the normal control chip, including: The first control chip and the second control chip share a processing board management list, which includes the master control chip, the slot number, and the processing board device information. The first control chip and the second control chip exchange heartbeat signals; If the first control chip does not receive a heartbeat signal from the second control chip within a specified period, the second control chip is deemed to be faulty. The first control chip selects the processing board whose master chip is the second control chip from the processing board management list as the target object, and reads the slot number and processing board device information of the target object. The first control chip sends a takeover request to the target object based on the target object's slot number and processing board device information, and takes over the target object's business after the request is approved.

7. A multi-data-channel management system, based on the multi-data-channel backplane of claim 1, characterized in that, include: The task monitoring module is used by each control chip to monitor the number of pending tasks in its own task queue. The target negotiation module is used by the control chips to negotiate to determine the first target chip with the largest number of tasks to be processed and the second target chip with the smallest number of tasks to be processed. The service transfer module is used to transfer the processing board managed by the first target chip to the second target chip; The fault handling module is used to confirm the existence of a faulty control chip and transfer the processing board managed by the faulty control chip to the normal control chip.

8. The system according to claim 7, characterized in that, The target negotiation module includes: The list generation unit is used to control the chip to save the number of tasks to be processed and the IP address to the negotiation list, and then send the negotiation list to the next control chip that does not have a corresponding mark, until all control chips are traversed. The target filtering unit is used by the control chip that last received the negotiation list to filter out the first IP of the first target chip corresponding to the maximum number of pending tasks and the second IP of the second target chip corresponding to the minimum number of pending tasks from the negotiation list. The first notification unit is used to send a first notification message to a first IP address, the first notification message including instructions for transferring the processing board and a second IP address; The second notification unit is used to send a second notification message to a second IP address. The second notification message includes instructions for receiving the processing board and the first IP address.

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