Chip selection signal generation method and apparatus

Abstract

The embodiment of the present disclosure provides a chip selection signal generation method and device, relates to the technical field of semiconductors, and comprises the following steps: receiving an external control signal input from a chip selection port, and sampling the external control signal to obtain a first sampling signal and a second sampling signal; inputting the first sampling signal into a first vector file to generate a power supply control signal; inputting the second sampling signal into a second vector file to generate a chip selection control signal; generating a chip selection signal based on the power supply control signal and the chip selection control signal; wherein the forms of the power supply control signal and the chip selection control signal include a high potential, a low potential and a high impedance state, the voltage values of the high potentials of the power supply control signal and the chip selection control signal are different, and the voltage values of the low potentials of the power supply control signal and the chip selection control signal are different. The embodiment of the present disclosure realizes a chip selection signal with four different potentials by using the above two vector files.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a method and apparatus for generating a chip select (Cs) signal. Background Technology

[0002] With the development of semiconductor technology, the fifth generation of low power double data rate (LPDDR5) memory has been widely used in various electronic products.

[0003] Since the clock enable signal (CKE) pin has been removed in LPDDR5, the function of the clock enable signal has not been removed in essence. Therefore, the clock enable function needs to be implemented based on other signals or signal ports. Summary of the Invention

[0004] This disclosure provides a method and apparatus for generating a chip select signal, which can realize a CS signal with four different potentials, thereby simultaneously realizing the chip select function and the clock enable function.

[0005] In a first aspect, embodiments of this disclosure provide a method for generating a chip select signal, the method comprising:

[0006] Receive an external control signal input from the chip select port, and sample the external control signal to obtain a first sample signal and a second sample signal;

[0007] The first sampled signal is input into the first vector file to generate a power control signal;

[0008] The second sampling signal is input into the second vector file to generate a chip select control signal; wherein the power control signal and the chip select control signal are in the form of high potential, low potential and high impedance state, the voltage values ​​of the high potential of the power control signal and the chip select control signal are different, and the voltage values ​​of the low potential of the power control signal and the chip select control signal are different.

[0009] The chip select signal is generated based on the power control signal and the chip select control signal. The chip select signal is used to perform power control operations and chip select operations.

[0010] In one feasible implementation, the first vector file is used to simulate a first MOSFET and a second MOSFET, the first MOSFET and the second MOSFET being of different types. The drain of the first MOSFET is connected to a first high level, the source of the first MOSFET is connected to the drain of the second MOSFET as an output terminal, and the source of the second MOSFET is connected to a first low level. The step of inputting the first sampling signal into the first vector file to generate a power control signal includes:

[0011] The first sampling signal is input to the gate of the first MOSFET and the gate of the second MOSFET to turn on the first MOSFET or the second MOSFET and output the power control signal.

[0012] In one feasible implementation, the first MOS transistor is a PMOS transistor and the second MOS transistor is an NMOS transistor.

[0013] In one feasible implementation, the second vector file is used to simulate a third MOSFET and a fourth MOSFET, the third MOSFET and the fourth MOSFET being of different types. The drain of the third MOSFET is connected to a second high level, the source of the third MOSFET is connected to the drain of the fourth MOSFET as an output terminal, and the source of the fourth MOSFET is connected to a second low level. The step of inputting the second sampling signal into the second vector file to generate a chip select control signal includes:

[0014] The second sampling signal is input to the gate of the third MOS transistor and the gate of the fourth MOS transistor to turn on the third MOS transistor or the fourth MOS transistor and output the chip select control signal.

[0015] In one feasible implementation, the third MOS transistor is a PMOS transistor, and the fourth MOS transistor is an NMOS transistor.

[0016] In one feasible implementation, the voltage value of the first high level is greater than the voltage value of the second high level, and the voltage value of the first low level is less than the voltage value of the second low level.

[0017] In one feasible implementation, the first vector file is used to simulate a first MOSFET and a second MOSFET, the first MOSFET and the second MOSFET being of the same type, the drain of the first MOSFET being connected to a first high level, the source of the first MOSFET being connected to the drain of the second MOSFET as an output terminal, and the source of the second MOSFET being connected to a first low level; the step of inputting the first sampling signal into the first vector file to generate a power control signal includes:

[0018] The first sampling signal is input to the gate of the first MOSFET, and the inverted signal of the first sampling signal is input to the gate of the second MOSFET, so as to turn on the first MOSFET or the second MOSFET and output the power control signal.

[0019] In one feasible implementation, after generating the chip select signal based on the power control signal and the chip select control signal, the method further includes:

[0020] The chip select signal is sampled to obtain the power control signal and the chip select control signal.

[0021] In one feasible implementation, after sampling the chip select signal to obtain the power control signal and the chip select control signal, the method further includes:

[0022] The power control signal is input to a preset power supply circuit so that the power supply circuit outputs an excitation signal or a shutdown signal based on the power control signal. The excitation signal is used to enable a preset storage circuit, and the shutdown signal is used to shut down the storage circuit.

[0023] And input the chip select control signal to the memory circuit so that the enabled memory circuit performs a chip select operation based on the chip select control signal.

[0024] Secondly, embodiments of this disclosure provide an apparatus for generating a chip select signal, the apparatus comprising:

[0025] The first sampling module is used to receive external control signals input from the chip select port, and sample the external control signals to obtain a first sampling signal and a second sampling signal;

[0026] A first vector file is used to receive the first sampled signal and output a corresponding power control signal based on the first sampled signal;

[0027] The second vector file is used to receive the second sampling signal and output the corresponding chip select control signal based on the second sampling signal;

[0028] The power control signal and the chip select control signal are in the form of high potential, low potential and high impedance state. The voltage values ​​of the high potential of the power control signal and the chip select control signal are different, and the voltage values ​​of the low potential of the power control signal and the chip select control signal are different.

[0029] The processing module is used to generate the chip select signal based on the power control signal and the chip select control signal, and the chip select signal is used to perform power control operation and chip select operation.

[0030] In one feasible implementation, the first vector file is used to simulate a first MOS transistor and a second MOS transistor, the first MOS transistor and the second MOS transistor are of different types, the drain of the first MOS transistor is connected to a first high level, the source of the first MOS transistor is connected to the drain of the second MOS transistor as an output terminal, and the source of the second MOS transistor is connected to a first low level.

[0031] The gates of the first MOS transistor and the second MOS transistor are used to receive the first sampling signal.

[0032] In one feasible implementation, the second vector file is used to simulate a third MOS transistor and a fourth MOS transistor of different types. The drain of the third MOS transistor is connected to a second high level, the source of the third MOS transistor is connected to the drain of the fourth MOS transistor as an output terminal, and the source of the fourth MOS transistor is connected to a second low level.

[0033] The gates of the third MOS transistor and the fourth MOS transistor are used to receive the second sampling signal.

[0034] In one feasible implementation, the voltage value of the first high level is greater than the voltage value of the second high level, and the voltage value of the first low level is less than the voltage value of the second low level.

[0035] In one feasible implementation, a second sampling module is also included, for:

[0036] The chip select signal is sampled to obtain the power control signal and the chip select control signal.

[0037] Thirdly, embodiments of this disclosure provide an electronic device, including: at least one processor and a memory;

[0038] The memory stores computer-executed instructions;

[0039] The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the chip select signal generation method as provided in the first aspect.

[0040] Fourthly, embodiments of this disclosure provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the chip select signal generation method provided in the first aspect.

[0041] The chip select signal generation method and apparatus provided in this disclosure include: obtaining a first sampling signal and a second sampling signal by sampling an external control signal; inputting the first sampling signal into a first vector file to generate a power control signal; inputting the second sampling signal into a second vector file to generate a chip select control signal; and generating a chip select signal based on the power control signal and the chip select control signal. The high-potential voltage values ​​of the power control signal and the chip select control signal are different, and the low-potential voltage values ​​of the power control signal and the chip select control signal are different. Therefore, the two vector files can be used to implement a chip select signal with four different potentials, where two potentials are used to implement the chip select function, and the other two potentials are used to implement the clock enable function. Attached Figure Description

[0042] Figure 1 This is a flowchart illustrating the steps of a chip select signal generation method provided in an embodiment of this disclosure;

[0043] Figure 2 This is a schematic diagram of a chip select signal generated in an embodiment of this disclosure;

[0044] Figure 3 This is a schematic diagram of a signal processing circuit simulated by a first vector file and a second vector file, provided in an embodiment of this disclosure.

[0045] Figure 4 This is a schematic diagram of another signal processing circuit simulated by a first vector file and a second vector file, provided in an embodiment of this disclosure;

[0046] Figure 5 This is a schematic diagram of the program modules of a chip select signal generation device provided in an embodiment of this disclosure;

[0047] Figure 6 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. Furthermore, although the disclosure in this disclosure is based on one or several exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete implementation method on its own.

[0049] It should be noted that the brief descriptions of terms in this disclosure are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this disclosure. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.

[0050] The terms "first," "second," etc., used in this disclosure, the specification, claims, and the accompanying drawings are used to distinguish similar or related objects or entities and do not necessarily imply a specific order or sequence, unless otherwise specified. It should be understood that such terms can be used interchangeably where appropriate, for example, in situations where implementation can proceed in an order other than those given in the illustrations or description of embodiments of this disclosure.

[0051] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover but not exclusively include, for example, a product or device that includes a series of components is not necessarily limited to those that are explicitly listed, but may include other components that are not explicitly listed or that are inherent to such product or device.

[0052] The term "module" as used in the embodiments of this disclosure refers to any known or subsequently developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code capable of performing the functions associated with that element.

[0053] The embodiments disclosed herein can be applied to the field of semiconductor technology, such as for generating Cs signals in memory.

[0054] In the field of semiconductor technology, the Cs signal generally refers to the signal used when selecting one or a specific integrated circuit chip. This selection is necessary because when many chips are connected to the same bus, sometimes it's necessary to independently transmit data, addresses, or commands to a specific chip. In this case, the Cs signal is needed to tell the chips connected to the bus which chip receives this data or address. In this way, other chips will not respond to these signals, while the target chip knows that the data is intended for it and can then react.

[0055] Chip select is used not only when there are multiple chips in a circuit, but also when only one chip is used, in order to save power and extend chip life. For example, the Cs signal is used to make the chip work only when it needs to be used, and if there is no action within a specified time, the chip select signal is automatically deactivated, putting it into a low-power (powerdown) mode.

[0056] LPDDR5 typically includes the following pins:

[0057] CK_t / CK_c: Address / command clock, sampled simultaneously on rising and falling edges, differential clock input;

[0058] CS: Chip Select signal, sampled on the rising (falling) edge of the clock, used to select the target chip;

[0059] CA[6:0]: Command / address input;

[0060] DQ[15:0]: Data input / output bus;

[0061] WCK[1:0]_t / WCK[1:0]_c: Write clock, for differential input;

[0062] RDQS[1:0]_t / RDQS[1:0]_c: Read strobe signal (read clock), differential output;

[0063] The DMI[1:0] data bus is flipped, with each byte of data followed by one bit of DMI.

[0064] Compared to LPDDR4, LPDDR5 removed the clock enable (CKE) pin. This means that for the Cs pin to exit power-down mode, in addition to its chip select function, four different voltage levels are required to implement the Cs signal. However, how to implement a Cs signal with four different voltage levels is a problem that urgently needs to be solved.

[0065] To address the aforementioned technical problems, this disclosure provides a method for generating a chip select signal, which can utilize two vector files to achieve a chip select signal with four different potentials. For detailed implementation methods, please refer to the following embodiments.

[0066] Reference Figure 1 , Figure 1 This is a flowchart illustrating the steps of a method for generating a chip select signal according to an embodiment of this disclosure. In some embodiments of this disclosure, the method for generating the chip select signal includes:

[0067] S101. Receive the external control signal input from the chip select port, and sample the external control signal to obtain the first sample signal and the second sample signal.

[0068] The chip select port mentioned above can be the Cs pin.

[0069] In some embodiments, when an external control signal is received from the chip select port, the external control signal is sampled at a preset sampling frequency to obtain a first sampling signal and a second sampling signal.

[0070] S102. Input the first sampling signal into the first vector file to generate a power control signal.

[0071] After the first sampling signal is input into the first vector file, the first vector file can generate a power control signal based on the first sampling signal. The power control signal can include states such as high potential, low potential, high impedance state and indeterminate state.

[0072] The high-impedance state is neither a high level nor a low level. Its extreme state can be considered as floating (open circuit). When the high-impedance state is input to the next stage circuit, it has no effect on the next stage circuit, just like it is not connected.

[0073] An indeterminate state refers to a voltage output at a pin that is between a high potential and a low potential, and the voltage level is in an uncertain state.

[0074] For example, the first sampling signal can be composed of two level signals. When these two level signals are 0 and 0 respectively, the first vector file output is a high level; when these two level signals are 1 and 1 respectively, the first vector file output is a low level; when these two level signals are 1 and 0 respectively, the first vector file output is a high impedance state; and when these two level signals are 0 and 1 respectively, the first vector file output is an indeterminate state. Here, 0 represents a low level and 1 represents a high level.

[0075] In some embodiments, the power control signal is used to perform power control operations, such as controlling the chip to exit power down mode or enter working state, that is, to realize the function of the clock enable signal.

[0076] S103. Input the second sampling signal into the second vector file to generate the chip select control signal.

[0077] After the second sampling signal is input into the second vector file, the second vector file can generate a chip select control signal based on the second sampling signal. The chip select control signal can include states such as high potential, low potential, high impedance state and indeterminate state.

[0078] For example, the second sampling signal can also consist of two level signals. When these two level signals are 0 and 0 respectively, the second vector file output is a high level; when these two level signals are 1 and 1 respectively, the second vector file output is a low level; when these two level signals are 1 and 0 respectively, the second vector file output is a high impedance state; and when these two level signals are 0 and 1 respectively, the second vector file output is an indeterminate state. Here, 0 represents a low level and 1 represents a high level.

[0079] In some embodiments, the chip select control signal described above is used to perform chip select operations.

[0080] In some embodiments, the high-potential voltage values ​​of the power control signal and the chip select control signal are different, and the low-potential voltage values ​​of the power control signal and the chip select control signal are also different.

[0081] In some embodiments, when the power control signal is at a high or low potential, the chip select control signal is in a high impedance state; when the chip select control signal is at a high or low potential, the power control signal is in a high impedance state.

[0082] In some embodiments, both the first vector file and the second vector file described above can be Vector files.

[0083] S104. Generate chip select signal based on power control signal and chip select control signal.

[0084] In some embodiments, after generating the power control signal and the chip select control signal, the power control signal and the chip select control signal can be combined into a chip select signal.

[0085] For example, suppose the high potential voltage value of the power control signal is H1 and the low potential voltage value is L1; the high potential voltage value of the chip select control signal is H2 (H1≠H2) and the low potential voltage value is L2 (L1≠L2). Since the chip select control signal is in a high-impedance state when the power control signal is high or low, and vice versa, the chip select signal generated based on the power control signal and the chip select control signal can have four different potentials: H1, H2, L1, and L2.

[0086] To better understand the embodiments of this disclosure, please refer to... Figure 2 , Figure 2 This is a schematic diagram of a chip select signal generated in an embodiment of this disclosure.

[0087] In some embodiments, since the chip select signal has four different potentials, power control operation and chip select operation can be performed using the chip select signal. Specifically, chip select operation is performed first, followed by power control operation.

[0088] The chip select signal generation method provided in this embodiment of the present disclosure obtains a first sampling signal and a second sampling signal by sampling an external control signal; inputs the first sampling signal into a first vector file to generate a power control signal; inputs the second sampling signal into a second vector file to generate a chip select control signal; and generates a chip select signal based on the power control signal and the chip select control signal. The high-potential voltage values ​​of the power control signal and the chip select control signal are different, and the low-potential voltage values ​​of the power control signal and the chip select control signal are different, thereby enabling the generation of a chip select signal with four different potentials using the two vector files.

[0089] Based on the content described in the above embodiments, in some embodiments, the first vector file and the second vector file can be used to simulate a signal processing circuit composed of some specific semiconductor devices, which can generate the chip select signal based on the first sampling signal and the second sampling signal.

[0090] To better understand the embodiments of this disclosure, please refer to... Figure 3 , Figure 3 This is a schematic diagram of a signal processing circuit simulated by a first vector file and a second vector file, provided in an embodiment of this disclosure.

[0091] In some embodiments of this disclosure, the first vector file described above is used to simulate a first MOSFET P1 and a second MOSFET N1. The first MOSFET P1 and the second MOSFET N1 are of different types.

[0092] Optionally, the first MOSFET P1 can be a PMOS transistor, and the second MOSFET N1 can be an NMOS transistor.

[0093] In some embodiments, the source of the first MOSFET P1 is connected to the first high level H1, and the drain is connected to the drain of the second MOSFET N1 to serve as the output terminal Ao. The source of the second MOSFET N1 is connected to the first low level L1.

[0094] In some embodiments, after obtaining the first sampling signal, the first sampling signal is input to the gate Ap of the first MOSFET P1 and the gate An of the second MOSFET N1 to turn on the first MOSFET or the second MOSFET, and the signal output from the output terminal Ao is used as the power control signal. It can be understood that inputting the first sampling signal to the gate Ap of the first MOSFET P1 and the gate An of the second MOSFET N1 means that after obtaining the first sampling signal, the first sampling signal is sampled again to obtain a first signal and a second signal. The first signal is input to the gate Ap of the first MOSFET P1, and the second signal is input to the gate An of the second MOSFET N1 to generate the power control signal.

[0095] For example, when the first MOSFET P1 is a PMOS transistor and the second MOSFET N1 is an NMOS transistor, based on the working principles of PMOS and NMOS transistors, we can know that:

[0096] When both the gate Ap of the first MOSFET P1 and the gate An of the second MOSFET N1 are input with a low level, the first MOSFET P1 is turned on and the second MOSFET N1 is turned off. At this time, the output terminal Ao outputs the first high level H1.

[0097] When both the gate Ap of the first MOSFET P1 and the gate An of the second MOSFET N1 are input with a high level, the first MOSFET P1 is turned off and the second MOSFET N1 is turned on. At this time, the output terminal Ao outputs the first low level L1.

[0098] When the gate Ap of the first MOSFET P1 is high and the gate An of the second MOSFET N1 is low, both the first MOSFET P1 and the second MOSFET N1 are cut off, and the output terminal Ao is in a high state.

[0099] When the gate Ap of the first MOSFET P1 is low and the gate An of the second MOSFET N1 is high, both the first MOSFET P1 and the second MOSFET N1 are turned on, and the output terminal Ao is in an undetermined state.

[0100] In some embodiments of this disclosure, the aforementioned second vector file is used to simulate a third MOS transistor P2 and a fourth MOS transistor N2. The third MOS transistor and the fourth MOS transistor are of different types.

[0101] Optionally, the third MOSFET P2 can be a PMOS transistor, and the fourth MOSFET N2 can be an NMOS transistor.

[0102] In some embodiments, the drain of the third MOSFET P2 is connected to the second high level H2, and the source is connected to the drain of the fourth MOSFET N2 to serve as the output terminal Bo. The source of the fourth MOSFET N2 is connected to the second low level L2.

[0103] In some embodiments, after obtaining the second sampling signal, the second sampling signal is input to the gate Bp of the third MOSFET P2 and the gate Bn of the fourth MOSFET N2 to turn on the third MOSFET P2 or the fourth MOSFET N2, and the signal output from the output terminal Bo is used as the chip select control signal. It can be understood that inputting the second sampling signal to the gate Bp of the third MOSFET P2 and the gate Bn of the fourth MOSFET N2 means that after obtaining the second sampling signal, it is sampled again to obtain a third signal and a fourth signal. The third signal is input to the gate Bp of the third MOSFET P2, and the second signal is input to the gate Bn of the fourth MOSFET N2 to generate the chip select control signal.

[0104] For example, when the third MOSFET P2 is a PMOS transistor and the fourth MOSFET N2 is an NMOS transistor, based on the working principles of PMOS and NMOS transistors, we can know that:

[0105] When both the gate Bp of the third MOSFET P2 and the gate Bn of the fourth MOSFET N2 are input with a low level, the third MOSFET P2 is turned on and the fourth MOSFET N2 is turned off. At this time, the output terminal Bo outputs the second high level H2.

[0106] When both the gate Bp of the third MOSFET P2 and the gate Bn of the fourth MOSFET N2 are input with a high level, the third MOSFET P2 is turned off and the fourth MOSFET N2 is turned on. At this time, the output terminal Bo outputs the second low level L2.

[0107] When the gate Bp of the third MOSFET P2 is high and the gate Bn of the fourth MOSFET N2 is low, both the third MOSFET P2 and the fourth MOSFET N2 are cut off, and the output terminal Bo is in a high configuration.

[0108] When the gate Bp of the third MOSFET P2 is low and the gate Bn of the fourth MOSFET N2 is high, both the third MOSFET P2 and the fourth MOSFET N2 are turned on, and the output Bo is in an undetermined state.

[0109] In some embodiments, the first high level H1, the first low level L1, the second high level H2, and the second low level L2 are all different from each other.

[0110] In some embodiments, the voltage value of the first high level H1 is greater than the voltage value of the second high level H2; and the voltage value of the first low level L1 is less than the voltage value of the second low level L2.

[0111] In some embodiments, when the power control signal is a first high level H1 or a first low level L1, the chip select control signal is in a high impedance state; when the chip select control signal is a second high level H2 or a second low level L2, the power control signal is in a high impedance state.

[0112] In some embodiments, output terminal Ao is connected to output terminal Bo to serve as the chip select signal output terminal Y. It is understood that, in order to ensure that the power control signal and chip select control signal in the chip select signal can be identified, the power control signal and chip select control signal should be output sequentially according to actual needs, for example, the chip select control signal is output first and the power control signal is output later, so as to ensure that the synthesized chip select signal contains identifiable power control signal and chip select control signal.

[0113] To better understand the embodiments of this disclosure, refer to Table 1, which is a potential diagram of each of the above ports.

[0114] Table 1: Potential Diagram of Each Port

[0115]

[0116]

[0117] Where 1 represents a high level, 0 represents a low level, and z represents a high configuration.

[0118] In some embodiments, the chip select signal output from the chip select signal output terminal Y can be sampled to obtain the power control signal and the chip select control signal mentioned above.

[0119] In some embodiments, after obtaining the power control signal and chip select control signal, the power control signal can be input to a preset power supply circuit, so that the power supply circuit outputs an excitation signal or a shutdown signal based on the power control signal. The excitation signal enables a preset memory circuit, and the shutdown signal shuts down the memory circuit; that is, the power control signal can perform power control operations. It should be noted that shutting down the memory circuit may mean completely disconnecting the memory circuit or controlling the memory circuit to enter a sleep state; the memory circuit in a sleep state still requires power.

[0120] In some embodiments, the chip select control signal can also be input to the memory circuit so that the enabled memory circuit performs a chip select operation based on the chip select control signal.

[0121] The chip select signal generation method provided in this embodiment uses the first vector file and the second vector file to simulate a signal processing circuit composed of some specific semiconductor devices. The signal processing circuit can generate a chip select signal with four different potentials based on the first sampling signal and the second sampling signal.

[0122] Based on the content described in the above embodiments, in some embodiments, reference is made to... Figure 4 , Figure 4 This is a schematic diagram of another signal processing circuit simulated by a first vector file and a second vector file, provided in an embodiment of this disclosure.

[0123] In some embodiments of this disclosure, the first vector file described above is used to simulate a first MOS transistor M1 and a second MOS transistor M2. The first MOS transistor M1 and the second MOS transistor M2 are of the same type.

[0124] In some embodiments, the first MOS transistor M1 and the second MOS transistor M2 can both be PMOS transistors.

[0125] In some embodiments, the first MOS transistor M1 and the second MOS transistor M2 can both be NMOS transistors.

[0126] In some embodiments, the source of the first MOSFET M1 is connected to the first high level H1, and the drain is connected to the drain of the second MOSFET M2 to serve as the output terminal Ao. The source of the second MOSFET M2 is connected to the first low level L1.

[0127] In this circuit, the gate of the second MOS transistor M2 is connected to the inverter D1.

[0128] In some embodiments, after obtaining the first sampling signal, the first sampling signal is input to the gate Ap of the first MOS transistor M1, and after inputting the first sampling signal to the inverter D1, the inverted signal of the first sampling signal output by the inverter D1 is input to the gate An of the second MOS transistor M2 to turn on the first MOS transistor M1 or the second MOS transistor M2, and the signal output from the output terminal Ao is used as the power control signal mentioned above.

[0129] The chip select signal generation method provided in this embodiment simulates two different circuit structures using a first vector file and a second vector file respectively. A first sampling signal is input into the first vector file to generate a power control signal; a second sampling signal is input into the second vector file to generate a chip select control signal; and a chip select signal is generated based on the power control signal and the chip select control signal. Since the high potential voltage values ​​of the power control signal and the chip select control signal are different, and the low potential voltage values ​​of the power control signal and the chip select control signal are different, a chip select signal with four different potentials can be realized using the two vector files.

[0130] Based on the content described in the above embodiments, this disclosure also provides a chip select signal generation apparatus. (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of a program module for a chip select signal generation apparatus provided in an embodiment of the present disclosure. The chip select signal generation apparatus includes:

[0131] The first sampling module 501 is used to receive an external control signal input from the chip select port, and to sample the external control signal to obtain a first sampling signal and a second sampling signal.

[0132] The first vector file 502 is used to receive the first sampling signal and output a corresponding power control signal based on the first sampling signal.

[0133] The second vector file 503 is used to receive the second sampling signal and output a corresponding chip select control signal based on the second sampling signal.

[0134] The power control signal and the chip select control signal are in the form of high potential, low potential and high impedance state. The voltage values ​​of the high potential of the power control signal and the chip select control signal are different, and the voltage values ​​of the low potential of the power control signal and the chip select control signal are different.

[0135] The processing module 504 is used to generate the chip select signal based on the power control signal and the chip select control signal, and the chip select signal is used to perform power control operation and chip select operation.

[0136] In one feasible implementation, the first vector file 502 is used to simulate a first MOS transistor and a second MOS transistor, the first MOS transistor and the second MOS transistor are of different types, the drain of the first MOS transistor is connected to a first high level, the source of the first MOS transistor is connected to the drain of the second MOS transistor as an output terminal, and the source of the second MOS transistor is connected to a first low level.

[0137] The gates of the first MOS transistor and the second MOS transistor are used to receive the first sampling signal.

[0138] In one feasible implementation, the second vector file 503 is used to simulate a third MOS transistor and a fourth MOS transistor of different types. The drain of the third MOS transistor is connected to a second high level, the source of the third MOS transistor is connected to the drain of the fourth MOS transistor as an output terminal, and the source of the fourth MOS transistor is connected to a second low level.

[0139] The gates of the third MOS transistor and the fourth MOS transistor are used to receive the second sampling signal.

[0140] In one feasible implementation, the voltage value of the first high level is greater than the voltage value of the second high level, and the voltage value of the first low level is less than the voltage value of the second low level.

[0141] In one feasible implementation, the above-described apparatus further includes a second sampling module, used for:

[0142] The chip select signal is sampled to obtain the power control signal and the chip select control signal.

[0143] It should be noted that the specific execution of the first sampling module 501, the first vector file 502, the second vector file 503, and the processing module 504 in this embodiment can be found in the [reference needed]. Figures 1 to 4 The relevant content in the illustrated embodiments will not be repeated here.

[0144] Furthermore, based on the content described in the above embodiments, this disclosure also provides an electronic device, which includes at least one processor and a memory; wherein the memory stores computer execution instructions; the at least one processor executes the computer execution instructions stored in the memory to implement the various steps in the chip select signal generation method described in the above embodiments, which will not be repeated here.

[0145] To better understand the embodiments of this disclosure, please refer to... Figure 6 , Figure 6 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure.

[0146] like Figure 6 As shown, the electronic device 60 of this embodiment includes: a processor 601 and a memory 602; wherein:

[0147] Memory 602 is used to store instructions executed by the computer;

[0148] The processor 601 is used to execute computer execution instructions stored in the memory to implement the various steps in the chip select signal generation method described in the above embodiments, and for details, please refer to the relevant descriptions in the foregoing method embodiments.

[0149] Alternatively, the memory 602 can be either standalone or integrated with the processor 601.

[0150] When the memory 602 is set up independently, the device also includes a bus 603 for connecting the memory 602 and the processor 601.

[0151] Furthermore, based on the content described in the above embodiments, this disclosure also provides a computer-readable storage medium storing computer-executable instructions. When the processor executes the computer-executable instructions, it implements the various steps in the chip select signal generation method described in the above embodiments. This embodiment will not repeat the details here.

[0152] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0153] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0154] Furthermore, the functional modules in the various embodiments of this disclosure can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The unit integrating the above modules can be implemented in hardware or in the form of hardware plus software functional units.

[0155] The integrated modules implemented as software functional modules described above can be stored in a computer-readable storage medium. These software functional modules, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this disclosure.

[0156] It should be understood that the aforementioned processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in this disclosure can be directly manifested as execution by a hardware processor, or execution by a combination of hardware and software modules within the processor.

[0157] The memory may include high-speed RAM, and may also include non-volatile storage (NVM), such as at least one disk storage device, and may also be a USB flash drive, external hard drive, read-only memory, disk or optical disc, etc.

[0158] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0159] The aforementioned storage medium can be implemented from any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The storage medium can be any available medium accessible to general-purpose or special-purpose computers.

[0160] An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium can be an integral part of the processor. Both the processor and the storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and storage medium can exist as discrete components in an electronic device or host device.

[0161] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0162] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for generating a chip select signal, characterized in that, The method includes: Receive an external control signal input from the chip select port, and sample the external control signal to obtain a first sample signal and a second sample signal; The first sampled signal is input into a signal processing circuit simulated by a first vector file to generate a power control signal; The second sampling signal is input to a signal processing circuit simulated by a second vector file to generate a chip select control signal; wherein the power control signal and the chip select control signal are in the form of high potential, low potential and high impedance state, the voltage values ​​of the high potential of the power control signal and the chip select control signal are different, and the voltage values ​​of the low potential of the power control signal and the chip select control signal are different. The chip select signal is generated based on the power control signal and the chip select control signal. The chip select signal is used to perform power control operation and chip select operation. Specifically, when the power control signal is at a high or low potential, the chip select control signal is in a high-impedance state; when the chip select control signal is at a high or low potential, the power control signal is in a high-impedance state; the chip select control signal and the power control signal are output sequentially.

2. The method according to claim 1, characterized in that, The first vector file is used to simulate a first MOSFET and a second MOSFET. The first MOSFET and the second MOSFET are of different types. The drain of the first MOSFET is connected to a first high level, and the source of the first MOSFET is connected to the drain of the second MOSFET as an output terminal. The source of the second MOSFET is connected to a first low level. The step of inputting the first sampled signal into the signal processing circuit simulated by the first vector file to generate a power control signal includes: The first sampling signal is input to the gate of the first MOSFET and the gate of the second MOSFET to turn on the first MOSFET or the second MOSFET and output the power control signal.

3. The method according to claim 2, characterized in that, The first MOS transistor is a PMOS transistor, and the second MOS transistor is an NMOS transistor.

4. The method according to claim 2, characterized in that, The second vector file is used to simulate a third MOSFET and a fourth MOSFET, which are of different types. The drain of the third MOSFET is connected to a second high level, and the source of the third MOSFET is connected to the drain of the fourth MOSFET as an output terminal. The source of the fourth MOSFET is connected to a second low level. The step of inputting the second sampling signal into the signal processing circuit simulated by the second vector file to generate a chip select control signal includes: The second sampling signal is input to the gate of the third MOS transistor and the gate of the fourth MOS transistor to turn on the third MOS transistor or the fourth MOS transistor and output the chip select control signal.

5. The method according to claim 4, characterized in that, The third MOS transistor is a PMOS transistor, and the fourth MOS transistor is an NMOS transistor.

6. The method according to claim 4, characterized in that, The voltage value of the first high level is greater than the voltage value of the second high level, and the voltage value of the first low level is less than the voltage value of the second low level.

7. The method according to claim 1, characterized in that, The first vector file is used to simulate a first MOSFET and a second MOSFET. The first MOSFET and the second MOSFET are of the same type. The drain of the first MOSFET is connected to a first high level, and the source of the first MOSFET is connected to the drain of the second MOSFET as an output terminal. The source of the second MOSFET is connected to a first low level. The step of inputting the first sampled signal into the signal processing circuit simulated by the first vector file to generate a power control signal includes: The first sampling signal is input to the gate of the first MOSFET, and the inverted signal of the first sampling signal is input to the gate of the second MOSFET, so as to turn on the first MOSFET or the second MOSFET and output the power control signal.

8. The method according to claim 1, characterized in that, After generating the chip select signal based on the power control signal and the chip select control signal, the process further includes: The chip select signal is sampled to obtain the power control signal and the chip select control signal.

9. The method according to claim 8, characterized in that, After sampling the chip select signal to obtain the power control signal and the chip select control signal, the method further includes: The power control signal is input to a preset power supply circuit so that the power supply circuit outputs an excitation signal or a shutdown signal based on the power control signal. The excitation signal is used to enable a preset storage circuit, and the shutdown signal is used to shut down the storage circuit. And input the chip select control signal to the memory circuit so that the enabled memory circuit performs a chip select operation based on the chip select control signal.

10. A chip select signal generation apparatus, characterized in that, The device includes: The first sampling module is used to receive external control signals input from the chip select port, and sample the external control signals to obtain a first sampling signal and a second sampling signal; The first vector file, wherein the signal processing circuit simulated by the first vector file is used to receive the first sampled signal and output a corresponding power control signal based on the first sampled signal; The second vector file, which simulates a signal processing circuit, is used to receive the second sampled signal and output a corresponding chip select control signal based on the second sampled signal. The power control signal and the chip select control signal are in the form of high potential, low potential and high impedance state. The voltage values ​​of the high potential of the power control signal and the chip select control signal are different, and the voltage values ​​of the low potential of the power control signal and the chip select control signal are different. The processing module is configured to generate the chip select signal based on the power control signal and the chip select control signal, wherein the chip select signal is used to perform power control operation and chip select operation; Specifically, when the power control signal is at a high or low potential, the chip select control signal is in a high-impedance state; when the chip select control signal is at a high or low potential, the power control signal is in a high-impedance state; the chip select control signal and the power control signal are output sequentially.

11. The apparatus according to claim 10, characterized in that, The first vector file is used to simulate a first MOSFET and a second MOSFET. The first MOSFET and the second MOSFET are of different types. The drain of the first MOSFET is connected to a first high level, the source of the first MOSFET is connected to the drain of the second MOSFET as an output terminal, and the source of the second MOSFET is connected to a first low level. The gates of the first MOS transistor and the second MOS transistor are used to receive the first sampling signal.

12. The apparatus according to claim 11, characterized in that, The second vector file is used to simulate a third MOS transistor and a fourth MOS transistor. The third MOS transistor and the fourth MOS transistor are of different types. The drain of the third MOS transistor is connected to a second high level, and the source of the third MOS transistor is connected to the drain of the fourth MOS transistor as an output terminal. The source of the fourth MOS transistor is connected to a second low level. The gates of the third MOS transistor and the fourth MOS transistor are used to receive the second sampling signal.

13. The apparatus according to claim 12, characterized in that, The voltage value of the first high level is greater than the voltage value of the second high level, and the voltage value of the first low level is less than the voltage value of the second low level.

14. The apparatus according to claim 10, characterized in that, It also includes a second sampling module, used for: The chip select signal is sampled to obtain the power control signal and the chip select control signal.

15. An electronic device, characterized in that, include: At least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the method for generating a chip select signal as described in any one of claims 1 to 9.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, implement the chip select signal generation method as described in any one of claims 1 to 9.

Images