Logic circuit and method for checking and updating program counter values

Abstract

The present invention provides a logic circuit and a method for checking and updating a program counter value. The logic circuit can include a checking circuit and a program counter value determination circuit. The checking circuit can check continuity of a current program counter value and a plurality of flags associated with a branch predictor to generate a checking result, wherein the branch predictor is used to control the plurality of flags according to the current program counter value. The program counter value determination circuit can select one of a plurality of candidate program counter values as a subsequent program counter value according to the checking result, wherein the current program counter value corresponds to a current instruction, and the subsequent program counter value corresponds to a subsequent instruction after the current instruction.

Description

Technical Field

[0001] This invention relates to branch prediction in a pipelined architecture, and more particularly to a logic circuit and method for checking and updating a program counter value in a pipelined architecture. Background Technology

[0002] When the central processing unit (CPU) receives a branch instruction in a common pipelined architecture, without any branch prediction, it must wait until the branch instruction enters the instruction execution phase to determine whether the next instruction needs to jump to a branch target instruction that differs from a preset instruction sequence. This limits the operational efficiency of the pipelined architecture. To improve the efficiency of processing branch instructions in a pipelined architecture, a branch predictor is typically used to predict the target instruction of the branch instruction during the instruction fetch (IF) phase, allowing subsequent target instructions to enter the pipelined architecture earlier.

[0003] In related technologies, the static random access memory of the central processing unit (CPU) can be used to implement error correction codes using Single-Error-Correction-Double-Error-Detection (SEC-DED) Hamming codes. However, when the prediction result of the branch predictor causes a transient error due to a soft error, and this transient error (e.g., a multi-bit error) cannot be corrected or detected using SEC-DED, the CPU will malfunction.

[0004] Therefore, a novel checking mechanism is needed to check the order of instruction execution without significantly increasing additional costs, and to properly correct errors when they are detected. Summary of the Invention

[0005] The purpose of this invention is to provide a logic circuit and method for checking and updating the program counter value in a pipelined architecture, so as to solve the problems of related technologies with little or no side effects.

[0006] At least one embodiment of the present invention provides a logic circuit for checking and updating a program counter value in a pipelined architecture. The logic circuit may include a checking circuit and a program counter value determination circuit, wherein the program counter value determination circuit is coupled to the checking circuit. The checking circuit can be used to check the continuity of a current program counter value and multiple flags associated with a branch predictor to generate a checking result, wherein the branch predictor is used to control the multiple flags based on the current program counter value. The program counter value determination circuit can be used to select one of multiple candidate program counter values ​​as a subsequent program counter value based on the checking result, wherein the current program counter value corresponds to a current instruction, and the subsequent program counter value corresponds to a subsequent instruction following the current instruction.

[0007] At least one embodiment of the present invention provides a method for checking and updating a program counter value in a pipelined architecture, wherein the method is applicable to a logic circuit. The method may include: using a checking circuit of the logic circuit to check the continuity of a current program counter value and a plurality of flags associated with a branch predictor to generate a checking result, wherein the branch predictor is used to control the plurality of flags based on the current program counter value; and using a program counter value determining circuit of the logic circuit to select one of a plurality of candidate program counter values ​​as a subsequent program counter value based on the checking result. In particular, the current program counter value corresponds to a current instruction, and the subsequent program counter value corresponds to a subsequent instruction following the current instruction.

[0008] The logic circuits and methods provided by embodiments of the present invention can detect abnormalities in the program counter value or flag when a flexible error occurs, and eliminate problems caused by the flexible error by controlling the subsequent program counter value (e.g., by repeatedly executing instructions corresponding to the same program counter value). Compared to related technologies, embodiments of the present invention do not significantly increase additional costs. Therefore, the present invention can solve the problems of related technologies without or with minimal side effects. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a device operating under an instruction pipelined architecture according to an embodiment of the present invention.

[0010] Figure 2 This is a schematic diagram of a program counter sequence checking circuit according to an embodiment of the present invention.

[0011] Figure 3This is a schematic diagram illustrating the workflow of a method for checking and updating a program counter value in a pipelined architecture according to an embodiment of the present invention.

[0012] Figure 4 The following are some details of the method according to an embodiment of the present invention. Detailed Implementation

[0013] Figure 1 This is a schematic diagram illustrating the operation of a device 10 (e.g., a central processing unit) according to an embodiment of the present invention in an instruction pipelined architecture. In this embodiment, the instruction pipelined architecture may be a five-stage pipeline, including an instruction fetch (IF) stage, an instruction decode (ID) stage, an instruction execution stage, a memory access stage, and a data write-back stage. These stages are respectively labeled "IF", "ID", "EX", "MEM", and "WB" in the diagram for clarity, and each stage is separated by a corresponding interface, which is labeled "IF / ID", "ID / EX", "EX / MEM", and "MEM / WB" for ease of understanding.

[0014] Device 10 can use a program counter (PC) to indicate the current position of the central processing unit's operation within its program sequence, where different program counter values ​​correspond to different instructions. For example... Figure 1 As shown, device 10 may include a multitasking unit 20 (in Figure 1 The system includes a branch predictor 50 (labeled "MUX") and a logic circuit such as a PC sequence check circuit 100. During the instruction fetch phase, the branch predictor 50 can perform branch prediction based on the received PC value, such as determining whether the PC value corresponds to a branch instruction, predicting whether the branch instruction will initiate an instruction jump, and predicting the target PC value for the instruction jump, such as the PC value PC. PREDFor example, branch predictor 50 may include a branch target buffer (BTB) and a jump prediction circuit. The branch target buffer (BTB) may be implemented using static random access memory (SRAM), but the invention is not limited thereto. The branch target buffer may store the PC value of the branch instruction and the branch target (e.g., the prediction target) of the branch instruction to predict the branch jump target of the branch instruction, while the jump prediction circuit may be used to predict whether the branch instruction will take an instruction jump. In addition, branch predictor 50 may transmit these prediction results to PC sequence checking circuit 100 to check these prediction results during the memory access phase and generate a check result such as a flag. RERUN .

[0015] In this embodiment, the flag RERUN It is used to control whether the instruction corresponding to a certain PC value is re-executed. For example, by re-executing this PC value, such as PC... RERUN The instruction fetch phase is returned to allow the corresponding instruction to be re-executed. Additionally, the PC value... SEQ This can represent the next PC value (e.g., the current PC value plus a fixed offset value) under the preset sorting of the branch predictor 50. In this embodiment, the multiplexer 20 can obtain the next PC value from the PC value PC. SEQ PC PRED and PC RERUN Choose one of them as the PC value to enter the instruction acquisition phase. For example, when the flag... RERUN When raised (e.g., FLAG) RERUN =1), Multitasking device 20 can select PC value PC RERUN The PC value is used to enter the instruction fetch phase, and the instructions and data in the current pipeline are flushed to re-execute instructions with the PC value. RERUN The corresponding instructions. For example, when the flag... RERUN Not raised (e.g., FLAG) RERUN =0) and when the prediction result of the branch predictor 50 is to take an instruction jump, the multitasking unit 20 can select the PC value PC. PRED This serves as the PC value for entering the command acquisition phase. For example, when the flag... RERUN Not raised (e.g., FLAG) RERUN =0) and when the prediction result of the branch predictor 50 is that no instruction jump is taken, the multitasking unit 20 can select the PC value PC. SEQThe PC value is used to enter the instruction fetching phase.

[0016] It should be noted that the device 10 may include other logic circuits or arithmetic modules (not shown in the figure) to perform the work of each stage respectively. However, the implementation of these logic circuits or arithmetic modules is well known in the art and does not substantially affect the implementation of the present invention. For the sake of brevity, they will not be described in detail here.

[0017] Figure 2 This is a schematic diagram of a PC sequence checking circuit 100 according to an embodiment of the present invention. Figure 2 As shown, the PC sequence checking circuit 100 may include a PC value determination circuit 110 and a PC value checking circuit 120, wherein the PC value determination circuit 110 is coupled to the PC value checking circuit 120. In this embodiment, the PC value checking circuit 120 can be used to check the continuity of a current PC value and multiple flags such as FLAGs associated with the branch predictor 50. BRANCH and FLAG BPTAKEN To produce an inspection result such as a flag. RERUN The branch predictor 50 can control the flag based on the current PC value. BRANCH and FLAG BPTAKEN Additionally, the PC value determination circuit 120 can be used to determine the value based on the inspection results, such as flags. RERUN One of a plurality of candidate PC values ​​is selected as a subsequent PC value. In particular, the current PC value may correspond to a current instruction, and the subsequent PC value may correspond to a subsequent instruction following the current instruction.

[0018] In this embodiment, the PC value determination circuit 110 may include a selection control logic 111 and a multiplexer 112 (in... Figure 2 The system includes an adder 113 and a buffer 114 (e.g., a register), labeled "MUX". Selection control logic 111 can be based on a flag. RERUN FLAG EXCEPTION FLAG TAKENBRANCH and FLAG PCVALID Generate control signal SEL NEXTPC This controls the multiplexer 112 to select one of the multiple candidate PC values ​​as the subsequent PC value, and the buffer 114 can output the subsequent PC value in the next cycle. It should be noted that in a current cycle, the PC value PC located at the input of the buffer (e.g., the output of the multiplexer 112) is... NEXT [1] can represent the value of the subsequent PC value in the current cycle, and the PC value at the output of the buffer. NEXT[0] can represent the value of the subsequent PC value in a previous period. Additionally, adder 113 can be used to convert the PC value to PC. CURRENT [1] and offset value PC OFFSET Adding them together produces a sequence of PC values ​​(e.g., PC). CURRENT [1]+PC OFFSET ), where the offset value PC OFFSET The value can be set to a fixed value such as 4, 8, 16, etc., depending on the type of instruction, but the present invention is not limited thereto.

[0019] In this embodiment, the PC numerical checking circuit 120 may include a continuity detection logic such as a comparator 121 and an error detection logic such as an AND gate 122 (in... Figure 2 The middle label is indicated by "AND"), and a OR gate 123 (in Figure 2 The OR gate 123 is coupled to the AND gate 122 and the comparator 121. The comparator 121 can be used to compare the PC value with the AND gate 122. CURRENT [1] and PC value PC NEXT [0] Generates a continuous detection result. Due to the PC value PC NEXT [0] can represent the PC value determination circuit 110 based on the flag. RERUN FLAG EXCEPTION FLAG TAKENBRANCH and FLAG PCVALID The subsequent PC value is determined by the value of the previous period (e.g., the period preceding the current period), and the PC value is the PC value that the PC value determining circuit 110 expects or predicts to receive in the current period. CURRENT [1] is the current PC value in the current period (e.g., the PC value indeed received by the PC sequence checking circuit 100 in the current period), therefore the continuity detection result can indicate the PC value PC. CURRENT [1] PC value PC NEXT [0] Whether it is consistent is used to determine whether the continuity of PC values ​​in the pipelined architecture is abnormal. For example, when the continuity test result indicates that the PC value PC CURRENT [1] PC value PC NEXT When [0] is consistent (e.g., the continuity test result shows a logic value "0"), it indicates that the continuity of the PC value in the pipelined architecture is normal. For example, when the continuity test result indicates that the PC value PC... CURRENT [1] PC value PC NEXT [0] When there is an inconsistency (e.g., the continuity test result is displayed as a logical value "1"), it indicates an abnormal continuity of the PC value in the pipelined architecture.

[0020] Additionally, the flag BRANCH It can represent a branch instruction flag to indicate the current instruction (e.g., related to the PC value PC). CURRENT [1] Whether the corresponding instruction is a branch instruction, and the flag. BPTAKEN A flag can be used to indicate the current instruction (e.g., in relation to the PC value). CURRENT [1] Whether to perform instruction jump according to the corresponding instruction. In this embodiment, AND gate 122 can be based on the flag. BRANCH and FLAG BPTAKEN Produces an error detection result such as a flag. INVALID It should be noted that AND gate 122 is used to receive the flag. BRANCH The terminals at Figure 2 An additional circle is shown to indicate the flag. BRANCH Perform the reverse calculation. Therefore, when the flag... BRANCH Indicate that the current instruction is not a branch instruction (e.g., FLAG). BRANCH =0) but flag BPTAKEN However, it indicates that the current instruction takes a jump (e.g., FLAG). BPTAKEN When =1), AND gate 122 can display the flag. INVALID Raise (e.g., FLAG) INVALID =1) to indicate an operational anomaly in the branch predictor 50. In some embodiments, when the flag FLAG INVALID When raised, the PC sequence check circuit 100 can invalidate the PC value in the branch predictor 50 (e.g., the branch target buffer within it). CURRENT [1] The corresponding entry, but the present invention is not limited thereto.

[0021] Additionally, gate 123 can perform a logical OR operation between the continuity detection result and the error detection result to produce the check result such as a flag. RERUN When the continuous detection result indicates the PC value PC CURRENT [1] PC value PC NEXT [0] Inconsistent or when flag is displayed INVALID When a branch predictor 50 malfunctions, the flag is displayed. RERUN Can be lifted (e.g., FLAG) RERUN =1).

[0022] In this embodiment, the plurality of candidate PC values ​​may include values ​​corresponding to the flag. EXCEPTION PC value PC EXCEPTION Corresponding to the flag TAKENBRANCH PC value PCBRANCHTARGET Corresponding to the flag PCVALID The PC value of the sequence (e.g., PC) CURRENT [1]+PC OFFSET ), and corresponding to the flag PC RERUN PC value PC NEXT [0]. When the flag RERUN When lifted, the selection control circuit 111 can control the multiplexer 112 to select the PC value. NEXT [0] as PC value PC NEXT [1], and the output is Figure 1 The PC value shown is PC RERUN To make PC numerical PC NEXT The subsequent instructions corresponding to [0] are re-executed.

[0023] When the flag RERUN When not raised, it indicates the continuity of the current PC value and the multiple flags (such as FLAG). BRANCH and FLAG BPTAKEN If no abnormalities occur, the PC value determination circuit 110 can further select one of the multiple candidate program counter values ​​as the subsequent PC value based on multiple event flags. In this embodiment, the multiple event flags may include an exception event flag such as a flag. EXCEPTION One branch uses jump flags, such as FLAGs. TAKENBRANCH And a valid flag such as a flag. PCVALID For example, the PC value determination circuit 110 can be based on the flag. EXCEPTION Decide whether to select PC numerical PC EXCEPTION PC value PC NEXT [1], where the flag is activated when any interruption event occurs during the operation of device 10. EXCEPTION It can be lifted, and the PC value is PC. EXCEPTION This can represent a target PC value that the device 10 will jump to when it encounters an interrupt event, so that the device 10 will execute preset subsequent instructions according to the interrupt event, but the present invention is not limited thereto. For example, when a flag... EXCEPTION When not raised, the PC value determination circuit 110 can determine the value based on the flag. TAKENBRANCH Decide whether to select PC numerical PC BRANCHTAKEN PC value PC NEXT [1], where the branch predictor 50 determines the PC value PC NEXT [1] When a branch instruction is triggered and a jump instruction is to be performed, the flag is displayed. TAKENBRANCH It can be lifted, and the PC value is PC. BRANCHTAKENThis can represent the target PC value when a jump is taken according to the branch instruction, but the invention is not limited thereto. For example, when the flag... EXCEPTION and PC BRANCHTAKEN When none of them are raised, the PC value determination circuit 110 can determine the value based on the flag. PCVALID Decide whether to select the PC value of the sequence (e.g., (PC) CURRENT [1]+PC OFFSET PC value NEXT [1], where when the PC value is PC CURRENT [1] When a command is confirmed to correspond to a valid instruction (e.g., a general sequence instruction) after being processed in the instruction decoding stage, the flag is set. PCVALID It can be lifted to make the PC value PC NEXT [1] was set to (PC) CURRENT [1]+PC OFFSET However, the present invention is not limited thereto.

[0024] It should be noted that when a PC value is detected as abnormal by its corresponding flag (e.g., the flag), INVALID When raised, the PC sequence check circuit 100 does not necessarily have to immediately invalidate the entry in the branch predictor 50 (e.g., the branch target buffer within it) corresponding to this PC value. For example, when the branch predictor 50 makes the PC value PC due to a flexibility error... CURRENT [1] Corresponding flag BRANCH and FLAG BPTAKEN In the event of a transient anomaly, the PC sequence check circuit 100 can re-execute the check circuit with the PC value PC. CURRENT [1] The corresponding instruction can resolve the aforementioned momentary anomaly. In some embodiments, the PC sequence check circuit 100 may further include a counter for calculating the PC value. CURRENT [1] The number of times the corresponding instruction is re-executed to produce a count result, wherein when the count result is less than a preset threshold, the PC sequence check circuit 100 may compare the PC value in the branch predictor 50 (e.g., the branch target buffer therein) with the PC value. CURRENT [1] The corresponding entry remains valid, and when the count result reaches (or exceeds) the preset threshold, the PC sequence check circuit 100 may be deactivated in the branch predictor 50 (e.g., the branch target buffer therein) and the PC value PC. CURRENT [1] The corresponding entry, but the present invention is not limited thereto.

[0025] Figure 3This is a schematic diagram illustrating the workflow of a method for checking and updating a program counter value in a pipelined architecture according to an embodiment of the present invention, wherein the method is applicable to a logic circuit such as Figure 2 The PC sequence check circuit 100 is shown. It should be noted that one or more steps can be performed... Figure 3 The workflow shown has been added, deleted, or modified. Furthermore, these steps do not necessarily need to be followed exactly as long as they do not affect the overall result. Figure 3 Execute in the order shown.

[0026] In step S310, the logic circuit may use a check circuit (e.g., PC value check circuit 120) to check the continuity of a current program counter value and multiple flags associated with a branch predictor to generate a check result, wherein the branch predictor is used to control the multiple flags based on the current program counter value.

[0027] In step S320, the logic circuit may use a program counter value determination circuit (e.g., PC value determination circuit 110) to select one of a plurality of candidate program counter values ​​as a subsequent program counter value based on the check result, wherein the current program counter value corresponds to a current instruction and the subsequent program counter value corresponds to a subsequent instruction after the current instruction.

[0028] Figure 4 For certain details of the method according to an embodiment of the present invention, wherein Figure 4 The workflow shown is available Figure 2 The PC sequence check circuit 10 shown is used to perform this. It should be noted that one or more steps can be performed... Figure 4 The workflow shown has been added, deleted, or modified. Furthermore, these steps do not necessarily need to be followed exactly as long as they do not affect the overall result. Figure 4 Execute in the order shown.

[0029] In step S400, the PC sequence check circuit 100 can (e.g., via a confirmation flag) PCVALID Check PC value PC CURRENT [1] Whether it is valid. Confirm the PC value PC. CURRENT [1] Once it is valid, the process begins and proceeds to step S410.

[0030] In step S410, the PC sequence check circuit 100 can check the flag. BPTAKEN The flag was raised BRANCH The case where it was not lifted (in) Figure 4 The winning bid is marked as "FLAG" BPTAKEN &! FLAGBRANCH (For simplicity) Whether it is true. If the result of this step is "yes", the process proceeds to step S420; if the result of this step is "no", the process proceeds to step S430.

[0031] In step S420, the PC sequence check circuit 100 may be deactivated in the branch predictor 50 (e.g., the branch target buffer within it) and the PC value PC. CURRENT [1] The corresponding entry, then clear the instructions and data in the pipeline, and select the PC value PC. NEXT [0] as PC value PC NEXT [1](in) Figure 4 The entry marked as "Declare branch target buffer entry, clear pipeline, and set PC" is correct. NEXT [1] Set to PC NEXT [0]” for brevity).

[0032] In step S430, the PC sequence check circuit 100 can check the PC value PC. CURRENT [1] PC value PC NEXT [0] Whether they are consistent (in) Figure 4 The winning designation is "PC" CURRENT [1]==PC NEXT [0]” for brevity). If the result of this step is “yes”, the process proceeds to step S450; if the result of this step is “no”, the process proceeds to step S440.

[0033] In step S440, the PC sequence check circuit 100 can clear the instructions and data in the pipeline and select the PC value PC. NEXT [0] as PC value PC NEXT [1](in) Figure 4 The winning bid indicated "Empty the pipeline and remove the PC". NEXT [1] Set to PC NEXT [0]” for brevity).

[0034] In step S450, the PC sequence check circuit 100 can check the PC value PC. CURRENT [1] Whether it corresponds to a branch instruction (in) Figure 4 (The code is labeled "Branch Instruction?" for brevity). If the result of this step is "Yes", the process proceeds to step S470; if the result of this step is "No", the process proceeds to step S460.

[0035] In step S460, the PC sequence check circuit 100 can confirm the PC value PC. CURRENT [1] is a general instruction, and selects the PC value of the sequence (e.g., (PC) CURRENT [1]+PCOFFSET PC value NEXT [1](in) Figure 4 The winning bid is marked as "PC" NEXT [1] Set to PC CURRENT [1]+PC OFFSET (For the sake of brevity).

[0036] In step S470, the PC sequence check circuit 100 can confirm the corresponding PC value PC. CURRENT [1] Whether the branch instruction takes a jump (in) Figure 4 (The code is labeled "Branch jump?" for brevity). If the result of this step is "yes", the process proceeds to step S480; if the result of this step is "no", the process proceeds to step S460.

[0037] In step S480, the PC sequence checking circuit 100 can select the target PC value predicted by the branch predictor 50, such as PC BRANCHTAKEN PC value PC NEXT [1](in) Figure 4 The winning bid is marked as "PC" NEXT [1] Set it as a branch target for simplicity.

[0038] In step S490, the program counter check ends.

[0039] In summary, this invention uses a PC sequence checking circuit 100 to check the continuity of multiple flags and PC values ​​associated with the branch predictor 50 during the memory access phase to determine how to update subsequent PC values. When an abnormality in the continuity of a related flag or PC value is detected, the pipelined architecture can be controlled to re-execute the instruction corresponding to the abnormal PC value through a corresponding subsequent PC value update mechanism, thereby resolving transient anomalies caused by flexible errors. Compared to related technologies, the embodiments of this invention do not significantly increase additional costs. Therefore, this invention can solve the problems of related technologies without or with minimal side effects.

[0040] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

[0041] [Symbol Explanation]

[0042] 10: Equipment

[0043] 20: Multitasking

[0044] 50: Branch Predictor

[0045] 100: Program counter sequence check circuit

[0046] 110: PC numerical determination circuit

[0047] 111: Select Control Logic

[0048] 112: Multitasking

[0049] 113: Adder

[0050] 114: Buffer

[0051] 120: PC numerical checking circuit

[0052] 121: Comparator

[0053] 122: with the door

[0054] 123: OR gate

[0055] FLAG EXCEPTION FLAG TAKENBRANCH FLAG PCVALID FLAG RERUN Flag

[0056] FLAG BRANCH FLAG BPTAKEN FLAG INVALID Flag

[0057] PC EXCEPTION PC BRANCHTARGET PC CURRENT Program counter value

[0058] PC NEXT [0], PC NEXT [1], PC RERUN PC SEQ PC PRED Program counter value

[0059] PC OFFSET Offset value

[0060] SEL NEXTPC Control signals

[0061] S310~S320, S410~S490: Steps.

Claims

1. A logic circuit for checking and updating a program counter value in a pipelined architecture, comprising: A checking circuit is used to check the continuity of a current program counter value and multiple flags associated with a branch predictor to produce a checking result, wherein the branch predictor is used to control the multiple flags based on the current program counter value. as well as A program counter value determination circuit, coupled to the checking circuit, is used to select one of a plurality of candidate program counter values ​​as a subsequent program counter value based on the checking result. The current program counter value corresponds to a current instruction, and the subsequent program counter value corresponds to a subsequent instruction following the current instruction. The inspection circuit includes: A continuous detection logic is used to generate a continuous detection result based on the current program counter value and the subsequent program counter value; An error detection logic is used to generate an error detection result based on the multiple flags; as well as An OR gate, coupled to a comparator and the error detection logic, is used to perform a logical OR operation between the continuity detection result and the error detection result to produce the check result.

2. The logic circuit of claim 1, wherein the continuity detection result indicates whether the value of the current program counter in the current cycle is consistent with the value of the subsequent program counter in a previous cycle.

3. The logic circuit according to claim 1, wherein the plurality of flags includes a branch instruction flag and a branch prediction flag, the branch instruction flag indicating whether the current instruction is a branch instruction, and the branch prediction flag indicating whether the current instruction will take an instruction jump.

4. The logic circuit according to claim 3, wherein when the branch instruction flag indicates that the current instruction is not a branch instruction and the branch prediction flag indicates that the current instruction takes an instruction jump, the error detection result indicates that the branch predictor is malfunctioning.

5. The logic circuit of claim 4, wherein when the error detection result indicates that the branch predictor is malfunctioning, the logic circuit invalidates the entry in the branch predictor corresponding to the current program counter value.

6. The logic circuit of claim 1, wherein the plurality of candidate program counter values ​​includes the value of the subsequent program counter value in a previous cycle, and when the check result indicates the continuity of the current program counter value or the plurality of flags are abnormal, the program counter value determining circuit selects the value of the subsequent program counter value in the previous cycle as the value of the subsequent program counter value in the current cycle, so that the subsequent instruction corresponding to the value of the subsequent program counter value in the previous cycle is re-executed.

7. The logic circuit of claim 1, wherein when the check result indicates that the continuity of the current program counter value and the plurality of flags are not abnormal, the program counter value determining circuit further selects one of the plurality of candidate program counter values ​​as the subsequent program counter value based on the plurality of event flags.

8. The logic circuit according to claim 7, wherein the plurality of event flags includes an exception event flag, a branch take-jump flag, and a program counter valid flag, and the plurality of candidate program counter values ​​include a first candidate program counter value corresponding to an exception event jump instruction, a second candidate program counter value corresponding to a branch jump target instruction, and a third candidate program counter value corresponding to a preset sequence instruction, wherein the exception event flag, the branch take-jump flag, and the program counter valid flag respectively correspond to the first candidate program counter value, the second candidate program counter value, and the third candidate program counter value.

9. A method for checking and updating a program counter value in a pipelined architecture, the method being applicable to a logic circuit, the method comprising: The logic circuit uses a checking circuit to check the continuity of a current program counter value and multiple flags associated with a branch predictor to produce a checking result, wherein the branch predictor is used to control the multiple flags based on the current program counter value. as well as A program counter value determination circuit using the logic circuit selects one of a plurality of candidate program counter values ​​as a subsequent program counter value based on the check result. The current program counter value corresponds to a current instruction, and the subsequent program counter value corresponds to a subsequent instruction following the current instruction. The inspection circuit includes: A continuous detection logic is used to generate a continuous detection result based on the current program counter value and the subsequent program counter value; An error detection logic is used to generate an error detection result based on the multiple flags; as well as An OR gate, coupled to a comparator and the error detection logic, is used to perform a logical OR operation between the continuity detection result and the error detection result to produce the check result.

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