Test system

Abstract

The embodiment of the present application provides a test system, and relates to the technical field of test.The system comprises a shared memory unit and a plurality of devices;the shared memory unit comprises a plurality of memory operation subunits and a plurality of memories;the plurality of devices comprises at least one real-time computing device and at least one I / O device;the real-time computing device and the I / O device can generate operation instructions;any first memory operation subunit in the plurality of memory operation subunits is used for: acquiring a current operation instruction;when the current operation instruction is a first operation instruction used for operating a storage address of a first memory connected with the first memory operation subunit, interacting with the first memory to obtain first target data corresponding to the first operation instruction by executing the first operation instruction.The present application is helpful to flexibly expand the scale of the I / O device and the real-time computing device in the test system, is convenient for increasing or reducing the memory capacity and bandwidth, and has lower requirements on devices for data interaction between large-scale I / O devices and real-time computing devices.

Description

Technical Field

[0001] This invention relates to the field of testing technology, and more specifically to a testing system. Background Technology

[0002] In automobiles, new energy vehicles, and other vehicles, the electronic and electrical architecture of the entire vehicle is becoming increasingly complex. The number of electronic control units (ECUs), data bandwidth, and the processing power of CPUs and GPUs have all changed by an order of magnitude compared to before.

[0003] Hardware-in-the-Loop (HIL) testing can verify the functionality of various domain controllers, ECUs, CPUs, and other controllers in a vehicle in advance, thereby shortening the controller development cycle.

[0004] In existing HIL testing systems, devices with data storage and processing capabilities (such as real-time machines, or industrial control computers, Real-time Parameter Controls, RTPCs) and I / O cards are used to execute test tasks and complete the testing of the device under test. Typically, there is only one industrial control computer, and all I / O cards need to communicate with it. As testing requirements become more diverse and complex, a single industrial control computer can no longer meet the testing needs, leading to the trend of HIL testing systems towards clustering. In clustered HIL testing systems, the first problem to be solved is memory sharing. Summary of the Invention

[0005] The purpose of this invention is to provide a testing system that divides a large shared memory unit into multiple shared memory nodes. These multiple memory operation sub-units can communicate directly or indirectly with each other, thus realizing a distributed memory scheme with centralized shared memory. This helps to flexibly expand the scale of I / O devices and real-time computing devices in the testing system, making it easy to increase or decrease memory capacity and bandwidth. For data interaction between large-scale I / O devices and real-time computing devices, the requirements for devices are lower.

[0006] To achieve the above objectives, the present invention provides a testing system, which is a HIL system, including a shared memory unit and multiple devices; the shared memory unit includes multiple memory operation subunits and multiple memories, each of the memory operation subunits being connected to at least one memory; the multiple devices include at least one real-time computing device and at least one I / O device, the I / O device being directly or indirectly connected to at least one device under test; both the real-time computing device and the I / O device can generate operation instructions, the operation instructions being used to indicate that a corresponding memory address needs to be operated on; the devices transmit target data through the operation of the memory by the shared memory unit; the target data includes data that needs to be transferred between the real-time computing device and the I / O device during the HIL test; any first memory operation subunit among the multiple memory operation subunits is used to: obtain the current operation instruction; when the current operation instruction is a first operation instruction for operating on the memory address of the first memory connected to the first memory operation subunit, by executing the first operation instruction, interact with the first memory to obtain the first target data corresponding to the first operation instruction.

[0007] In one embodiment, the first memory operation subunit is further configured to: when the current operation instruction is a second operation instruction for operating on the storage address of the second memory among the plurality of memories, send the second operation instruction to other memory operation subunits other than the first memory operation subunit, so that the second operation instruction is eventually passed to the second memory operation subunit connected to the second memory, so as to execute the second operation instruction using the second memory operation subunit.

[0008] In one embodiment, the plurality of memory operation subunits are cascaded sequentially; the first memory operation subunit is specifically configured to: receive the current operation instruction sent by the cascaded memory operation subunits; and / or: when the current operation instruction is the second operation instruction, send the second operation instruction to the cascaded memory operation subunits.

[0009] In one embodiment, depending on the cascading order of the plurality of memory operation subunits, the storage addresses of the memory corresponding to the plurality of memory operation subunits sequentially increase or decrease; the first memory operation subunit is used to compare the storage address to be operated by the second operation instruction with the storage address of the memory connected to the first memory operation subunit when the current operation instruction is the second operation instruction, determine whether to send the second operation instruction to the previous level memory operation subunit or the next level memory operation subunit, and then send it.

[0010] In one embodiment, the first memory operation subunit is specifically configured to: when the current operation instruction is the second operation instruction, determine the second memory operation subunit among the plurality of memory operation units based on the second operation instruction; determine the transmission path information between the first memory operation subunit and the second memory operation subunit from a preset plurality of transmission path information; each transmission path information represents the path by which the operation instruction is transmitted from a port of a corresponding memory operation subunit to a port of another memory operation subunit; and issue the second operation instruction based on the transmission path information between the first memory operation subunit and the second memory operation subunit, so that the second memory operation subunit can obtain and execute the second operation instruction.

[0011] In one embodiment, any two memory operation subunits are directly connected through corresponding ports, and the plurality of transmission path information is a connection routing table that characterizes the connection relationship between the plurality of memory operation subunits.

[0012] In one embodiment, if there are multiple first operation instructions, the first memory operation subunit is further configured to compare the arrival order of the first operation instructions obtained from the device with the arrival order of the first operation instructions obtained from the memory operation subunit, and then execute them sequentially.

[0013] In one embodiment, the first memory operation subunit is configured to sort the first operation instructions obtained from the device according to their arrival order; the first memory operation subunit is further configured to compare the sorted first operation instructions with the arrival order of the first operation instructions obtained from the memory operation subunit, and then execute them sequentially.

[0014] In one embodiment, if there are multiple first operation instructions, the first memory operation subunit is used to determine the arrival order of the multiple first operation instructions based on the timestamp of each first operation instruction.

[0015] In one embodiment, the current device that issues the current operation instruction is configured to: if the operation of the current operation instruction is a write operation, determine whether the operation permission for the storage address operated by the current operation instruction has been successfully obtained before sending the current operation instruction to the memory operation subunit to which the current device is connected; and if the operation permission has been successfully obtained, send the current operation instruction to the memory operation subunit to which the current device is connected; and release the operation permission when it is determined that the current operation instruction has been successfully executed or the amount of data written has reached a set amount of data written.

[0016] In one embodiment, the testing system further includes: at least one status register respectively disposed in each of the memory operation sub-units; each status register corresponds to a storage address in the memory of the memory of the memory operation sub-unit in which it is located; the current device is configured to: read the storage address status indicated by the status register corresponding to the storage address operated by the current operation instruction; if the storage address status indicates that the storage address operated by the current operation instruction is in a writable state, modify the storage address status to indicate that the storage address operated by the current operation instruction is in a non-writable state, and determine that the acquisition of the operation permission is successful; if the storage address status indicates that the storage address operated by the current operation instruction is in a non-writable state, determine that the acquisition of the operation permission fails.

[0017] In one embodiment, the first memory operation subunit is configured to, after executing the first operation instruction for writing the first target data and writing the first target data into the first memory, feed back the writing result of the first target data as response data to the device that sent the first operation instruction, or read the first target data from the first memory as response data to the device that sent the first operation instruction; the first memory operation subunit is configured to, after executing the first operation instruction for reading the first target data and reading the first target data from the first memory, feed back the read first target data as response data to the device that sent the first operation instruction. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a test system according to the first embodiment of the present invention, wherein any two memory operation subunits in the test system are directly connected through corresponding ports.

[0019] Figure 2 This is a schematic diagram of a test system according to the first embodiment of the present invention, wherein multiple memory operation sub-units in the test system are cascaded in sequence;

[0020] Figure 3 yes Figure 2 A schematic diagram of the memory sharing unit of the test system, which includes three memory operation sub-units;

[0021] Figure 4 This is a schematic diagram of the test system being a HIL system according to the first embodiment of the present invention;

[0022] Figure 5 This is a schematic diagram of a two-level arbitration performed by a memory operation subunit according to the second embodiment of the present invention;

[0023] Figure 6This is a schematic diagram of a memory operation subunit in a test system according to a second embodiment of the present invention;

[0024] Figure 7 This is a schematic diagram of a test system according to a third embodiment of the present invention. Detailed Implementation

[0025] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings to provide a clearer understanding of the purpose, features, and advantages of the present invention. It should be understood that the embodiments shown in the drawings are not intended to limit the scope of the present invention, but are merely illustrative of the essential spirit of the technical solution of the present invention.

[0026] In the following description, certain specific details are set forth for the purpose of illustrating various disclosed embodiments in order to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the art will recognize that embodiments may be practiced without one or more of these specific details. In other instances, well-known apparatuses, structures, and techniques associated with this application may not have been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0027] Unless the context requires otherwise, throughout the specification and claims, the word “comprising” and its variations, such as “including” and “having”, shall be understood to have an open, inclusive meaning, that is, to be interpreted as “including, but not limited to”.

[0028] Throughout this specification, references to "an embodiment" or "an embodiment" indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Therefore, the appearance of "in an embodiment" or "an embodiment" in various places throughout the specification does not necessarily refer to the same embodiment. Furthermore, a particular feature, structure, or characteristic may be combined in any manner in one or more embodiments.

[0029] The singular forms “a” and “the” used in this specification and the appended claims include plural references unless otherwise expressly stated herein. It should be noted that the term “or” is generally used to include the meaning of “or / and” unless otherwise expressly stated herein.

[0030] In the following description, in order to clearly demonstrate the structure and working method of the present invention, a number of directional terms will be used. However, terms such as "front", "back", "left", "right", "outside", "inside", "outward", "inward", "up", and "down" should be understood as convenient terms and not as limiting terms.

[0031] In clustered HIL testing systems, industrial control computers (ICCs) and I / O devices are connected via centralized memory. Information exchange between the ICCs and I / O devices occurs through access to this centralized memory, typically using the CC coherence protocol. However, this technology is often controlled by CPU manufacturers and not publicly available. Existing open protocols, such as AXI / CXL, while supporting coherence, have limited support for certain device types and are unsuitable for large-scale memory cascading scenarios. Based on these technical issues, the applicant has proposed the technical solution in this application.

[0032] The first embodiment of the present invention relates to a testing system, such as a hardware-in-the-loop (HIL) testing system, which can be used to test ECUs, domain controllers, and other device-under-tests (DUTs) in vehicles (including but not limited to new energy vehicles, fuel vehicles, etc.). Common DUTs in vehicles include vehicle controllers, battery management system controllers, electric drive controllers, body controllers, chassis suspension controllers, and driver assistance controllers. The test items include, but are not limited to, operational stability tests and control algorithm tests under various scenarios.

[0033] The test system includes multiple devices and a shared memory unit. The shared memory unit includes multiple memory operation subunits and multiple memories. Each memory operation subunit is connected to at least one memory, and each memory is connected to only one memory operation subunit. The memory operation subunits are directly or indirectly connected to each other, and each memory operation subunit is connected to one or more devices.

[0034] In this embodiment, there are various ways to connect the multiple memory operation subunits in the shared memory unit, such as sequential cascading, pairwise interconnection, and tree-like connection.

[0035] The test system includes multiple devices, including at least one real-time computing device and at least one I / O device. The I / O device is directly or indirectly connected to at least one device under test. Both the real-time computing device and the I / O device can generate operation instructions, which are used to indicate that the corresponding memory address needs to be operated. The devices transfer target data through the operation of memory via shared memory units. The target data includes the data that needs to be transferred between the real-time computing device and the I / O device during the HIL test.

[0036] The real-time computing device can be a computer device equipped with a CPU, or a circuit board equipped with a CPU, etc. Similarly, the control module in the I / O device can also be a computer device equipped with a CPU, MCU or FPGA, or a circuit board equipped with a CPU, MCU or FPGA, etc.

[0037] Taking any one of multiple memory operation subunits (denoted as the first memory operation subunit) as an example: The first memory operation subunit is used for:

[0038] Get the current operation command;

[0039] When the current operation instruction is a first operation instruction for operating on the storage address of the first memory connected to the first memory operation subunit, the first target data corresponding to the first operation instruction is interacted with the first memory by executing the first operation instruction.

[0040] Specifically, the first memory operation subunit can obtain the current operation instruction to be executed from the connected device or other memory operation subunits. The current operation instruction can be used to write or read data. Then, it is determined whether the current operation instruction is used to operate on the storage address of the first memory connected to the first memory operation subunit. For example, the first memory operation subunit can compare the storage address operated on by the current operation instruction with the storage address range of the first memory. If the storage address operated on by the current operation instruction is within the storage address range of the first memory, then the current operation instruction is determined to be a first operation instruction; if the storage address operated on by the current operation instruction is outside the storage address range of the first memory, then the current operation instruction is determined to be a second operation instruction.

[0041] If the current operation instruction is a first operation instruction used to operate on the storage address of the first memory connected to the first memory operation subunit, the first memory operation subunit can execute the first operation instruction immediately or after a set time, operate on the first memory, and interact with the first memory to exchange the first target data corresponding to the first operation instruction. Wherein, if the first memory includes multiple memories, the first operation instruction can be used to operate on one or more memories in the first memory connected to the first memory operation subunit, or to operate on a segment of memory within a specific memory.

[0042] The first operation instruction may be an operation instruction to write or read the first target data; if the first operation instruction is an operation instruction to write the first target data, the first memory operation subunit obtains the first target data from the first operation instruction, writes the first target data into the first memory, and after writing the first target data into the first memory, feeds back the writing result of the first target data (e.g., writing successful, writing failed) as response data to the device that sent the first operation instruction, or reads the first target data from the first memory as response data to the device that sent the first operation instruction.

[0043] If the first operation instruction is an operation instruction to read the first target data, then the first memory operation subunit executes the first operation instruction, reads the first target data from the first memory, and after reading the first target data from the first memory, feeds back the read first target data as response data to the device that sent the first operation instruction.

[0044] Alternatively, the response data can be returned to the device that sent the first operation instruction via the opposite path from the first operation instruction being transmitted to the first memory operation subunit.

[0045] If the device sending the first operation instruction is a device connected to the first memory operation subunit, the first memory operation subunit can directly send the first target data to that device. If the device sending the first operation instruction is not a device connected to the first memory operation subunit, the first memory operation subunit can add the identification ID information of the device receiving the first target data, such as a number or address, to the first target data. Then, the first target data is fed back to the device that issued the first operation instruction through other memory operation subunits that are directly or indirectly connected. For example, after obtaining each response data, the first memory operation subunit first determines whether the device to which the response data points (i.e., the device that issued the first operation instruction) is a device connected to it. If so, the first memory operation subunit can directly send the response data to that device. If not, the first memory operation subunit determines the second memory operation subunit connected to the device receiving the response data (i.e., the device that issued the first operation instruction), and sends the response data directly or indirectly to the second memory operation subunit, which then feeds it back to the device that issued the first operation instruction.

[0046] In one example, if there are multiple first operation instructions in the first operation subunit, the first memory operation subunit is further configured to compare the arrival order of the first operation instructions obtained from the device with that obtained from the memory operation subunit, and then execute them sequentially. For example, the first operation subunit records the timestamp of each obtained operation instruction, thereby determining the arrival order of each first operation instruction. The timestamp can be used to indicate the time when the corresponding operation instruction was generated.

[0047] In another example, the first memory operation subunit is used to queue the received operation instructions according to their arrival order and sequentially determine whether the operation instruction is the second operation instruction or the first operation instruction. That is, the first memory operation subunit executes or forwards the operation instructions in the order they arrive, so that each operation instruction is forwarded or executed in a timely manner.

[0048] It should be noted that the memory to be operated by an operation instruction received by the first memory operation subunit can be one or more memories connected to the same memory operation subunit; or it can be multiple memories connected to different memory operation subunits. In this case, while executing the operation instruction, the first memory operation subunit forwards the operation instruction to the memory operation subunits connected to other memories operated by the operation instruction.

[0049] When the current operation instruction is a second operation instruction for operating on the storage address of a second memory in a plurality of memories, the first memory operation subunit sends the second operation instruction to other memory operation subunits outside the first memory operation subunit, so that the second operation instruction is ultimately passed to the second memory operation subunit connected to the second memory, and the second memory operation subunit executes the second operation instruction. Specifically, the first memory operation subunit is used for:

[0050] When the current operation instruction is the second operation instruction, the second memory operation sub-unit is determined among multiple memory operation units based on the second operation instruction; for example, each memory operation sub-unit pre-stores the memory address range that all memory operation sub-units can operate on, so the first memory operation sub-unit can determine the second memory operation sub-unit among the multiple memory operation sub-units connected to the memory when the current operation instruction is the second operation instruction by comparing the memory address operated on by the current operation instruction with the memory address range that all memory operation sub-units can operate on.

[0051] The first memory operation subunit has several preset transmission path information. Each transmission path information represents the path through which an operation instruction is transmitted from one port of a corresponding memory operation subunit to one port of another memory operation subunit. Thus, after determining the second memory operation subunit, the transmission path information between the first and second memory operation subunits can be determined from these several transmission path information. The determined transmission path information represents how the second operation instruction is transmitted from the first memory operation subunit to the second memory operation subunit. Therefore, the first memory operation subunit can issue a second operation instruction based on the transmission path information between the first and second memory operation subunits. The second operation instruction can carry the transmission path information. Thus, each memory operation subunit that receives the second operation instruction can transmit the second operation instruction based on the transmission path information until the second operation instruction is transmitted to the second memory operation subunit. Thus, the second memory operation subunit can obtain and execute the second operation instruction.

[0052] In one example, please refer to Figure 1The testing system includes: multiple devices 1 and a shared memory unit 2. The shared memory unit 2 includes: multiple memory operation sub-units 21 (taking three memory operation sub-units 21 as an example) and multiple memory 22. Any two memory operation sub-units 21 are directly connected through corresponding ports. Each memory operation sub-unit 21 is connected to at least one memory 22, and each memory 22 is connected to only one memory operation sub-unit 21.

[0053] Each memory operation subunit 21 is connected to multiple devices 1, and each device 1 is connected to a single memory operation subunit 21. Each device 1 is directly or indirectly connected to the memory operation subunit 21. Figure 1 Taking the example of each device 1 being directly connected to the memory operation subunit 21; wherein the memory 22 can be a single DDR memory or a storage pool including multiple DDR memories, some or all of the DDR memories can be located in a rack, or the DDR memories can be across racks, for example, distributed in different racks.

[0054] The aforementioned transmission path information is a connection routing table that represents the connection relationship between multiple memory operation subunits 21. The connection routing table contains how the ports of any two devices are connected. Thus, the first memory operation subunit can determine the transmission path information between the first memory operation subunit and the second memory operation subunit by querying the connection routing table.

[0055] The following example illustrates this using the cascading of multiple memory operation sub-units in a test system.

[0056] Please refer to Figure 2 The testing system includes: multiple devices 1 and a shared memory unit 2. The shared memory unit 2 includes: multiple memory operation sub-units 21 and multiple memories 22. The multiple memory operation sub-units 21 are cascaded in sequence. Each memory operation sub-unit 21 is connected to at least one memory 22. Each memory 22 is connected to only one memory operation sub-unit 21.

[0057] Each memory operation subunit 21 is connected to multiple devices 1, and each device 1 is connected to a single memory operation subunit 21. Each device 1 is directly or indirectly connected to the memory operation subunit 21. Figure 2 Taking the example of each device 1 being directly connected to the memory operation subunit 21; wherein the memory 22 can be a single DDR memory or a storage pool including multiple DDR memories, some or all of the DDR memories can be located in a rack, or the DDR memories can be across racks, for example, distributed in different racks.

[0058] Figure 2The test system can be a HIL system, in which multiple devices 1 include: multiple industrial control computers included in the HIL system and at least one I / O device. The I / O device is used to directly or indirectly connect to the device under test. Each I / O device includes: a control module and multiple I / O units that are respectively communicatively connected to the control module. The I / O units are used to directly or indirectly connect to the device under test. The industrial control computer is a type of real-time computing device.

[0059] At this time, each memory operation subunit 21 is connected to multiple devices 1, including at least one industrial control computer and at least one I / O device, such as... Figure 3 As shown, taking a memory sharing unit 2 including three memory operation sub-units 21 as an example, each memory operation sub-unit 21 is connected to X I / O devices, Y industrial control computers and M memory 22, where X≥1, Y≥1, M≥1, and X, Y and M are all integers.

[0060] In this embodiment, multiple devices 1 are connected to a shared memory unit 2, thereby connecting the multiple devices 1 in a star topology through the shared memory unit 2, that is, connecting the industrial control computer and the I / O devices in a star topology.

[0061] In this embodiment, each memory operation subunit 21, its connected memory 22, and device 1 (including industrial control computer and I / O devices) can be considered as a shared memory node. That is, a large shared memory unit is divided into multiple shared memory nodes. By cascading multiple memory operation subunits 21 sequentially, multiple shared memory nodes are cascaded, thus realizing a centralized shared memory cascading scheme. Each shared memory node can support multiple I / O devices, multiple industrial control computers, and can have multiple external memories 22 connected. Therefore, in the test system, the scale of I / O devices and industrial control computers can be flexibly expanded by adding shared memory nodes, facilitating the increase or decrease of memory capacity and bandwidth. For large-scale data interaction between I / O devices and industrial control computers, the requirements for components are lower. The data transmitted between the I / O devices and the industrial control computer is based on the transmission of the operation results of the memory operation subunits on the memory.

[0062] The following section provides a detailed explanation of the target data transfer between multiple cascaded shared memory nodes, using one of the multiple memory operation subunits (the first memory operation subunit) as an example.

[0063] The first memory operation subunit receives the current operation instruction from the connected slave device 1 or the cascaded memory operation subunit 21. The current operation instruction may originate from the connected device 1 (this shared memory node) or other cascaded memory operation subunits 21 (i.e. other shared memory nodes). The first memory operation subunit first determines whether the current operation instruction is used to operate on the memory within this shared memory node. If the operation instruction is used to operate on the memory within this shared memory node, that is, the operation instruction is the first operation instruction, then the first operation instruction can be directly used to interact with the first memory and exchange the first target data corresponding to the first operation instruction.

[0064] If the current operation instruction is not used to operate on the memory within this shared memory node, that is, if the current operation instruction is the second operation instruction, then the second operation instruction is sent to the cascaded memory operation sub-units. For example, each memory operation sub-unit 21 stores the memory address range of all memory operation sub-units 21 corresponding to the memory 22. Thus, the first memory operation sub-unit can determine by comparison whether the second operation instruction is to be transmitted to the upper-level memory operation sub-unit 21 or to the lower-level memory operation sub-unit 21. A second operation instruction may be transmitted once or multiple times.

[0065] In one example, depending on the cascading order of multiple memory operation subunits, the memory addresses corresponding to these subunits sequentially increase or decrease. The first memory operation subunit, when the current operation instruction is the second operation instruction, compares the memory address required by the second operation instruction with the memory address of the memory connected to the first memory operation subunit to determine whether to send the second operation instruction to the next higher-level or next-level memory operation subunit. Thus, the memory operation subunit can also store only its own memory address range. For example, the memory operation subunits 21 cascaded from the first to the last in the multiple memory operation subunits 21 are allocated memory addresses in ascending order. Therefore, when the memory address required by the second operation instruction is lower than the memory address range of the first memory connected to the first memory operation subunit, the first memory operation subunit sends the second operation instruction to the next higher-level memory operation subunit 21; when the memory address required by the second operation instruction is higher than the memory address range of the first memory connected to the first memory operation subunit, the second operation instruction sends the second operation instruction to the next lower-level memory operation subunit 21.

[0066] A large shared memory unit is divided into multiple shared memory nodes. By cascading multiple memory operation subunits, multiple shared memory nodes are cascaded, thus realizing a centralized shared memory cascading scheme. Each shared memory node can support multiple I / O devices, multiple industrial control computers, and can be connected to multiple external storage devices.

[0067] In this embodiment, the operation instructions received by each memory operation subunit 21 (originating from device 1 or other memory operation subunits 21) are generated and issued by one of the devices 1. Taking the current device that sends a current operation instruction as an example, the current device is used for:

[0068] If the current operation instruction is a write operation, before sending the current operation instruction to the memory operation subunit 21 connected to the current device, it is determined whether the operation permission for the memory address operated by the current operation instruction has been successfully obtained; and if the operation permission is successfully obtained, the current operation instruction is sent to the memory operation subunit 21 connected to the current device. Specifically, when the current operation instruction generated by the current device is an operation instruction for writing data, it first attempts to obtain the operation permission for the memory address operated by the current operation instruction, which is the permission to write data to the memory address operated by the current operation instruction; if the operation permission is successfully obtained, the current device sends the current operation instruction to the memory operation subunit 21 connected to the current device; if the operation permission is not obtained, the current device can try to obtain the operation permission for the memory address operated by the current operation instruction again after a set interval.

[0069] The test system also includes: at least one status register respectively set in each memory operation sub-unit 21; each status register corresponds to a storage address in the memory of the memory operation sub-unit 21 it is located in; the number of status registers in each memory operation sub-unit 21 can be one or more, and a status register can correspond to all storage addresses in one memory of the memory operation sub-unit 21 it is located in, or correspond to a segment of storage addresses in the memory of the memory operation sub-unit 21 it is located in, or correspond to all storage addresses in multiple memories of the memory operation sub-unit 21 it is located in, which can be specifically divided as needed, thus each Each memory address in the memory operation subunit 21 has its corresponding status register. Each status register represents the memory address status, i.e., the operation permission of the memory address. For example, when the status register is 0, it indicates that the memory address is writable, meaning that the operation permission of the memory address has not been acquired by any device 1. When the status register is 1, it indicates that the memory address is non-writable, meaning that the operation permission of the memory address has been acquired by a device 1. Thus, by using hardware locks to manage the operation permissions of memory addresses, and ensuring that each device can only issue operation instructions to the memory operation subunit after acquiring the operation permission, congestion of operation instructions is avoided, which helps to improve the overall data interaction efficiency of the test system.

[0070] In one example, when the current device needs to obtain operation permission for the memory address operated on by the current operation instruction, it first reads the memory address status indicated by the status register corresponding to the memory address operated on by the current operation instruction. If the memory address status indicates that the memory address operated on by the current operation instruction is in a writable state, the memory address status is modified to indicate that the memory address operated on by the current operation instruction is in a non-writable state, thus confirming successful acquisition of operation permission. For example, if the current device reads that the value of the status register corresponding to the memory address operated on by the current operation instruction is 0 (indicating that the memory address status is writable), the current device changes the value of the status register to 1 (indicating that the memory address status is non-writable), and the current device successfully acquires operation permission. Subsequently, the current operation instruction is sent to the memory operation subunit 21 connected to the current device, and the memory operation subunit 21 continues to process the current operation instruction. For details, please refer to the foregoing content and will not be repeated here. If the memory address status indicates that the memory address operated on by the current operation instruction is in a non-writable state, confirming that acquisition of operation permission has failed, the device can try to acquire operation permission for the memory address operated on by the current operation instruction again after a set interval.

[0071] In another example, when the current device needs to obtain operation permission for the memory address operated on by the current operation instruction, it directly attempts to write a first preset value (e.g., 1) into the target status register corresponding to the memory address operated on by the current operation instruction. If the target status register currently contains the first preset value, the current device cannot write the first preset value into the target status register. If the target status register currently contains a second preset value (e.g., 0), the current device can write the first preset value into the target status register. Subsequently, the current device reads the value in the target status register to determine whether the target status register has been written with the first preset value by the current device. If the first preset value is found to have been written by the current device in the status register, it is determined that obtaining operation permission for the memory address operated on by the current operation instruction has been successful. If the first preset value is not found to have been written by the current device in the status register, it is determined that obtaining operation permission for the memory address operated on by the current operation instruction has failed, and the device can then attempt to write the first preset value into the target status register corresponding to the memory address operated on by the current operation instruction again after a set time interval.

[0072] In addition, when the device determines that the current operation instruction has been successfully executed or the amount of data written has reached the set amount of data to be written, it releases the operation permission. The way to release the operation permission of the memory address operated by the current operation instruction is, for example, to modify the memory address status indicated by the status register corresponding to the memory address operated by the current operation instruction to the writable state.

[0073] In one example, after the current operation instruction is executed by a memory operation subunit 21 (which may be the memory operation subunit 21 connected to the current device or another memory operation subunit 21), it can write data to the memory address operated on by the current operation instruction, and then read the data in that memory address. If the target data to be written by the current operation instruction is read, it is determined that the current operation instruction has been executed successfully; if the target data to be written by the current operation instruction is not read, it is determined that the current operation instruction has not been executed successfully. The memory operation subunit 21 that executed the current operation instruction feeds back the execution result to the current device, or the current device can also directly determine whether the current operation has been executed successfully by reading the data in the memory address to be operated on by the current operation.

[0074] In another example, the upper limit of data that the memory operation subunit 21 can write to the memory each time, i.e., the data write amount, can also be configured. When the memory operation subunit 21 executes the current operation instruction, it stops writing data when it determines that the amount of data written has reached the set data write amount. The memory operation subunit 21 then sends a prompt message to the current device indicating that the amount of data written in the current operation instruction has reached the set data write amount. Alternatively, the current device can determine whether the amount of data written has reached the set data write amount by reading the data in the memory address to be operated on by the current operation instruction. The remaining unwritten data in the current operation instruction can be written by the current device after it obtains the operation permission for the memory address to be operated on by the current operation instruction again. The upper limit of the amount of data written is still the set data write amount.

[0075] In one example, each device 1 is connected to the shared memory unit 2 via a PCIe bus, that is, the shared memory unit 2 is connected to each device 1 via a PCIe connector. Thus, each device 1 can map the target data to be shared to a segment of address in the memory 22. Each device 1 can read data from the memory 22 by accessing local memory data, thereby realizing read and write access to the same memory data by each device 1 and realizing the sharing of target data among multiple devices 1.

[0076] The shared memory unit 2 is used as a standard PCIe device, which can convert operation instructions from any one of the multiple devices 1 into high-speed serial signals, and transmit the high-speed serial signals representing the operation instructions to each memory operation subunit 21 through a high-speed serial bus. Each memory operation subunit 21 executes the operation instructions to perform read and write operations on the target data of the memory 22.

[0077] In one embodiment, the memory operation subunit 21 may be implemented using an FPGA.

[0078] In one example, the test system described above is a HIL system; please refer to [reference needed]. Figure 4 The HIL system includes: the shared memory unit 2 mentioned above, the industrial computer pool 3, and multiple I / O devices 4. The industrial computer pool 3 may include at least one industrial computer 31. The industrial computers 31 and I / O devices 4 can be housed in different racks or in the same rack. Specifically, the number of industrial computers 31 in the industrial computer pool 3 can be fixed or expandable. The industrial computers 31 in the industrial computer pool 3 can be housed in the same rack or in different racks, and the multiple I / O devices 4 can be housed in the same rack or in different racks.

[0079] In one example, the industrial computer pool 3 includes at least one configurable number of industrial computers 31 (the figure shows an example of four industrial computers 31 in the industrial computer pool 3), meaning the number of industrial computers 31 in the industrial computer pool 3 is expandable and can be configured according to requirements. The industrial computers 31 in the industrial computer pool 3 are interconnected and communicate with each other.

[0080] Figure 4 Taking the shared memory unit 2, which includes three memory operation subunits 21 and six memory modules 22, as an example, each memory operation subunit 21 is connected to two memory modules 22, and each memory operation subunit 21 is connected to an I / O device 4. Each I / O device 4 includes a control module 41 and two I / O units 42. The control module 41 can be a computer including an I / O controller. The number of I / O units 42 in each I / O device 4 is expandable and can be configured according to requirements.

[0081] The control module 41 communicates with the industrial computer 31 in the industrial computer pool 3. The control module 41 also communicates with the I / O units 42 in its respective I / O devices 4. The control module 41 and each I / O unit 42 communicate via the same EtherCAT network. The I / O units 42 and the control module 41 are cascaded and communicate using EtherCAT, which generally meets the low latency requirements. Furthermore, the I / O units 42 can also be plugged into the control module 41, for example, via the control module 41's data bus (e.g., PCIe bus).

[0082] The industrial control computer 31 can be understood as part or all of the real-time emulator (RTPC) in the HIL system. That is, the real-time computing device referred to in this specification. The industrial control computer 31 and the control module 41 can be different computers, or different circuit boards, etc.

[0083] The I / O unit 42 can be understood as an input / output unit.

[0084] Specifically, this can be understood as follows: I / O unit 42 satisfies at least one of the following:

[0085] It can input data relative to the test piece 5;

[0086] It can output data relative to the tested component 5;

[0087] It can input data relative to an industrial control computer 31;

[0088] It can output data relative to the industrial control computer 31;

[0089] The data A input and / or output by I / O unit 42 to the device under test 5 and the data B input and / or output by I / O unit 42 to the industrial control computer may be related or unrelated.

[0090] Specifically, data A and data B can be different forms of data with the same content. For example, the industrial control computer 31 receives a digital signal with a certain content and sends an analog signal with the same content to the device under test 5, or vice versa. For another example, the industrial control computer 31 receives a signal before the fault is injected and sends a signal after the fault is injected to the device under test 5.

[0091] Data A and data B can also be data with the same content and format;

[0092] Data A and data B can also be data with different contents. For example, data A and data B are respectively the trigger signal and the Sign1 signal that triggers I / O unit 42 to generate a certain Sign1 signal. For another example, I / O unit 42 needs to obtain a certain condition signal from industrial control computer 31 in order to simulate the Sing2 signal that needs to be sent to the test device 5. In this case, the condition signal and the Sign2 signal are data A and data B, respectively.

[0093] I / O unit 42 can refer to a circuit, a circuit board, or a device containing a circuit board and other assemblies.

[0094] In one example, the I / O unit 42 can interact with the industrial computer 31 via the control module 41, or directly or via a switching matrix with the device under test 5 (e.g., the controller of a vehicle).

[0095] I / O unit 42 can implement only input and / or output functions. In some examples, it can also process the transmitted signals during input and / or output, such as performing signal conversion, fault simulation, information simulation, signal generation, and on / off control. Therefore, regardless of whether other functions are integrated, it can be considered one implementation method for I / O unit 42.

[0096] The I / O unit 42 can be an I / O board, such as a board supporting at least one of the following functions: digital signal input, analog signal input, digital signal output, analog signal output, PWM signal input, PWM signal output, high-side power output, and low-side power output. It can further realize high-speed signal acquisition and output. Furthermore, the board resources can be flexibly configured according to requirements. The board accuracy and sampling frequency performance achieved by this technology have reached industry-leading levels.

[0097] The I / O boards include at least one of the following: AD PWM-IN board, DAC board, FIU board, PWM-OUT board, RELAY-IO board, RC board, PSI5&DSI3&SENT board, multi-bus board (Flexray / CANFD / LIN), Eth (vehicle-mounted network) board, etc.

[0098] The I / O boards may also include at least one of the following dedicated boards: current output board, thermocouple board, battery simulator, temperature simulator, motor board, IO_HUB board.

[0099] Furthermore, an I / O unit can be understood as containing one or more I / O channels, and an I / O unit can also be understood as the I / O channel of an I / O board.

[0100] In the HIL system, the cluster control module within the HIL system can determine the data transmission relationships between at least some of the I / O units 42 and at least some of the industrial control computers 31 for the current test task. The cluster control module can be connected to one of the computers in each industrial control computer 31, or any industrial control computer 31 can be configured as a cluster control module.

[0101] The data transmission relationship can be understood as: determining the industrial control computer 31 and I / O unit 42 that need to directly or indirectly share data when performing the corresponding test task;

[0102] Furthermore, at least one relationship can be represented between one or more industrial control computers 31 (i.e., at least some industrial control computers 31) and one or more I / O units 42 (i.e., at least some I / O units 42) that allows data transmission, that is, to define the industrial control computers 31 and I / O units 42 that allow data transmission.

[0103] In one example, the data transmission relationship can further determine which industrial control computer 31 the data transmitted from the industrial control computer 31 should be synchronized to, and which I / O unit 42 the data transmitted from the industrial control computer 31 should be synchronized to. That is, the mapping relationship between the industrial control computer 31 and the I / O unit 42 is defined in detail. Furthermore, the data transmission relationship can further define the mapping relationship between the ports in the industrial control computer 31 and the ports in the I / O unit 42. The ports can refer to hardware ports, software ports, addresses, etc. (e.g., a certain output port or input port of a certain model running in the industrial control computer). Thus, with the mapping relationship described, the industrial control computer 31 and the I / O unit 42 that are allowed to transmit data can be represented.

[0104] In another example, the data transmission relationship is mainly used to define the range of the industrial control computer 31 and the I / O unit 42 that are allowed to transmit data. As for which I / O unit 42, device under test or port (I / O unit 42 or port of device under test 5) the industrial control computer should transmit to each time data is transmitted, and which industrial control computer 31 or which port of industrial control computer 31 the data transmitted from I / O unit 42 should be transmitted to, these can be determined by other means.

[0105] Furthermore, if there are multiple control modules 41, and different control modules 41 are connected to different I / O units 42, then in one example, the data transmission relationship can be understood as: at least used to define the range of the industrial computer 31 and the I / O units 42 to which the control modules 41 are connected, allowing data transmission.

[0106] Different data transmission relationships can be determined for different tasks, and different tasks can be executed simultaneously or sequentially.

[0107] After determining the data transmission relationship between at least some I / O units 42 and at least some industrial control computers 31, the cluster control module can complete the data transmission between I / O units 42 and industrial control computers 31 in various ways based on the data transmission relationship. Taking the determination of the data transmission relationship between K industrial control computers 31 and L I / O units 42 by the cluster control module as an example.

[0108] In one example, the cluster control module sends the data transmission relationship to K industrial control computers 31. Based on this relationship, each industrial control computer 31 can determine which I / O channel of which I / O unit 42 to retrieve target data from when it needs to acquire it, and which I / O channel of which I / O unit 42 to send the target data to when it needs to send it to the device under test (DUT). Since the connection between the control module 41 and the I / O units 42 is fixed, each industrial control computer 31 can determine which control module 41 to retrieve the required target data from and which control module 41 to send the target data to. Specifically, when each industrial control computer 31 needs to send information to the DUT, it designates an I / O unit 42 to receive the information based on the data transmission relationship. The control module 41 then sends the information to the DUT through the designated I / O unit 42. In addition, when the device under test needs to send reporting information to the industrial control computer 31, the control module 41 receives the reporting information through L I / O units 42. The I / O units 42 can mark the I / O units 42 that send each reporting information, so that each industrial control computer 31 receives the reporting information from the designated I / O unit 42 based on the above data transmission relationship.

[0109] Suppose that data transmission is required between an industrial computer 31 and an I / O unit 42 connected to a control module 41. Let the industrial computer 31 be referred to as device A and the control module 41 as device B.

[0110] For example, each device (including the aforementioned industrial computer 31 and control module 41) has its own pre-defined address space in its memory. When device A needs to transfer the target data to device B, it can write the target data into the corresponding address space in device B's memory. Device B can periodically retrieve data from its own corresponding address space in memory. If device B needs to distribute the retrieved data to I / O units 42, in one scenario, device A can write an I / O unit 42 (or its I / O channel) identifier into the shared target data, and device B can allocate the data based on the identifier contained in the retrieved data. In another scenario, different I / O units 42 (or their I / O channels) of device B can be allocated different address subspaces. When sharing target data, device A can instruct the target data to be written into the corresponding address subspace, and device B only needs to read the data from the address subspace and provide it to the corresponding I / O unit 42.

[0111] When device A obtains target data from device B, it can also directly retrieve the data from the corresponding address space or address subspace of device B based on data transmission relationships, and then provide it to the corresponding port of the corresponding model according to the data transmission relationships; the model mentioned here can refer to the test simulation model running on device A. Alternatively,

[0112] When device A obtains target data from device B, device B can also write the target data to the corresponding address space of device A. Device A can periodically retrieve the target data from its corresponding address space in memory. At this time, if the target data needs to be given to the corresponding model and its port, in one scheme, device B can write the identifier of I / O unit 42 (or its I / O channel) into the shared target data. Based on this identifier and the data transmission relationship, device A knows which model and which port the data from I / O unit 42 (or its I / O channel) should be given to.

[0113] In another example, the cluster control module sends this data transmission relationship to one or more control modules 41 connected to the L I / O units 42. When each industrial computer 31 needs to send information to the device under test (DUT), it directly sends the information to the control module 41. The control module 41 then sends the information to the DUT via the designated industrial computer 31 based on the data transmission relationship. Similarly, when the DUT needs to send reporting information to the industrial computer 31, the control module 41 receives the reporting information through the L I / O units 42. Based on the aforementioned data transmission relationship, the control module 41 sends the reporting information from each I / O unit 42 to the designated industrial computer 31.

[0114] For example, during the execution of a certain test task, K industrial control computers and L I / O units are used to test the device under test (DUT) 5. The L I / O units are connected to the DUT 4. The data transmission relationship defines the flow of target data between the industrial control computers 31 and the I / O units 42. That is, after the reporting information from the DUT 5 or I / O units 42 that needs to be sent to the industrial control computers 31 is transmitted to the I / O units 42, each I / O unit 42 sends the reporting information to the control module 41. This data transmission relationship determines which industrial control computer 31 (or its port) the control module needs to send the reporting information from each I / O unit to. After the sending information generated by the target industrial control computer that needs to be sent to the DUT 5 or I / O units 42 is transmitted to the control module, this data transmission relationship determines which sending information from each industrial control computer 31 is sent to the DUT 5 or I / O units 42. The DUT 5 can receive different information through different pins. When the industrial computer 31 transmits information to the control module 41, it can add its own identifier or the identifier of the I / O unit 42 receiving the data to the transmitted information. When the I / O unit 42 transmits reporting information to the control module, it can add its own identifier or the identifier of the industrial computer 31 receiving the reporting information to the reported information. Thus, the control module 41 can forward data between the industrial computer 31 and the I / O unit 42.

[0115] As can be seen, the control module 41 can be used to select the interaction path between the industrial computer 31 and the I / O unit 42.

[0116] It should be noted that, Figure 4 Taking the example of each I / O device 4 having a control module 41, this is not an exception. Each I / O device 4 can also have multiple control modules 41. Each control module 41 corresponds to one or more I / O units 42, and each I / O unit 42 corresponds to only one control module 4. Each control module 41 is connected to its corresponding I / O unit 42. For the current test task, each control module 41 can determine the data transmission relationship corresponding to itself. Taking any control module 41 as an example, the data transmission relationship determined by the control module 41 limits the data transmission relationship between at least some industrial control computers 31 and all target I / O units. The target I / O unit is the I / O unit corresponding to the control module 41. That is, the control module 41 determines which industrial control computer 31 the data transmitted from each target I / O unit should be synchronized to, and which target I / O unit the data transmitted from the industrial control computer 31 should be synchronized to. In each I / O device 4, each control module 41 and each I / O unit 42 can be connected in a cascaded manner, or each control module 41 can be directly connected to each I / O unit 42.

[0117] In this embodiment, each I / O unit 42 is directly or indirectly connected to the device under test (DUT) 5, and the number of DUTs 5 can be one or more. Figure 4 In one example, taking the direct connection between I / O unit 42 and device under test (DUT) 5 as an example, DUT 5 is directly connected to the ports of each I / O unit 42 via connectors to achieve signal transmission; different I / O units 42 can be connected to different pins of DUT 5 to transmit different information. In another example, a switching matrix can be set in the HIL system, connected between I / O units 42 and DUT 5, meaning each I / O unit 42 is indirectly connected to its corresponding DUT 5 through the switching matrix. Specifically, all I / O units 42 in I / O devices 4 can be configured to be connected to DUT 5 through the same switching matrix, or I / O units 42 in the same shared memory node can be connected to DUT 5 through the same switching matrix, or I / O units 42 in the same I / O device 4 can be connected to DUT 5 through the same switching matrix.

[0118] As can be seen, to achieve communication between the industrial control computer (ICC), I / O devices, and the device under test (DUT), and to transmit target data, when a switching matrix is ​​in place, both the switching matrix and the data transmission relationships of the control modules must be configured. This enables the data transmission required for testing between the ICC and the DUT, such as data transmission between the ports of the simulation model in the ICC and the ports of the DUT. This approach allows for more flexible and customizable connection methods for the DUT. Only the switching matrix needs to be configured according to the actual connection situation. For example, after configuring the control modules, if no switching matrix is ​​set, it is necessary to determine which I / O devices the DUT should be connected to and how to connect them based on the configuration results. With a switching matrix, the DUT can be connected to the switching matrix more freely, and then only the switching matrix needs to be configured to achieve the required data transmission for testing.

[0119] Multiple devices 1 include: industrial control computers 31 and I / O devices 4 in the HIL system, that is, each industrial control computer 31 and I / O device 4 is connected to the memory operation subunit 22 of the shared memory unit 2, and the memory operation subunits 22 are cascaded with each other, thereby connecting each industrial control computer 31 and I / O device 4 in a star topology through the shared memory unit 2.

[0120] During the testing of the HIL system, the memory operation subunit 21 receives operation instructions from either the industrial control computer 31 or the control module 41. The operation instructions are used to write at least part of the target data to or read at least part of the target data from the memory 22. The memory operation subunit 21 executes the operation instructions sent by the designated device. If the operation instructions are used to write at least part of the target data to the memory 22, then the operation instructions contain the target data to be written. The memory operation subunit 21 executes the operation instructions and writes the target data contained in the operation instructions into the memory 22. If the operation instructions are used to read at least part of the target data from the memory 22, then the operation instructions contain identification information of the target data to be read. The identification information represents the source of the target data, either the industrial control computer 31 or the I / O device 4. The memory operation subunit 21 executes the operation instructions, reads the target data corresponding to the identification information in the operation instructions, and feeds back the target data to the designated device that sent the operation instructions.

[0121] Based on the above process, target data generated by each industrial control computer 31 can be synchronized to the I / O device 4, and target data received by the I / O device 4 from the device under test 5 can be synchronized to each industrial control computer 31. The target data includes information generated by the industrial control computer 31 that needs to be sent to the device under test 5, and / or, information that needs to be sent to the industrial control computer 31 via the control module. (For example, it can originate from the device under test, where "originates" indicates that the content of the reported information is related to or determined by the signal emitted by the device under test).

[0122] The target data may further include data that needs to be shared between industrial control computers or between control modules.

[0123] The target data transmitted between I / O device 4 and industrial computer 31 is obtained based on the operation results of memory 22. That is, after generating the information to be sent to device under test 5, industrial computer 31 sends an operation instruction to memory operation subunit 21 to write the information. Memory operation subunit 21 determines whether the operation instruction is a second operation instruction or a first operation instruction. If the operation instruction is a second operation instruction, it forwards the second operation instruction to the target memory operation subunit through cascading. If the operation instruction is a first operation instruction, it executes the first operation instruction and writes the information to memory 22. Subsequently, I / O device 4 reads the information from memory 22 by sending an operation instruction to memory operation subunit 21 to read the information and sends it to device under test 5. Similarly, after receiving the reporting information sent by the device under test 5, the I / O device 4 sends an operation instruction to the memory operation subunit 21 to write the reporting information. The memory operation subunit 21 repeats the above process to write the reporting information into the memory 22 indicated by the operation instruction. Subsequently, the industrial control computer 31 reads the reporting information from the memory 22 by sending an operation instruction to the memory operation subunit 21 to read the reporting information.

[0124] In addition, other adapter circuits and interfaces can be provided between the device under test and the I / O unit, such as DB9 interface, EDAC interface, BOB module, etc.

[0125] In this embodiment of the HIL testing system, multiple devices are connected in a star topology through a shared memory unit. Multiple memory operation sub-units in the shared memory unit are cascaded. Each device can synchronize the target data to be shared to the memory of the shared memory unit, and each device can also read the target data required from the memory. This enables multiple devices to perform read and write operations on the same physical memory, ensuring data consistency among multiple devices and offering advantages such as high sharing efficiency, good accuracy, and low latency.

[0126] The second embodiment of the present invention relates to a testing system. The main difference between this embodiment and the first embodiment is that the first memory operation subunit performs two-level arbitration on the operation commands, as follows:

[0127] The first memory operation subunit is used to sort the first operation instructions obtained from the device in the order of arrival.

[0128] The first memory operation subunit is also used to compare the sorted first operation instructions with the arrival order of the first operation instructions obtained from other connected memory operation subunits 21, and then execute them sequentially.

[0129] In one example, please refer to Figure 5In the first memory operation subunit, the first-level arbitration is used to arbitrate the first operation instructions from each device 1, that is, to arbitrate the first operation instructions from the device 1 that is directly connected to the first memory operation subunit. After arranging them according to the order of arrival at the first memory operation subunit, they are output sequentially for the second-level arbitration.

[0130] The second-level arbitration simultaneously arbitrates the first operation instruction after the first-level arbitration and the first operation instructions from other memory operation subunits 21 that are communicatively connected to the first memory operation subunit. All the first operation instructions to be executed are arranged according to the order in which they arrive at the first memory operation subunit, and the execution order of all the first operation instructions is obtained. Then they are executed in sequence to operate on the memory 22.

[0131] In one example, each operation instruction may include a timestamp of the time that device 1 sent the operation instruction, thereby the first memory operation subunit is used to determine the arrival order of each first operation instruction based on the timestamp of each first operation instruction, so as to achieve the above-mentioned two-level arbitration.

[0132] In one example, such as Figure 6 As shown, each memory operation subunit 21 may include: a first-level arbitration module 211, a second-level arbitration module 212, and an execution module 213 connected in sequence, with the execution module 213 connected to the memory 22 within this shared memory node.

[0133] The first-level arbitration module 211 is used to receive the first operation instructions sent by each directly connected device 1, sort these first operation instructions, and then output them sequentially to the second-level arbitration module 212.

[0134] The secondary arbitration module 212 is used to receive the first operation instruction sent by the primary arbitration module 211 and the first operation instructions of other memory operation subunits 21 for arbitration. It arranges all the first operation instructions to be executed in the order of arrival at the memory operation subunits 21 and outputs them to the execution module 213 in sequence. The execution module 213 then executes each first operation instruction in the order of receiving the first operation instructions, operates on the memory 22, and interacts with the memory 22 for target data.

[0135] It should be noted that, Figure 6 Only the modules related to the two-level arbitration of the memory operation subunit 21 and the operation instructions are shown. The memory operation subunit 21 may also contain other modules to perform other functions of the memory operation subunit 21, which will not be described in detail here.

[0136] The third embodiment of the present invention relates to a testing system. The main difference between this embodiment and the first embodiment is that this embodiment provides another implementation of the memory operation subunit in the shared memory unit.

[0137] Please refer to Figure 7 Each memory operation subunit 21 includes: multiple memory access units 214 and a memory control unit 215; multiple devices 1 correspond one-to-one with multiple memory access units 214, and each device 1 is connected to the memory control unit 215 through the corresponding memory access unit 214. The memory control unit 215 is also connected to the memory 22 within this shared memory node. The memory control units 215 in the multiple memory operation subunits 21 are cascaded sequentially. It should be noted that this embodiment uses... Figure 2 The test system shown is an example, but it is not limited to this. The memory operation subunit in this embodiment can also be applied to... Figure 1 The testing system.

[0138] Each device 1 is connected to the corresponding memory access unit 214 via a PCIe bus. That is, one end of the memory access unit 214 is plugged into the corresponding device 1 via PCIe, and the other end of the memory access unit 214 is connected to the memory control unit 215 via a high-speed serial bus.

[0139] In this embodiment, the memory control unit 215 is used to receive operation instructions sent by the connected device 1 through the memory access unit 214, and to receive operation instructions from the memory control units 215 of other cascaded memory operation subunits 21.

[0140] For the memory control unit 215 in each memory operation unit 21, when it receives an operation instruction, it first determines whether the operation instruction is used to operate on the target memory within the shared memory node. If the operation instruction is not used to operate on the target memory within the shared memory node, the operation instruction is the second operation instruction; if the operation instruction is used to operate on the target memory within the shared memory node, the operation instruction is the first operation instruction.

[0141] In response to the second operation instruction, the memory control unit 215 identifies the memory control unit 215 connected to the memory 22 indicated by the second operation instruction as the target memory control unit, and then sends the second operation instruction to the target memory control unit through cascading.

[0142] In response to the first operation instruction, the memory control unit 215 can execute the first operation instruction immediately or at a set time, operate on the target memory, interact with the target memory to exchange target data corresponding to the first operation instruction, and then send response data back to the device 1 that sent the first operation instruction.

[0143] The transmission of the second operation instruction and the execution of the first operation instruction by the memory control unit 215 are similar to those in the first embodiment and will not be repeated here.

[0144] In the above embodiment, the data transmission relationship between the K industrial computers 31 and L I / O units 42 in the industrial computer pool 3 executing the current first test task can be determined by the cluster control module in the HIL test system. The number of cluster control modules can be one or more; each test task can test one or more devices under test of the same type, and the first device under test tested by the first test task is... Figure 4 The number of test devices 5 in the test device list can be one or more. The L I / O units 42 can originate from one or more I / O devices 4.

[0145] Specifically, for the first test task to be executed, the cluster control module can first allocate K industrial control computers 31 from the industrial control computer pool 3 to execute the first test task, and allocate L I / O units 42 from the I / O devices 4 to execute the first test task, thus obtaining the K industrial control computers 31 and L I / O units 42 for executing the first test task. Then, the data transmission relationship between the K industrial control computers 31 and the L I / O units 42 is established. If there are insufficient resources for the industrial control computers 31 in the industrial control computer pool 3 and / or the I / O units 42 in the I / O devices 4, horizontal expansion can be performed accordingly, i.e., adding new shared memory nodes, and cascading the memory operation subunits 21 in the newly added shared memory nodes with the existing memory operation subunits 21.

[0146] After determining the data transmission relationship between K industrial control computers 31 and L I / O units 42, the cluster control module can send this data transmission relationship to each of the K industrial control computers 31. When each industrial control computer 31 needs to send information to the first device under test (DUT), it designates an I / O unit 42 to receive the information based on this data transmission relationship. The control module 41 connected to the L I / O units 42 then sends the information to the DUT through the designated I / O unit 42. Furthermore, when the DUT needs to send reporting information to the industrial control computers 31, at least one control module 41 receives the reporting information through the L I / O units 42. The I / O units 42 can mark the I / O unit 42 that sends the reporting information, thus allowing each industrial control computer 31 to receive the reporting information from the designated I / O unit 42 based on the aforementioned data transmission relationship.

[0147] or,

[0148] After determining the data transmission relationship between the K industrial control computers 31 and the L I / O units 42, the cluster control module can feed back this data transmission relationship to the control module 41 connected to the L I / O units 42. When each industrial control computer 31 needs to send a message to the first device under test (DUT), it directly sends the message to the control module 41 connected to the L I / O units 42. The control module 41 then sends the message to the DUT via the designated I / O unit 42 based on the data transmission relationship. Similarly, when the DUT needs to send a report to the industrial control computer 31, at least one control module 41 receives the report through the L I / O units 42. Based on the aforementioned data transmission relationship, at least one control module 41 sends the report from each I / O unit 42 to the designated industrial control computer 31.

[0149] In addition, the L I / O units 42 are configured to communicate with the first device under test (DUT). For example, after dividing into L I / O units 42, the L I / O units 42 are directly connected to each of the first DUTs, or a switching matrix is ​​connected between the I / O units 42 and the first DUTs. The cluster control module configures the first port connected to the L I / O devices in the switching matrix to form a connection channel with the second port connected to the first DUTs, thus establishing a communication connection between the L I / O units 42 and the first DUTs. As a result, the switching matrix 5 can transmit target data between the L I / O units 42 and the first DUTs through the configured connection channel.

[0150] The cluster control module is also used to send the task information of the first test task to K industrial control computers 31, so that the industrial control computers 31 can generate the distribution information to be sent to the first device under test based on the task information of the first test task. The task information of the first test task includes the simulation model, test parameters, and test cases required for the test.

[0151] The cluster control module is also used to determine the test requirements information for the first test task. The test requirements information at least indicates the number of CPUs (or industrial control computers) and the number of I / O units 42 required to execute the first test task. The quantity information is a numerical value or a range. Additionally, the test requirements information may include the memory and storage space required for the test; that is, the selection of CPUs and I / O units 42 also needs to consider whether the available memory and storage space meets the test requirements. The selection of an industrial control computer can also be understood as the selection of a CPU.

[0152] In one specific example, test requirement information can also be used to characterize the quantity and / or type of required memory, GPU, bus interface, sensor interface, simulation board, etc.

[0153] In another specific example, test requirement information can also be used to characterize various parameters of the CPU or industrial control computer, such as the model, brand, and attributes of the GPU and memory.

[0154] The cluster control module determines the test requirements information for the first test task in the following ways, including but not limited to:

[0155] In one example, the cluster control module determines the number of CPUs (or industrial control computers) and the number of I / O units required to execute the first test task based on the task information of the first test task, thus obtaining test requirement information. For example, it calculates the resource consumption for executing the first test task based on the task information, thereby determining the test requirement information of the first test task; or, it queries historical test data based on the task information of the first test task, and finds the test requirement information of previously executed first test tasks as the test requirement information of the current first test task. The task information includes at least one or any combination of the following: test cases, test simulation models, and test parameters.

[0156] In one example, the cluster control module obtains the number of CPUs N (or industrial control computer information) and the number of I / O units L required to execute the first test task from the received configuration parameters of the first test task. The configuration parameters include: information on the number of CPUs configured to execute the first test task, and information on the number of I / O devices. For example, the cluster control module is connected to a host computer, and the user can configure the configuration parameters for each first test task on the host computer and send the configuration parameters of the first test task to the cluster control module. Thus, the cluster control module can obtain the test requirement information of the first test task from the configuration parameters; that is, the configuration parameters can be user-specified.

[0157] In one example, the cluster control module performs pre-testing based on the received task information of the first test task, and determines the test requirements information of the first test task based on the test results during the pre-testing process. For example, one or more simulation models for testing are selected from the task information of the first test task. The pre-testing is to test the simulation model. An industrial control computer 31 is selected from the industrial control computer pool 1 to run the simulation model, and an I / O unit 42 is selected to perform pre-testing together with the selected industrial control computer 31. Test information during the pre-testing process is obtained, and the test requirements information of the first test task is determined based on the test information. The test information includes any one or any combination of the following: test time, operating status of industrial control computer 31, operating status of I / O unit 42, etc., where the operating status includes, but is not limited to, CPU utilization rate, memory utilization rate, etc. Alternatively, the pre-testing is to use all or a specified number of industrial control computers 31 currently in an idle state and all or a specified number of I / O units 42 currently in an idle state to execute the first test task within a certain period of time, then obtain the test information during the test process, and determine the test requirements information of the first test task based on the test information.

[0158] The cluster control module is used to select N CPUs from the currently idle CPUs and L I / O units 42 from the currently idle I / O units 42 based on test requirement information, where N is any integer greater than or equal to 1. "Idle" here means that there is currently no first test task being executed or pending. Additionally, the cluster control module will also determine that the newly expanded industrial control computers 31 in the industrial control computer pool 1 and the I / O units 42 in the newly expanded shared memory nodes are all in an idle state.

[0159] Taking the selection of N CPUs from currently idle CPUs as an example, the cluster control module can read the number of CPUs required to execute the first test task from the test requirement information of the first test task. If the number information is a numerical value, CPUs of that number can be selected directly from the idle CPUs, or N CPUs greater than that number can be selected from the idle CPUs. If the number information is a range, the number of idle CPUs can be obtained first. If the number of idle CPUs is greater than or equal to the lower limit of the range, a number value can be selected within that range. The selected number value is less than or equal to the number of idle CPUs, and then CPUs of that number value can be selected from the idle CPUs. For example, under the premise of ensuring that the number value selected from the range is less than or equal to the number of idle CPUs, the largest number value is selected first, thereby selecting more CPUs to execute the first test task and providing a certain degree of redundancy.

[0160] Each of the K industrial control computers 31 includes at least one CPU from the N CPUs. In one example, when selecting N CPUs from the currently idle CPUs, CPUs can be selected first from one industrial control computer 31. If no idle CPUs are found in a single industrial control computer 31, and if N CPUs are still not selected, then CPUs are selected from the next industrial control computer 31, and so on, until N CPUs are selected.

[0161] The specific method for selecting L I / O units 42 from the currently idle I / O units 42 is similar to the method for selecting the CPU described above, and will not be repeated here.

[0162] In addition, if the test requirements information can also include the memory and storage space required for the test, then when selecting the CPU and I / O unit 42, the memory and storage space required for the test can also be taken into account. That is, it is necessary to ensure that the selected CPU and I / O unit 42 meet the requirements for memory and storage space.

[0163] The cluster control module is also used to use N CPUs and L I / O units 42 to execute a first test task to test the first device under test, and after the first test task is completed, to release the N CPUs and L I / O units 42 that executed the first test task so that the released CPUs and I / O units 42 can return to the idle state.

[0164] Specifically, during the testing process, each industrial control computer 31 uses its selected CPU (or can be understood as the first target industrial control computer) to execute the corresponding test part. The CPU used for testing in each first target industrial control computer can generate the information to be sent to the first device under test (DUT) and send the information to the control module 41 connected to the L I / O units 42. Each control module 41 then sends the information from each CPU to the first DUT through the designated I / O unit 42. During the testing process, the first DUT can generate the reporting information to be sent to the first target industrial control computer. Each control module 41 receives the reporting information through the L I / O units 42 and sends the reporting information from each I / O unit 42 to the designated CPU of the first target industrial control computer.

[0165] When the first test task is completed, for example, after the set test time or the set number of cycles is met, the cluster control module releases N CPUs and L I / O units 42 in the K first target industrial control computers that executed the first test task. The released CPUs and I / O units 42 all re-enter the idle state.

[0166] In this embodiment, the cluster control module is further configured to: before the first test task is completed, based on the test requirement information of another second test task, use J CPUs from the CPUs of multiple industrial control computers 31 and M I / O units 42 from the I / O units 42 to execute the second test task to test another second device under test, so that the second device under test and the J CPUs can interact through the M I / O units 42; J and M are both arbitrary integers greater than or equal to 1; wherein, the J CPUs and N CPUs are different CPUs from the CPUs of multiple industrial control computers, and the L I / O units 42 and M I / O units 42 are different I / O units 42 from the I / O units 42.

[0167] And / or:

[0168] After releasing the N CPUs and L I / O units 42 executing the first test task, based on the test requirements of another third test task, Z CPUs are selected from the currently idle CPUs, and T I / O units 42 are selected from the currently idle I / O units 42. The third test task is then executed using the Z CPUs and T I / O units 42 to test the third device under test, so that the third device under test and the Z CPUs can interact through the T I / O units 42. Z and T are both arbitrary integers greater than or equal to 1. Among them, the Z CPUs and N CPUs have overlapping CPUs, and / or the L I / O units 42 and T I / O units 42 have overlapping I / O units 42.

[0169] Among them, the second test device tested in the second test task and the third test device tested in the third test task are both... Figure 4 Item 5 being tested.

[0170] In this specification, the specific means of selecting the CPU can be by selecting an industrial control computer (i.e., an RTPC).

[0171] Specifically, there are multiple test tasks to be executed. These multiple test tasks can be performed on the same type of test device 5 or on different types of test devices 5. The multiple test tasks are arranged sequentially in the task queue.

[0172] In one example, if there are still test tasks to be executed in the task queue during the execution of the first test task, another test task, namely the second test task, is obtained from the task queue. If the CPUs currently in an idle state and the I / O units 42 currently in an idle state meet the test requirements of the second test task, J CPUs and M I / O units 42 corresponding to the second test task are determined based on the test requirement information of the second test task. The second test task is then executed using the J CPUs and M I / O units 42 to test another second device under test, so that the second device under test and the J CPUs can interact through the M I / O units 42. J and M are both arbitrary integers greater than or equal to 1. In this configuration, J CPUs and N CPUs are different CPUs among the CPUs of multiple industrial control computers 31, and L I / O units 42 and M I / O units 42 are different I / O units 42 among multiple I / O units 42. This means that during the execution of the first test task, CPUs and I / O units 42 not involved in the first test task can be selected to execute another second test task, thus achieving parallel execution of multiple test tasks. Furthermore, the multiple CPUs within a single industrial control computer 31 can be simultaneously divided for parallel execution of different test tasks. For example, the multiple CPUs in a single industrial control computer 31 can be divided into two CPU groups, each used to execute two different test tasks.

[0173] The second test task is a different test task from the first test task, and the second device under test (DUT) is a different DUT from the first DUT. The first test task and the second test task can be performed by the same user or different users. The process of determining the CPU, I / O unit 42 and performing tests for the second test task can be understood by referring to the relevant descriptions in other embodiments of this specification, and will not be repeated here.

[0174] As can be seen, other test tasks can be executed in parallel during the execution of the first test task, effectively ensuring the efficient execution of the test.

[0175] In another example, after the first test task is completed and the N CPUs and L I / O units 42 that executed the first test task are released, there are still test tasks to be executed in the task queue. Another test task, namely the third test task, is obtained from the task queue. Based on the test requirement information of the third test task, Z CPUs are selected from the currently idle CPUs and T I / O units 42 are selected from the currently idle I / O units 42. The third test task is then executed using the Z CPUs and T I / O units 42 to test the third device under test, so that the third device under test and the Z CPUs can interact through the T I / O units 42. Z and T are any integers greater than or equal to 1. Among them, Z CPUs and N CPUs have overlapping CPUs, and / or L I / O units 42 and T I / O devices have overlapping I / O units 42. That is, the released CPUs and I / O units 42 can be used to execute other test tasks.

[0176] The third test task is a test task different from the first test task. The third device under test (DUT) can be the first DUT or a different DUT. The first test task and the third test task can be performed by the same user or different users. The process of determining the CPU, I / O units and performing tests for the third test task can be understood by referring to the relevant descriptions in other embodiments of this specification, and will not be repeated here.

[0177] As can be seen, after the first test task is completed, the CPU, I / O unit 42, etc. used can be used to execute other test tasks, effectively ensuring the full and efficient utilization of resources.

[0178] The preferred embodiments of the present invention have been described in detail above, but it should be understood that, if necessary, aspects of the embodiments can be modified to utilize aspects, features, and concepts from various patents, applications, and publications to provide other embodiments.

[0179] In light of the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the claims should not be considered limited to the specific embodiments disclosed in the specification and claims, but should be understood to include all possible embodiments together with the full scope of equivalents enjoyed by these claims.

Claims

1. A test system, characterized by, The test system is a HIL system, which includes a shared memory unit and multiple devices; The shared memory unit includes: multiple memory operation subunits and multiple memories, with each memory operation subunit connected to at least one of the memories; The plurality of devices includes at least one real-time computing device and at least one I / O device, the I / O device being directly or indirectly connected to at least one device under test; both the real-time computing device and the I / O device are capable of generating operation instructions, the operation instructions indicating that a corresponding memory address needs to be operated; the devices transfer target data through the shared memory unit's operation on the memory; the target data includes data that needs to be transferred between the real-time computing device and the I / O device during HIL testing; any first memory operation subunit among the plurality of memory operation subunits is used for: Get the current operation command; When the current operation instruction is a first operation instruction for operating on the storage address of the first memory connected to the first memory operation subunit, the first target data corresponding to the first operation instruction is interacted with the first memory by executing the first operation instruction.

2. The testing system according to claim 1, characterized in that, The first memory operation subunit is also used for: When the current operation instruction is a second operation instruction for operating on the storage address of the second memory among the plurality of memories, the second operation instruction is sent to other memory operation sub-units other than the first memory operation sub-unit, so that the second operation instruction is eventually passed to the second memory operation sub-unit connected to the second memory, so that the second memory operation sub-unit can be used to execute the second operation instruction.

3. The testing system according to claim 2, characterized in that, The multiple memory operation subunits are cascaded in sequence; The first memory operation subunit is specifically used for: Receive the current operation instruction sent by the cascaded memory operation subunits; and / or: When the current operation instruction is the second operation instruction, the second operation instruction is sent to the cascaded memory operation subunit.

4. The testing system according to claim 3, characterized in that, Depending on the cascading order of the plurality of memory operation sub-units, the storage addresses of the memory corresponding to the plurality of memory operation sub-units increase or decrease sequentially. The first memory operation subunit is configured to, when the current operation instruction is the second operation instruction, compare the storage address to be operated by the second operation instruction with the storage address of the memory connected to the first memory operation subunit, determine whether to send the second operation instruction to the previous level memory operation subunit or the next level memory operation subunit, and then send it.

5. The testing system according to claim 2, characterized in that, The first memory operation subunit is specifically used for: When the current operation instruction is the second operation instruction, the second memory operation sub-unit is determined from the plurality of memory operation sub-units based on the second operation instruction; Among a number of preset transmission path information, the transmission path information between the first memory operation subunit and the second memory operation subunit is determined; Each of the transmission path information represents the path through which the operation instruction is transmitted from a port of one of the corresponding memory operation subunits to a port of another memory operation subunit; Based on the transmission path information between the first memory operation subunit and the second memory operation subunit, the second operation instruction is issued so that the second memory operation subunit can obtain and execute the second operation instruction.

6. The testing system according to claim 5, characterized in that, Any two memory operation subunits are directly connected through corresponding ports, and the plurality of transmission path information is a connection routing table that characterizes the connection relationship between the plurality of memory operation subunits.

7. The testing system according to claim 1, characterized in that, If there are multiple first operation instructions, the first memory operation subunit is further configured to compare the arrival order of the first operation instructions obtained from the device with the arrival order of the first operation instructions obtained from the memory operation subunit, and then execute them sequentially.

8. The testing system according to claim 1, characterized in that, The first memory operation subunit is used to sort the first operation instructions obtained from the device according to their arrival order; The first memory operation subunit is further configured to compare the sorted first operation instructions with the arrival order of the first operation instructions obtained from the memory operation subunit, and then execute them sequentially.

9. The testing system according to claim 1, characterized in that, If there are multiple first operation instructions, the first memory operation subunit is used to determine the arrival order of the multiple first operation instructions based on the timestamp of each first operation instruction.

10. The testing system according to claim 1, characterized in that, The current device that issues the current operation command is used for: If the current operation instruction is a write operation, before sending the current operation instruction to the memory operation subunit connected to the current device, it is determined whether the operation permission for the storage address operated by the current operation instruction has been successfully obtained; Upon successfully obtaining the operation permission, the current operation instruction is sent to the memory operation subunit to which the current device is connected; The operation permission is released when it is determined that the current operation instruction has been executed successfully or the amount of data written has reached the set amount of data to be written.

11. The testing system according to claim 1, characterized in that, The first memory operation subunit is configured to, after executing the first operation instruction for reading the first target data and reading the first target data from the first memory, use the read first target data as response data to feed back to the device that sent the first operation instruction.

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