A read-write method and circuit of a dual-port memory and a stacked memory

Abstract

The application discloses a read-write method and circuit of a dual-port memory and a stacked memory. The read-write method of the dual-port memory comprises the following steps: in response to the first port and the second port being enabled at the same time, it is judged whether there is a conflict between the processing signals received by the first port and the second port; and in response to the processing signals corresponding to the first port and the second port being in conflict, an operation matched with the processing signals is executed based on the priority of the first port and the second port. The application can improve the read-write operation efficiency of the dual-port memory.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a method, circuit, and stacked memory for reading and writing a dual-port memory. Background Technology

[0002] Static Random-Access Memory (SRAM) is a type of random access memory. Single-port SRAM can only perform read or write operations at a time, severely limiting device performance. Therefore, dual-port SRAM was proposed, which allows simultaneous read and write operations, significantly improving SRAM performance. However, dual-port SRAM is prone to read / write conflicts. Existing technologies avoid these conflicts by using internal signals of the dual-port SRAM array to perform logical checks in the environment to determine if a read / write conflict has occurred. If a conflict occurs, the read / write operation is discarded.

[0003] Therefore, current methods for handling read / write conflicts in dual-port memory discard too many read / write operations, resulting in low efficiency for read / write operations on dual-port memory. Summary of the Invention

[0004] In view of the above problems, the present invention proposes a method, circuit and stacked memory for reading and writing dual-port memory, which improves the reading and writing efficiency of dual-port memory.

[0005] In a first aspect, this application provides the following technical solution through an embodiment:

[0006] A read / write method for a dual-port memory includes: in response to both a first port and a second port being enabled simultaneously, determining whether there is a conflict between the processing signals received by the first port and the second port; and in response to the conflict between the processing signals corresponding to the first port and the second port, performing an operation matching the processing signal based on the priority of the first port and the second port.

[0007] Optionally, the step of determining whether there is a conflict between the processing signals received by the first port and the second port includes:

[0008] If both the first port and the second port receive a write signal, a conflict is determined based on the processing signals corresponding to the first port and the second port and the addresses of the processing signals.

[0009] Optionally, the step of determining whether a conflict exists based on the processing signals corresponding to the first port and the second port, and the addresses of the processing signals, includes:

[0010] Determine whether the addresses of the processing signals corresponding to the first port and the second port overlap; if the addresses of the processing signals corresponding to the first port and the second port overlap, and if the processing operations corresponding to the processing signals corresponding to the first port and the second port conflict, then determine that a conflict exists.

[0011] Optionally, the step of determining whether there is a conflict between the processing signals received by the first port and the second port includes:

[0012] If the processing signal received by the first port is read and the processing signal received by the second port is write, it is determined whether the addresses of the processing signals corresponding to the first port and the second port overlap; if the addresses of the processing signals corresponding to the first port and the second port overlap, it is determined that a conflict exists.

[0013] Optionally, the step of determining whether the addresses of the processing signals corresponding to the first port and the second port overlap includes:

[0014] Based on the bit width of the first port and the second port, determine whether the addresses of the processing signals corresponding to the first port and the second port overlap.

[0015] Optionally, the step of determining whether the addresses of the processing signals corresponding to the first port and the second port overlap based on the bit width of the first port and the second port includes:

[0016] Based on the bit width of the first port and the second port, the addresses of the processing signals of the first port and the second port are extended respectively to obtain the extended addresses of the first port and the second port respectively; based on the bit width of the first port and the second port, the comparison address is determined from the extended addresses of the first port and the second port respectively; it is determined whether the comparison address of the first port and the second port overlaps with the comparison address of the second port; in response to the overlap of the comparison address of the first port and the comparison address of the second port, it is determined that the addresses of the processing signals corresponding to the first port and the second port overlap.

[0017] Optionally, the step of responding to a conflict between the processing operations corresponding to the processing signals of the first port and the second port includes:

[0018] The address corresponding to the smaller bit width of the first port and the second port is determined as the cell address; the address corresponding to the larger bit width of the first port and the second port is determined as the reference address; the reference address corresponds to multiple memory segments, and the bit width of each memory segment is the same as the memory bit width of the cell address; based on the reference address and the cell address, a target memory segment is determined among the multiple memory segments; in response to the data in the target memory segment being different from the data in the cell address, it is determined that there is a conflict between the processing operations corresponding to the processing signals of the first port and the second port.

[0019] Optionally, the step of performing an operation matching the processing signal based on the priority of the first port and the second port includes:

[0020] Confirm the priorities of the first port and the second port respectively; perform operations based on the port with higher priority, and disable the ports with lower priority.

[0021] Optionally, after the step of determining whether there is a conflict between the processing signals received by the first port and the second port, the method further includes:

[0022] If the addresses of the processing signals corresponding to the first port and the second port overlap, and if the processing operations corresponding to the processing signals corresponding to the first port and the second port do not conflict, then a write operation is performed on the port with the larger bit width between the first port and the second port, and the port with the smaller bit width between the first port and the second port is disabled.

[0023] Optionally, the step of performing an operation matching the processing signal based on the priority of the first port and the second port includes:

[0024] If the priority of the first port is lower than the priority of the second port, and the bit width of the first port is smaller than the bit width of the second port, and the operation of the first port is a read operation while the operation of the second port is a write operation, then the data matching the processing signal of the second port is transmitted to the first port. If the priority of the first port is lower than the priority of the second port, and the bit width of the first port is greater than the bit width of the second port, and the operation of the first port is a read operation while the operation of the second port is a write operation, then the enable signal of the first port is delayed. If the priority of the first port is higher than the priority of the second port, then the enable signal of the second port is delayed.

[0025] Optionally, the step of determining whether there is a conflict between the processing signals received by the first port and the second port includes:

[0026] If both the processing signals corresponding to the first port and the second port are read, it is determined that there is no conflict between the processing signals received by the first port and the second port; wherein, if there is no conflict between the processing signals received by the first port and the second port, the read operation corresponding to the processing signal is executed.

[0027] Optionally, before the step of determining whether there is a conflict between the processing signals received by the first port and the second port, the method further includes:

[0028] In response to the first port being enabled, the current address corresponding to the first port is updated to the received first target address; or, in response to the first port being disabled, the address of the first port is kept unchanged based on the first address holding signal; in response to the second port being enabled, the current address corresponding to the second port is updated to the received second target address; or, in response to the second port being disabled, the address of the second port is kept unchanged based on the second address holding signal.

[0029] Secondly, based on the same inventive concept, this application provides the following technical solution through an embodiment:

[0030] A read / write circuit for a dual-port memory includes: a data analysis circuit, configured to determine whether there is a conflict between the processing signals received by the first port and the second port when both the first port and the second port are enabled simultaneously; and an output processing circuit, configured to perform an operation matching the processing signals based on the priority of the first port and the second port when there is a conflict between the processing signals corresponding to the first port and the second port.

[0031] Optionally, the data analysis circuit includes:

[0032] The first sub-analysis circuit is configured to determine whether a conflict exists based on the processing signals corresponding to the first port and the second port and the addresses of the processing signals, in response to both the processing signals received by the first port and the second port being write signals.

[0033] Optionally, the first sub-analysis circuit is also used for:

[0034] Determine whether the addresses of the processing signals corresponding to the first port and the second port overlap; if the addresses of the processing signals corresponding to the first port and the second port overlap, and if the processing operations corresponding to the processing signals corresponding to the first port and the second port conflict, then determine that a conflict exists.

[0035] Optionally, the data analysis circuit further includes a second sub-analysis circuit for:

[0036] If the processing signal received by the first port is read and the processing signal received by the second port is write, it is determined whether the addresses of the processing signals corresponding to the first port and the second port overlap; if the addresses of the processing signals corresponding to the first port and the second port overlap, it is determined that a conflict exists.

[0037] Optionally, either the first sub-analysis circuit or the second sub-analysis circuit is also used for:

[0038] Based on the bit width of the first port and the second port, determine whether the addresses of the processing signals corresponding to the first port and the second port overlap.

[0039] Optionally, both the first sub-analysis circuit and the second sub-analysis circuit include:

[0040] The comparison address determination subcircuit is used to expand the addresses of the processing signals of the first port and the second port respectively based on the bit width of the first port and the second port to obtain the expanded addresses of the first port and the second port respectively; and to determine the comparison address from the expanded addresses of the first port and the second port respectively based on the bit width of the first port and the second port. The address conflict judgment subcircuit is used to determine whether the comparison address of the first port and the comparison address of the second port overlap; and to determine that the addresses of the processing signals corresponding to the first port and the second port overlap if the comparison address of the first port and the comparison address of the second port overlap.

[0041] Optionally, the first sub-analysis circuit further includes:

[0042] A cell address determination subcircuit is used to determine the address corresponding to the smaller bit width of the first port and the second port as the cell address; a reference address determination subcircuit is used to determine the address corresponding to the larger bit width of the first port and the second port as the reference address; the reference address corresponds to multiple memory segments, and the bit width of each memory segment is the same as the memory bit width of the cell address; a data conflict judgment subcircuit is used to determine a target memory segment among the multiple memory segments based on the reference address and the cell address; in response to the data in the target memory segment being different from the data in the cell address, it is determined that there is a conflict between the processing operations corresponding to the processing signals of the first port and the second port.

[0043] Optionally, the output processing circuit includes: a first processing sub-circuit, used for:

[0044] Confirm the priorities of the first port and the second port respectively; perform operations based on the port with higher priority, and disable the ports with lower priority.

[0045] Optionally, the output processing circuit includes: a second processing sub-circuit, configured after the step of determining whether there is a conflict between the processing signals received by the first port and the second port:

[0046] If the addresses of the processing signals corresponding to the first port and the second port overlap, and if the processing operations corresponding to the processing signals corresponding to the first port and the second port do not conflict, and if the processing operations corresponding to the first port and the second port are both write operations, then a write operation is performed on the port with the larger bit width among the first port and the second port, and the port with the smaller bit width among the first port and the second port is disabled.

[0047] Optionally, the output processing circuit further includes: a third processing sub-circuit, used for:

[0048] If the priority of the first port is lower than the priority of the second port, and the bit width of the first port is smaller than the bit width of the second port, and the operation of the first port is a read operation while the operation of the second port is a write operation, then the data matching the processing signal of the second port is transmitted to the first port. If the priority of the first port is lower than the priority of the second port, and the bit width of the first port is greater than the bit width of the second port, and the operation of the first port is a read operation while the operation of the second port is a write operation, then the enable signal of the first port is delayed. If the priority of the first port is higher than the priority of the second port, then the enable signal of the second port is delayed.

[0049] Optionally, the data analysis circuit includes a third sub-analysis circuit; the output processing circuit further includes a fourth processing sub-circuit.

[0050] The third sub-analysis circuit is used to determine that there is no conflict between the processing signals received by the first port and the second port when both processing signals corresponding to the first port and the second port are read; the fourth processing sub-circuit is used to execute the read operation corresponding to the processing signal when there is no conflict between the processing signals received by the first port and the second port.

[0051] Optionally, it also includes: an address update circuit, used for:

[0052] In response to the first port being enabled, the current address corresponding to the first port is updated to the received first target address; or, in response to the first port being disabled, the address of the first port is kept unchanged based on the first address holding signal; in response to the second port being enabled, the current address corresponding to the second port is updated to the received second target address; or, in response to the second port being disabled, the address of the second port is kept unchanged based on the second address holding signal.

[0053] Thirdly, based on the same inventive concept, this application provides the following technical solution through an embodiment:

[0054] A stacked memory, characterized in that it comprises: a storage unit, the storage unit including the read / write circuit of the dual-port memory in the second aspect mentioned above; and a logic unit, the logic unit being stacked with the storage unit and three-dimensionally heterogeneously integrated.

[0055] The beneficial effects of the multiple embodiments provided by the present invention are that when the first port and the second port are enabled at the same time, it is first determined whether there is a conflict between the processing signals of the two ports; if there is a conflict, the operation matching the processing signal is executed based on priority, which avoids directly discarding the current operation when there is a conflict between the processing signals of the two ports, thereby improving the read and write operation efficiency of the dual-port memory.

[0056] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0058] Figure 1 A flowchart illustrating a read / write method for a dual-port memory provided in an embodiment of the present invention is shown;

[0059] Figure 2 A schematic diagram of the read / write circuit of a dual-port memory provided in an embodiment of the present invention is shown;

[0060] Figure 2A A schematic diagram of the structure of the first sub-analysis circuit in an embodiment of the present invention is shown;

[0061] Figure 3 A schematic diagram of the address conflict judgment sub-circuit in an embodiment of the present invention is shown;

[0062] Figure 4 The circuit schematic diagram for determining the maximum bit width in a dual-port circuit is shown in an embodiment of the present invention.

[0063] Figure 5 A schematic diagram of the data conflict judgment sub-circuit in an embodiment of the present invention is shown;

[0064] Figure 6 A schematic diagram of the address update circuit in an embodiment of the present invention is shown;

[0065] Figure 7 A schematic diagram of a stacked memory provided in an embodiment of the present invention is shown. Detailed Implementation

[0066] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0067] This invention provides a read / write method for a dual-port memory, applicable to dual-port memories (hereinafter referred to as memories for ease of description). For example, a separate circuit module can be set up in the memory to implement the dual-port memory read / write method, or the circuit structure implementing the dual-port memory read / write method can be integrated into the main control chip of the dual-port memory, without limitation. The dual-port memory includes at least a first port and a second port. When both ports of the dual-port memory are enabled simultaneously, the dual-port memory read / write method can be executed to avoid conflicts during read and write operations and ensure correct handling of read and write operations under different conditions.

[0068] Please see Figure 1 , Figure 1 A flowchart illustrating a read / write method for a dual-port memory provided in an embodiment of the present invention is shown. The read / write method for the dual-port memory includes:

[0069] Step S10: In response to the simultaneous enabling of the first port and the second port, determine whether there is a conflict between the processing signals received by the first port and the second port;

[0070] Step S20: In response to a conflict between the processing signals corresponding to the first port and the second port, an operation matching the processing signal is performed based on the priority of the first port and the second port.

[0071] The dual-port memory read / write method of this embodiment, when both the first and second ports are enabled simultaneously, first determines whether there is a conflict between the processing signals of the two ports; if a conflict exists, the operation matching the processing signal is executed based on priority. This method avoids directly discarding the current operation when there is a conflict between the processing signals of the two ports, thus improving the read / write efficiency of the dual-port memory. The specific implementation of each step of the method in this embodiment will be described and explained in detail below.

[0072] Step S10: In response to the simultaneous enabling of the first port and the second port, determine whether there is a conflict between the processing signals received by the first port and the second port.

[0073] In step S10, after both the first port and the second port are enabled simultaneously, they will receive corresponding processing signals. The processing signals received by the first port and the second port may include: both the first port's processing signal and the second port's processing signal are read operations; both the first port's processing signal and the second port's processing signal are write operations; and the first port's processing signal is a read operation and the second port's processing signal is a write operation. The port conflict determination process for each case is as follows:

[0074] 1. The processing signals of the first port and the processing signals of the second port are both read operations.

[0075] When a conflict is detected, if both the processing signals corresponding to the first port and the second port are read, it is determined that there is no conflict between the processing signals received by the first port and the second port. Furthermore, since there is no conflict between the processing signals received by the first port and the second port, the read operation corresponding to the processing signal is executed. In other words, both ports perform read operations on the data in the memory, without modifying the data; therefore, the processing signals received by the first port and the second port will not conflict.

[0076] In this case, no processing is performed on the processing signals. Data, addresses, and control signals are output according to the processing signals of the two ports respectively, and read operations can be performed in the memory according to the address corresponding to the processing signal.

[0077] 2. The processing signals of the first port and the processing signals of the second port are both write operations.

[0078] In some implementations, if both the first port and the second port receive a write signal, a conflict is determined based on the corresponding processing signals and their addresses. The address of the processing signal is the address of the data stored in the memory corresponding to the operation of that signal.

[0079] Furthermore, it can be first determined whether the addresses of the processing signals corresponding to the first port and the second port overlap; then, in response to the overlap of the addresses of the processing signals corresponding to the first port and the second port, and in response to the conflict of the processing operations corresponding to the processing signals corresponding to the first port and the second port, it is determined that a conflict exists.

[0080] Here, the processing signals correspond to write operations performed on their respective data. In this embodiment, if the addresses of the processing signals overlap, the current operation is not discarded; instead, a further judgment is made to determine whether there is a conflict in the write operations performed on the respective data. If there is no conflict, the write operations corresponding to the two ports can continue to be executed; if there is a conflict, step S20 is executed. That is, when the addresses of the processing signals corresponding to the first port and the second port overlap and the write operations also conflict, step S20 is executed.

[0081] In some implementations, the overlap of the addresses of the processing signals corresponding to the first and second ports can be determined based on their bit widths. Understandably, the bit widths of the two ports may be the same or different. Whether the bit widths of the two ports are the same or different, the addresses of the processing signals corresponding to the two ports can be compared to see if they overlap. If they overlap, the addresses of the processing signals corresponding to the two ports are considered to conflict; otherwise, it is determined that there is no conflict.

[0082] Furthermore, this embodiment includes the following specific address conflict determination methods:

[0083] One way to determine address conflicts is:

[0084] First, based on the bit widths of the first and second ports, the addresses of the processing signals of each port are extended to obtain their respective extended addresses. It's understandable that the addresses of the processing signals corresponding to each port can be extended to a preset length. This preset length can be determined by the bit widths of the two ports; for example, the memory ports are port A and port B. Let the bit width of port A be data_wa, and the highest bit of the address of the port's processing signals (hereinafter referred to as the port address for brevity) be addr_a; let the bit width of port B be data_wb, and the highest bit of port B's address be addr_b. Then, the extended address of port A corresponds to addr_a + log2data_wa bits, padded in the low-order bits with a padded value of 0; the extended address of port B corresponds to addr_b + log2data_wb bits, padded in the low-order bits with a padded value of 0. Thus, the extended addresses of the two ports are obtained, and since the two extended addresses have the same bit width, comparison is convenient.

[0085] For example, in a specific example, a memory has a capacity of 1024 bits, port A has a bit width of 8 bits, and port B has a bit width of 4 bits. Then, from 1024 = 8 × 128 = 4 × 256, we know that the address bit width of port A is 7 bits (log₂128), and the address bit width of port B is 8 bits (log₂256). If the address of port A is 0000101 and the address of port B is 00001011, then the corresponding extended address of port A is 0000101. 000 (The underscores are padding 0s), the extended address of port B is 00001011. 00 .

[0086] Then, based on the bit widths of the first and second ports, the comparison address is determined from the extended addresses of each port. Specifically, the extended address of the port with the larger bit width can be used as a reference to determine the comparison address of each port.

[0087] Finally, it is determined whether the comparison addresses of the first port and the second port overlap. This is done by sequentially comparing each bit of the comparison addresses of the two ports; if they are the same, it is determined that the comparison addresses of the two ports overlap. In this case, since the comparison addresses of the first port and the second port overlap, it is determined that the addresses of the processing signals corresponding to the first port and the second port overlap, which will cause a conflict.

[0088] Continuing with the example above, if the bit width of port A is greater than that of port B, then bits (addr_a + log2data_wa) to (log2data_wa) + 1 of the extended address of both ports can be used as the comparison address. That is, compare bits (addr_a + log2data_wa) to (log2data_wa) + 1 of the extended address of port A with bits (addr_a + log2data_wa) to (log2data_wa) + 1 of port B. This allows for the comparison of two addresses of different lengths, thus accurately determining whether the shorter address overlaps with the longer address. For example, if the extended address of port A is 0000101... 000 The extended address of port B is 00001011 00 When comparing, the 10th to 4th bits of the address of port A are used, which is 0000101 in the extended address of port A. and Are the extended address 0000101 of port B the same?

[0089] Furthermore, after the addresses of the two ports overlap, a process is initiated to determine whether write data conflicts occur, specifically whether write operations corresponding to the two ports conflict. The implementation is as follows:

[0090] First, the address corresponding to the smaller bit width between the first port and the second port is determined as the cell address. Then, the address corresponding to the larger bit width between the first port and the second port is determined as the base address; the base address corresponds to multiple memory segments, and the bit width of each memory segment is the same as the memory bit width of the cell address.

[0091] Then, based on the reference address and the cell address, a target storage segment is determined from the plurality of storage segments; it is determined whether the data in the target storage segment is the same as the data in the cell address; in response to the data in the target storage segment being different from the data in the cell address, it is determined that there is a conflict between the processing operations corresponding to the processing signals of the first port and the second port; otherwise, it is determined that there is no conflict between the processing operations corresponding to the processing signals of the first port and the second port. When a write conflict is determined to occur, step S20 can be executed. It can be understood that in response to the overlapping addresses of the processing signals corresponding to the first port and the second port, and in response to the lack of conflict between the processing operations corresponding to the processing signals of the first port and the second port, an operation matching the processing signal is executed based on the bit width of the first port and the second port. Specifically, a write operation is performed on the port with the larger bit width between the first port and the second port, and the port with the smaller bit width between the first port and the second port is disabled. By first determining the address conflict and then determining the write operation conflict, when there is an address conflict but no write operation conflict, more write operations can be executed normally, avoiding excessive discarding of write operations and reducing write efficiency.

[0092] Continuing with the previous example, the memory ports are port A and port B. Let the bit width of port A be data_wa, and the bit width of port B be data_wb. First, determine the data bit width of ports A and B. If the port with the larger data bit width is selected, choose port A. Calculate the value of bits log2data_wa to (log2data_wb)+1 in the address of port B, denoted as N. This locates the target memory segment, which is bits (data_wb)×N to [(data_wb)×(N+1)]-1 in the address of port A. Then, compare the write data in bits (data_wb)×N to [(data_wb)×(N+1)]-1 in the address of port A with the write data in port B, where N is a positive integer. If the data in bits (data_wb)×N to [(data_wb)×(N+1)]-1 of the address of the processing signal at port A is exactly the same as the write data at port A, then the processing operation corresponding to the processing signal is determined to be conflict-free; otherwise, the processing operation corresponding to the processing signal is determined to be conflict-free. In other words, since the same data is written to both the address of the processing signal at port A and the address of the processing signal at port B, even if there is a conflict between the addresses of the processing signals at ports A and B, it will not affect the final write operation result.

[0093] Suppose that the extended address of port A is 0000101000 and the extended address of port B is 0000101100, then the values ​​of bits log2data_wa to (log2data_wb)+1 in the extended address of port B are the values ​​of bits 3 to 3, which is 1 for bit 3. In this case, the target memory segment in the extended address of port A is bits (data_wb)×N to [(data_wb)×(N+1)]-1, i.e., bits 4 to 7. Therefore, the data in the address of port B is compared with bits 4 to 7 in the address of port A, as shown in the diagram below. If each bit is exactly the same, it is determined that there is no conflict in the processing operation corresponding to the processing signal; otherwise, it is determined that there is a conflict in the processing operation corresponding to the processing signal.

[0094] Storage bits of port address A

[0095] 0 1 2 3 4 5 6 7

[0096] 0 1 2 3

[0097] Storage bits of port B address

[0098] By using one or more of the above implementation methods, when there is an address conflict when writing data, it will further determine whether there is a conflict in the writing data itself; then, based on the judgment result, step S20 will be performed, and the write operation will not be discarded after determining that there is an address or data conflict, thus improving the efficiency of the write operation.

[0099] 3. The processing signal for the first port is a read operation, and the processing signal for the second port is a write operation.

[0100] In other words, if the processing signal received at the first port is "read" and the processing signal received at the second port is "write," then it is determined whether the addresses of the corresponding processing signals at the first and second ports overlap. In some implementations, the overlap can be determined based on the bit width of the first and second ports. This determination process can be referred to the explanation in the second case above, and will not be repeated here. If the addresses of the corresponding processing signals at the first and second ports overlap, a conflict is determined. When a conflict is determined, step S20 is executed.

[0101] Step S20: In response to a conflict between the processing signals corresponding to the first port and the second port, an operation matching the processing signal is performed based on the priority of the first port and the second port.

[0102] In step S20, the priorities of the first port and the second port can be preset. For example, a separate preset priority signal can be given to the processing circuit executing this step to specify the port priority. Alternatively, the priorities of the first port and the second port can be carried by processing signals without restriction. When the processing signals of the two ports conflict, the operation matching the processing signal is executed, which can be categorized as follows:

[0103] 1. When the processing signals of the first port and the second port are both in write operation state, only address conflict occurs.

[0104] Understandably, if the addresses of the processing signals corresponding to the first and second ports overlap, and the processing operations corresponding to these signals do not conflict, then the operation matching the processing signal is executed based on the bit width of the first and second ports. Specifically, a port with a larger bit width will occupy more storage bits for one address; with the same number of storage bits, a port with a smaller bit width will correspond to more addresses. Therefore, the port with the smaller data bit width can be disabled, and operations can be performed only on the port with the larger data bit width. In this case, the operations on the processing signals of both ports can be completed, avoiding data loss.

[0105] 2. When both the processing signals of the first port and the processing signals of the second port are write operations, and an address conflict and a data conflict occur.

[0106] Understandably, the priorities of the first and second ports can be confirmed. Port priorities can be configured based on specific application scenarios. For example, when applied to processors with large bit widths, the priority of ports with larger bit widths can be configured higher, and the priority of ports with smaller bit widths lower, improving data processing efficiency. When applied to processors with small bit widths, the priority of ports with smaller bit widths can be configured higher, and the priority of ports with larger bit widths lower, to avoid data queuing due to the processor's inability to complete processing in a timely manner after data is read. Then, write operations are performed on the higher-priority ports, while the lower-priority ports are disabled. This ensures that at least one higher-priority port's processing signal is correctly executed, avoiding the discarding of both processing signals and improving processing efficiency.

[0107] 3. The processing signal received by the first port is for reading, and the processing signal received by the second port is for writing.

[0108] In some implementations, if the priority of the first port is lower than that of the second port, and the bit width of the first port is smaller than that of the second port, then the data matching the processing signal of the second port is transmitted to the first port to complete the read operation of the processing signal of the first port. It is understandable that if the write port has a higher priority than the read port, and the data bit width of the write port is larger than that of the read port, then the relevant part of the written data is directly sent to the read data signal corresponding to the port.

[0109] In some implementations, the enable signal of the first port is delayed if the priority of the first port is lower than that of the second port and if the bit width of the first port is greater than that of the second port; and the enable signal of the second port is delayed if the priority of the first port is higher than that of the second port.

[0110] The above control method enables the higher-priority port to write data and the lower-priority port to read data, thus avoiding conflicts during actual execution and preventing the discarding of the processing signal of the current operation.

[0111] In some implementations, the enable signal of the second port is delayed in response to the fact that the priority of the first port is higher than that of the second port. That is, if the read port priority is higher than the write port priority, the write enable signal is delayed; furthermore, the delay of the write enable signal can be controlled to be equal to the SRAM cell read time of the memory, thus ensuring that the write operation is performed only after the data read is completed.

[0112] In this embodiment, conflicts between the address and data corresponding to the processing signal are identified sequentially. In cases of address conflicts, further data conflict assessment is performed. Operations are then performed based on a preset priority for each situation, ensuring appropriate operation even in the event of signal conflicts. This avoids discarding processing signals and improves read / write efficiency.

[0113] In some embodiments of the present invention, address holding processing logic can be added to improve read and write efficiency. This eliminates the need for frequent address updates when operating on the same address; that is, when the addresses corresponding to the processing signals of the two ports do not change, an address holding signal can be generated to maintain the addresses of the two ports unchanged. Specifically, in response to enabling the first port, the current address corresponding to the first port is updated to the received first target address; or, in response to disabling the first port, the address of the first port is kept unchanged based on the first address holding signal; in response to enabling the second port, the current address corresponding to the second port is updated to the received second target address; or, in response to disabling the second port, the address of the second port is kept unchanged based on the second address holding signal.

[0114] Please see Figure 2 In another embodiment of the present invention, a read / write circuit 30 for a dual-port memory is also provided. This read / write circuit 30 can be used to implement the methods described in the foregoing embodiments. The read / write circuit includes:

[0115] The data analysis circuit 31 is used to determine whether there is a conflict between the processing signals received by the first port and the second port when the first port and the second port are enabled at the same time.

[0116] The output processing circuit 32 is configured to, in response to a conflict between the processing signals corresponding to the first port and the second port, perform an operation matching the processing signal based on the priority of the first port and the second port.

[0117] As an optional implementation, the data analysis circuit 31 includes:

[0118] The first sub-analysis circuit 311 is configured to determine whether a conflict exists based on the processing signals corresponding to the first port and the second port and the addresses of the processing signals, in response to the fact that both the processing signals received by the first port and the second port are write signals.

[0119] As an optional implementation, the first sub-analysis circuit 311 is further configured to:

[0120] Determine whether the addresses of the processing signals corresponding to the first port and the second port overlap;

[0121] If the addresses of the processing signals corresponding to the first port and the second port overlap, and if the processing operations corresponding to the processing signals corresponding to the first port and the second port conflict, then a conflict is determined to exist.

[0122] As an optional implementation, the data analysis circuit 31 further includes a second sub-analysis circuit 312, used for:

[0123] If the processing signal received by the first port is read and the processing signal received by the second port is write, then it is determined whether the addresses of the processing signals corresponding to the first port and the second port overlap.

[0124] If the addresses of the processing signals corresponding to the first port and the second port overlap, a conflict is determined to exist.

[0125] As an optional implementation, either the first sub-analysis circuit 311 or the second sub-analysis circuit 312 is further used for:

[0126] Based on the bit width of the first port and the second port, determine whether the addresses of the processing signals corresponding to the first port and the second port overlap.

[0127] Please see Figure 2A As an optional implementation, both the first sub-analysis circuit 311 and the second sub-analysis circuit 312 include:

[0128] The comparison address determination sub-circuit 3111 is used to expand the addresses of the processed signals of the first port and the second port respectively based on the bit width of the first port and the second port to obtain the expanded addresses of the first port and the second port respectively.

[0129] Address conflict determination sub-circuit 3112 is used to determine whether the comparison address of the first port and the comparison address of the second port overlap; in response to the overlap of the comparison address of the first port and the comparison address of the second port, it is determined that the addresses of the processing signals corresponding to the first port and the second port overlap.

[0130] Please see Figure 3 Let's continue with the example of ports A and B from the previous example. Figure 3 A specific implementation of the address conflict judgment sub-circuit 3112 is given. The bit width of the comparison address is 8 bits. Before determining the extended address, a selector can be used to select the larger data bit width between the two ports, such as... Figure 4 As shown, the comparison address is determined based on the maximum data bit width.

[0131] Address conflict judgment subcircuit 3112 includes address comparison subcircuit 1121 and first result processing subcircuit 1122. The number of address comparison subcircuit 1121 is the same as the bit width of the comparison address, allowing each bit to be judged. The first result processing subcircuit 1122 is used to compare whether the judgment results of each bit are the same and outputs an address coincidence signal. For example, each address comparison subcircuit 1121 may include an XOR gate and a selector. The two inputs of an XOR gate are respectively input to the A port address and B port address with the same bit width. The selector outputs 1 when the A port address and B port address are the same, and outputs 0 otherwise. The first result processing subcircuit 1122 may include multiple cascaded AND gates. The AND gates located at the inputs of the first result processing subcircuit 1122 are respectively connected to the outputs of a selector, and the AND gates located at the outputs of the first result processing subcircuit 1122 are connected to a NOT gate, thereby outputting an address coincidence signal.

[0132] As an optional implementation, the first sub-analysis circuit 311 further includes:

[0133] The cell address determination sub-circuit 3113 is used to determine the address corresponding to the smaller bit width between the bit width of the first port and the bit width of the second port as the cell address;

[0134] The reference address bit determination sub-circuit 3114 is used to determine the address corresponding to the larger bit width between the bit width of the first port and the bit width of the second port as the reference address; the reference address corresponds to multiple memory segments, and the bit width of each memory segment is the same as the storage bit width of the cell address;

[0135] The data conflict determination sub-circuit 3115 is used to determine a target storage segment among the plurality of storage segments based on the reference address and the cell address; in response to the data in the target storage segment being different from the data in the cell address, it is determined that there is a conflict between the processing operations corresponding to the processing signals of the first port and the second port.

[0136] Please see Figure 5 Continuing with the example of ports A and B from the previous example, a specific implementation of a data conflict judgment subcircuit 3115 is given. Port A has an 8-bit data width, and port B has a 4-bit data width. The data conflict judgment subcircuit 3115 may include: a data comparison subcircuit 1151 and a second result processing subcircuit 1152. The number of data comparison subcircuits 1151 is the same as the data width of port A, ensuring that each bit of data can be judged. The second result processing subcircuit is used to determine whether the memory segment of port A that matches port B contains the exact same data as the corresponding memory segment of port B. If not, a write-write conflict signal is output. For example, each data comparison subcircuit 1151 may include an XOR gate and a selector. The two inputs of an XOR gate are respectively input to the data of port A and port B. The second result processing subcircuit may include multiple cascaded AND gates. The AND gates located at the inputs of the second result processing subcircuit are respectively connected to the outputs of a selector, and the AND gates located at the outputs of the second result processing subcircuit output a write-write conflict signal indicating whether data exists.

[0137] As an optional implementation, the output processing circuit 32 includes: a first processing sub-circuit, used for:

[0138] Confirm the priorities of the first port and the second port respectively;

[0139] Write operations are performed on the higher-priority ports, while the lower-priority ports are disabled.

[0140] As an optional implementation, the output processing circuit 32 further includes: a second processing sub-circuit, configured to: after determining whether there is a conflict between the processing signals received by the first port and the second port: in response to the overlapping addresses of the processing signals corresponding to the first port and the second port, and in response to the absence of a conflict between the processing operations corresponding to the processing signals corresponding to the first port and the second port, perform a write operation on the port with the larger bit width among the first port and the second port, and disable the port with the smaller bit width among the first port and the second port.

[0141] As an optional implementation, the output processing circuit 32 further includes: a third processing sub-circuit, used for:

[0142] If the priority of the first port is lower than that of the second port, and the bit width of the first port is less than that of the second port, then the data matching the processing signal of the second port is transmitted to the first port; if the priority of the first port is lower than that of the second port, and the bit width of the first port is greater than that of the second port, then the enable signal of the first port is delayed; if the priority of the first port is higher than that of the second port, then the enable signal of the second port is delayed.

[0143] As an optional implementation, the data analysis circuit 31 includes a third sub-analysis circuit 313; the output processing circuit 32 further includes a fourth processing sub-circuit.

[0144] The third sub-analysis circuit 313 is used to determine that there is no conflict between the processing signals received by the first port and the second port when both the processing signals corresponding to the first port and the second port are read.

[0145] The fourth processing sub-circuit is used to execute the read operation corresponding to the processing signal if there is no conflict between the processing signals received by the first port and the second port.

[0146] As an optional implementation, it also includes: an address update circuit 33, used for:

[0147] In response to the first port being enabled, the current address corresponding to the first port is updated to the received first target address; or, in response to the first port being disabled, the address of the first port is kept unchanged based on the first address holding signal.

[0148] In response to the second port being enabled, the current address corresponding to the second port is updated to the received second target address; or, in response to the second port being disabled, the address of the second port is kept unchanged based on the second address hold signal.

[0149] Please see Figure 6 Let's continue with the example of ports A and B from the previous example. Figure 5 A specific implementation of the address update circuit 33 is given, which can be used to implement both port A and port B. The address update circuit 33 includes: a control signal generation sub-circuit 331, a selection sub-circuit 332, and a trigger sub-circuit 333.

[0150] The control signal generation sub-circuit 331 receives address holding signals (such as a first address holding signal or a second address holding signal) and port enable signals (such as port A enable signal and port B enable signal), and generates a control signal based on the received address holding signals and port enable signals. This control signal is used to control the output of the selection sub-circuit 332. For example, the control signal generation sub-circuit 331 can be composed of a NOT gate and an AND gate; the address holding signal is processed by the NOT gate and then input to one input terminal of the AND gate, and the port enable signal is input to the other input terminal of the AND gate, so that the output terminal of the AND gate outputs the control signal.

[0151] The selection sub-circuit 332 is used to select the port address to be output to the trigger sub-circuit 333. For example, the selection sub-circuit 332 can be implemented by a 2-to-1 selector; the input terminals of the selector are respectively input to the port address corresponding to the current operation (e.g., the address of port A or the read address of port B) and the port address at the time of the previous operation; when the port enable signal received by the control signal generation sub-circuit 331 is valid, the selector outputs the port address corresponding to the current operation.

[0152] The trigger sub-circuit 333 is used to trigger the port address of the output selector input based on the received clock signal corresponding to the port. For example, the trigger sub-circuit 333 can be implemented by a flip-flop.

[0153] Please see Figure 7 In another embodiment of the present invention, a stacked memory 60 is also provided, comprising: a memory unit 61, the memory unit 61 including the read / write circuit 30 of the dual-port memory in the foregoing embodiment; and a logic unit 62, the logic unit 62 being stacked with the memory unit 61 and three-dimensionally heterogeneously integrated, such as... Figure 7 The connecting part 63 is shown.

[0154] In summary, the beneficial effects of the various embodiments provided by the present invention are as follows: when the first port and the second port are enabled at the same time, it is first determined whether there is a conflict between the processing signals of the two ports; if there is a conflict, the operation matching the processing signal is executed based on priority, which avoids directly discarding the current operation when there is a conflict between the processing signals of the two ports, thereby improving the read and write operation efficiency of the dual-port memory.

[0155] It should be noted that the implementation circuits listed above are not the only implementations of this embodiment. They may also have conventional variations or optimized equivalent circuits with the same function, and there are no limitations. Furthermore, the specific implementations and technical effects of the dual-port memory read / write circuit and the stacked memory in this embodiment are the same as those in the aforementioned method embodiments. For the sake of brevity, any parts not mentioned in the device embodiment section can be referred to the corresponding content in the aforementioned method embodiments.

[0156] The term "and / or" as used herein is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects are in an "or" relationship; the word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of multiple such elements. This invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims listing several means, several of these means can be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0157] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0158] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0159] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0160] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0161] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0162] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for reading and writing a dual-port memory, characterized in that, include: In response to the simultaneous enabling of the first port and the second port, it is determined whether there is a conflict between the processing signals received by the first port and the second port; If there is a conflict between the processing signals corresponding to the first port and the second port, an operation matching the processing signal is performed based on the priority of the first port and the second port. The step of responding to a conflict between the processing operations corresponding to the processing signals of the first port and the second port includes: The address corresponding to the smaller bit width between the first port and the second port is determined as the cell address; The address corresponding to the larger bit width between the first port and the second port is determined as the base address; the base address corresponds to multiple memory segments, and the bit width of each memory segment is the same as the memory bit width of the cell address; Based on the reference address and the cell address, a target storage segment is determined from the plurality of storage segments; If the data in the target storage segment is different from the data in the cell address, it is determined that there is a conflict between the processing operations corresponding to the processing signals of the first port and the second port.

2. The read / write method according to claim 1, characterized in that, The step of determining whether there is a conflict between the processing signals received by the first port and the second port includes: If both the first port and the second port receive a write signal, a conflict is determined based on the processing signals corresponding to the first port and the second port and the addresses of the processing signals.

3. The read / write method according to claim 2, characterized in that, The step of determining whether a conflict exists based on the processing signals corresponding to the first port and the second port, and the addresses of the processing signals, includes: Determine whether the addresses of the processing signals corresponding to the first port and the second port overlap; If the addresses of the processing signals corresponding to the first port and the second port overlap, and if the processing operations corresponding to the processing signals corresponding to the first port and the second port conflict, then a conflict is determined to exist.

4. The read / write method according to claim 1, characterized in that, The step of determining whether there is a conflict between the processing signals received by the first port and the second port includes: If the processing signal received by the first port is read and the processing signal received by the second port is write, then it is determined whether the addresses of the processing signals corresponding to the first port and the second port overlap. If the addresses of the processing signals corresponding to the first port and the second port overlap, a conflict is determined to exist.

5. The read / write method according to claim 3 or 4, characterized in that, The step of determining whether the addresses of the processing signals corresponding to the first port and the second port overlap includes: Based on the bit width of the first port and the second port, determine whether the addresses of the processing signals corresponding to the first port and the second port overlap.

6. The read / write method according to claim 5, characterized in that, The step of determining whether the addresses of the processing signals corresponding to the first port and the second port overlap based on the bit width of the first port and the second port includes: Based on the bit width of the first port and the second port, the addresses of the processed signals of the first port and the second port are extended respectively to obtain the extended addresses of the first port and the second port respectively; Based on the bit width of the first port and the second port, the comparison address is determined from the extended address of each of the first port and the second port; Determine whether the comparison addresses of the first port and the second port overlap; If the comparison address of the first port and the comparison address of the second port coincide, it is determined that the addresses of the processing signals corresponding to the first port and the second port coincide.

7. The read / write method according to claim 3, characterized in that, The step of performing an operation matching the processing signal based on the priority of the first port and the second port includes: Confirm the priorities of the first port and the second port respectively; Write operations are performed on the higher-priority ports, while the lower-priority ports are disabled.

8. The read / write method according to claim 3, characterized in that, After the step of determining whether there is a conflict between the processing signals received by the first port and the second port, the method further includes: If the addresses of the processing signals corresponding to the first port and the second port overlap, and if the processing operations corresponding to the processing signals corresponding to the first port and the second port do not conflict, then a write operation is performed on the port with the larger bit width between the first port and the second port, and the port with the smaller bit width between the first port and the second port is disabled.

9. The read / write method according to claim 4, characterized in that, The step of performing an operation matching the processing signal based on the priority of the first port and the second port includes: In response to the fact that the priority of the first port is lower than that of the second port, and in response to the fact that the bit width of the first port is smaller than that of the second port, the data of the processing signal corresponding to the second port is transmitted to the first port. If the priority of the first port is lower than that of the second port, and if the bit width of the first port is greater than that of the second port, then the enable signal of the first port is delayed. In response to the fact that the priority of the first port is higher than that of the second port, the enable signal of the second port is delayed.

10. The read / write method according to claim 1, characterized in that, The step of determining whether there is a conflict between the processing signals received by the first port and the second port includes: If both the processing signals corresponding to the first port and the second port are read, it is determined that there is no conflict between the processing signals received by the first port and the second port. If there is no conflict between the processing signals received by the first port and the second port, then the read operation corresponding to the processing signal is executed.

11. The read / write method according to claim 1, characterized in that, Before the step of determining whether there is a conflict between the processing signals received by the first port and the second port, the method further includes: In response to the first port being enabled, the current address corresponding to the first port is updated to the received first target address; or, in response to the first port being disabled, the address of the first port is kept unchanged based on the first address holding signal. In response to the second port being enabled, the current address corresponding to the second port is updated to the received second target address; or, in response to the second port being disabled, the address of the second port is kept unchanged based on the second address hold signal.

12. A read / write circuit for a dual-port memory, characterized in that, include: The data analysis circuit is used to determine whether there is a conflict between the processing signals received by the first port and the second port when the first port and the second port are enabled simultaneously. An output processing circuit is configured to, in response to a conflict between the processing signals corresponding to the first port and the second port, perform an operation matching the processing signal based on the priority of the first port and the second port; The cell address determination sub-circuit is used to determine the address corresponding to the smaller bit width between the bit width of the first port and the bit width of the second port as the cell address; A reference address bit determination sub-circuit is used to determine the address corresponding to the larger bit width between the bit width of the first port and the bit width of the second port as the reference address; the reference address corresponds to multiple memory segments, and the bit width of each memory segment is the same as the memory bit width of the cell address; The data conflict determination sub-circuit is used to determine the target storage segment among the plurality of storage segments based on the reference address and the cell address; in response to the data in the target storage segment being different from the data in the cell address, it is determined that there is a conflict between the processing operations corresponding to the processing signals of the first port and the second port.

13. A stacked memory, characterized in that, include: A storage unit, the storage unit comprising the read / write circuitry of the dual-port memory as described in claim 12; The logic unit is stacked with the storage unit and is three-dimensionally heterogeneously integrated and connected.

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