Sparse cholesky decomposition hardware acceleration system and solution method thereof

Abstract

This invention discloses a hardware-accelerated system and solution method for sparse Cholesky decomposition. The system comprises an FPGA-side hardware component and a CPU-side software component. The FPGA-side hardware component includes a matrix input and basic operation module, an updated matrix generation module, and an extended summation module. The CPU-side software component includes an auxiliary matrix generation module, a parallel scheduling module, and a rollback computation module. This invention fully utilizes the pipelined characteristics of FPGAs, using FIFO channels to synchronize modules with different computation rates, thereby reducing the use of on-chip SRAM resources and lowering the overall latency of matrix decomposition computation. Furthermore, this invention, through joint CPU and FPGA solution, frees the processable matrix size from the limitations of FPGA hardware resources, improving the system's reliability in real-world scenarios.

Description

Technical Field

[0001] This invention relates to the technical field of FPGA hardware acceleration, and in particular to a sparse Cholesky decomposition hardware acceleration system and its solution method for embedded platforms. Background Technology

[0002] In recent years, the Cholesky decomposition method for sparse matrices has been widely used in embedded platforms. Sparse Cholesky decomposition is a method of decomposing a sparse symmetric positive definite matrix into the product of a sparse matrix and its transpose. Currently, methods in the field of mobile robotics, such as local path planning, real-time localization, and map building, all involve the decomposition of symmetric positive definite sparse matrices, thus creating a demand for high performance and real-time efficiency in the computation of sparse Cholesky algorithms on embedded platforms. FPGA hardware, with its pipelined and reconfigurable resources, can provide efficient computational solutions for the aforementioned sparse matrix decomposition algorithms and integrate them into the computational flow of embedded platforms, solving the performance limitations of current embedded platforms in processing decomposition operations and enabling hardware acceleration for various upper-layer applications.

[0003] Cholesky's decomposition method uses a recursive approach. For a matrix A to be decomposed, the matrix is ​​divided into blocks, resulting in the following formula:

[0004]

[0005] Among them, a 11 Let A be the element located in the 1st row and 1st column of matrix A. 21 Let A be the column vector of the elements below the diagonal of the first row of matrix A. 22 Let A be a square matrix of order n-1, and let A be the matrix formed excluding the first row and first column. For A 21 The transpose of matrix A. The result of Cholesky decomposition of matrix A can also be represented in the following block form:

[0006]

[0007] Where L is the lower triangular matrix in the decomposition result of matrix A, L T For the transpose of L, l 11 Let L be the element in the first row and first column of matrix L. 21 Let L be the column vector of the elements below the diagonal of the first row of matrix L. 22 Let L be a square matrix of order n-1, and let L be the matrix formed excluding the first row and first column. For L 21 transpose, For L 22 The transpose of .

[0008] According to the matrix factorization formula A = LL T We can obtain the following formula:

[0009]

[0010] From this, we can calculate A. 22 and L 21 Similarly, for L 22 The solution can also be achieved using the Cholesky method. Therefore, by recursively performing the above calculation process, the decomposition of A can be completed.

[0011] The decomposition method described above starts from the first column of the matrix A to be decomposed and proceeds sequentially through each column. The decomposition of each column depends on the modifications made to the matrix by the decomposition of the previous column. For sparse matrices, since most positions in the matrix are filled with zero elements, the decomposition of one column may not affect subsequent columns. Therefore, in the sparse Cholesky decomposition process, there are generally no strict data dependencies between columns, which provides a good opportunity for parallel decomposition of different columns. To achieve parallel decomposition of sparse matrices, current hardware and software acceleration systems for the sparse Cholesky decomposition method typically utilize the Multifrontal method to handle the data dependencies between columns during decomposition calculations. This method passes intermediate values ​​between nodes in the dependency graph to eliminate competition for reading and writing access to the original matrix, thereby achieving parallelization of the decomposition on various computing platforms and improving the throughput of the algorithm and the utilization of hardware resources.

[0012] The Multifrontal method uses a elimination tree to manage the dependencies between nodes during the decomposition process. If each column is considered a node in a graph, a dependency graph called the elimination tree can be formed. In this elimination tree, the column corresponding to a parent node depends on the modifications made to the original matrix by its child nodes during decomposition. For a given state in the decomposition process, if the nodes with an in-degree of 0 in the elimination tree are represented as a set, then all nodes in this set can be decomposed in parallel. In the matrix A′ to be decomposed after symbolic decomposition, if the set R is represented by the row indices of the diagonal and sub-diagonal elements of the current decomposition column, then the column corresponding to the child node of that column in the elimination tree can only depend on the set E = {a′}. ij The elements in set R are modified, where i and j represent elements in set R, and a′ are modified. ijThis represents the element located in the i-th row and j-th column of the matrix A′ to be decomposed. The Multifrontal method uses the Frontal matrix to eliminate the race condition when updating the original matrix during the computation of child nodes. The Frontal matrix stores the latest values ​​of the matrix elements involved in the node decomposition operation, and it corresponds one-to-one with the element positions in the aforementioned set E. When the decomposition operation of a node begins, it obtains the latest values ​​of the elements from its own Frontal matrix. When it is necessary to modify the matrix elements of subsequent columns, it temporarily stores the updated values ​​in the update matrix, waiting to update the Frontal matrix of the parent node of the tree, thereby avoiding the race problem caused by other nodes modifying the same elements of the original matrix.

[0013] FPGA hardware platforms can enhance the performance of sparse Cholesky decomposition. Utilizing the dataflow model of an FPGA hardware platform, parallel computation can be achieved between modules. Specifically, modules in the FPGA hardware use FIFO channels to pass intermediate computational values. Modules downstream of the channel synchronize based on the FIFO channel, receiving output values ​​from upstream modules in real time and performing parallel computations. This model is called the dataflow model. Currently, existing sparse Cholesky decomposition acceleration schemes based on FPGA hardware platforms are typically designed for large-scale scientific computing problems and server platforms. These schemes leverage the ample resources of the platform, storing some intermediate results in on-chip SRAM and performing operations on multiple elements within a single clock cycle to maximize throughput. However, embedded FPGA acceleration platforms generally have limited hardware resources, making it difficult to fully store intermediate results in on-chip SRAM. Furthermore, the kernel of an embedded FPGA acceleration platform directly accesses host memory via the AXI bus, eliminating the need for PCIe bus and controller data exchange. Therefore, the memory access and communication models of FPGA hardware acceleration systems deployed on embedded and server platforms differ significantly, making traditional hardware and software designs for server platforms difficult to port easily. In addition, computing applications running on embedded platforms typically handle smaller-scale inputs and are more sensitive to latency, making throughput-centric design approach unsuitable. Therefore, it is necessary to implement specialized sparse matrix Cholesky decomposition hardware and software designs for embedded FPGA acceleration platforms to provide low-latency and high-efficiency acceleration solutions for embedded applications. Summary of the Invention

[0014] This invention aims to overcome the shortcomings of existing sparse Cholesky decomposition acceleration hardware designs for deployment on embedded small-scale FPGA devices. It proposes a sparse Cholesky decomposition hardware acceleration system and its solution method for embedded platforms. This system employs a heterogeneous computing approach combining FPGA and CPU, and the provided technical solution includes FPGA-side hardware and CPU-side software. The system implements the pipelined computational parts of sparse Cholesky decomposition in the FPGA-side hardware and the scheduling management and auxiliary data generation tasks in the CPU-side software, fully leveraging the advantages of FPGA parallel computing and CPU random read / write efficiency. The proposed system reduces hardware complexity, considers the resource constraints of embedded FPGA devices, and uses FIFO channels to achieve data transfer between various sub-modules of the FPGA-side hardware, reducing the use of on-chip BRAM resources, lowering processing latency for small-scale problems, and improving the performance of the sparse Cholesky decomposition algorithm.

[0015] To achieve the above objectives, the technical solution provided by this invention is: a hardware acceleration system for sparse Cholesky decomposition on embedded platforms, comprising:

[0016] The FPGA-side hardware is used to implement the decomposition of a single column of a matrix in the sparse Cholesky decomposition algorithm, generating the decomposition result of the single column and updating the matrix. This FPGA-side hardware uses a data flow model to synchronize internal modules at different rates, and realizes data transfer between modules through a FIFO channel. The intermediate results of the calculation are pushed to the channel element by element, thereby realizing the parallelization of calculation between modules.

[0017] The CPU-side software receives the input matrix information to be decomposed, outputs a task scheduling sequence, allocates memory regions for the FPGA-side hardware in each round of computation, generates auxiliary data, and performs on-demand CPU rollback calculations. This CPU-side software manages memory and generates auxiliary data at the start of each column decomposition. When the column to be decomposed meets the calculation conditions of the FPGA-side hardware, it uses the AXI bus to transfer the address of the aforementioned memory region and auxiliary data to the FPGA-side hardware, initiating the FPGA-side hardware to complete the single-column decomposition. Conversely, if the column does not meet the conditions, the CPU-side software employs a CPU rollback calculation strategy, implementing the single-column decomposition calculation on the CPU.

[0018] Preferably, the FPGA-side hardware includes a matrix input and basic operation module, an updated matrix generation module, and an extended summation module, wherein:

[0019] The matrix input and basic operation module is used to read a column of the matrix to be decomposed from the host DDR memory, and then perform floating-point square root and division operations on each element on the diagonal and below of the column to generate the decomposition result. Finally, the result is written back to the DDR memory and pushed to the FIFO channel.

[0020] The update matrix generation module is used to receive processing results from the matrix input and basic operation module, calculate the Cartesian product of the result set to generate a set of element pairs, and then calculate the product of each element with respect to its two quantities; the above product is subtracted from the corresponding element of the frontal matrix of the parent node of the elimination tree to generate an update matrix and push it to the FIFO channel connected to the downstream module.

[0021] The extended summation module receives the updated matrix from the updated matrix generation module, completes the sparse matrix extended summation operation with the help of auxiliary data input from the CPU-side software and the current frontal matrix data of the eliminated tree parent node in memory, generates a new frontal matrix of the eliminated tree parent node, and then writes the result back to DDR memory through the AXI bus.

[0022] Preferably, the matrix input and basic operation module includes a matrix input submodule, a basic operation submodule, and a result write-back submodule, wherein:

[0023] The matrix input submodule reads a specified length of data from the host DDR memory via the AXI bus, processes the data, and pushes it into the FIFO channel within the module. Upon startup, the matrix input submodule uses task control bits transmitted from the CPU-side software to determine if the current node is a leaf node in the elimination tree. If it is a leaf node, the matrix input submodule outputs all non-zero elements of the column to be decomposed to the FIFO channel Q. FF If it is not a leaf node, the matrix input submodule will sum the first column of the current node's Frontal matrix with all non-zero elements of the column to be decomposed, and then output the sum to the FIFO channel Q. FF It also outputs the subsequent columns of the current node's Frontal matrix to the FIFO channel Q. FA Since the frontal matrix is ​​a symmetric matrix, the number of elements in the first column to be output is the order Fn of the matrix, and the number of elements in subsequent columns is Fn×(Fn-1)÷2. Simultaneously, this matrix input submodule will output the frontal matrix, excluding the parent node of the current node in the tree, to the FIFO channel Q. PF ;

[0024] The basic operation submodule and the matrix input submodule are connected via a FIFO channel Q. FF Connected; the basic operation submodule from Q FFThe first column of the current node's Frontal matrix is ​​read in, and the first element read is the diagonal element (trig) of that column. This basic operation submodule uses a square root logic circuit to calculate the square root of the diagonal element. Push it to two FIFO channels Q L Q FFD Both of the above FIFO channels are used to store the decomposition results of the current column, where channel Q... L Connected to the result write-back submodule, channel Q FFD Connected to the update matrix generation module; then, the basic operations submodule processes all elements t below the first diagonal of the Frontal matrix. i Calculate floating-point division t i ÷trig, and similarly push the calculation results to the two FIFO channels Q mentioned above. L Q FFD middle;

[0025] The result write-back submodule and the matrix input submodule communicate via FIFO channel Q. L The CPU-side software sends the base address of the memory containing the calculation results and the offset of the current decomposition column to the FPGA-side hardware during startup. The result write-back submodule calculates the actual memory address where the calculation results for the current decomposition column are stored using the offset. The actual memory address is the base address plus the offset. Then, the result write-back submodule sequentially writes Q values ​​to this actual memory address via the AXI bus. L Element.

[0026] Preferably, the update matrix generation module includes a submodule for sending elements to be processed and a submodule for calculating elements, wherein:

[0027] The element-to-be-processed sending submodule internally uses BRAM to temporarily store the first column element of the node's frontal matrix; upon startup, the element-to-be-processed sending submodule uses a loop with a length equal to the order of the node's frontal matrix to send elements from the FIFO channel Q. FFD Read the first column of elements and store them sequentially into the BRAM; after storing the first column of elements, the element sending submodule uses a double-nested loop to send the elements to Q. D Push element pairs, where Q D This represents a FIFO channel storing the Cartesian product of the first column of elements; from the FIFO channel Q... FFD The element received in is F first ={f1,f2,...,f n}, where f n This represents the nth element received, that is, the nth element in the first column of the lower triangular frontal matrix, F. firstLet F represent the set of elements in the first column of the lower triangular frontal matrix; after removing the diagonal elements, we obtain the set F. f ′ irst =F first f1 = {f2, f3, ..., f n Nested loops are used to push collections. The element pairs in the matrix, where x and y are the indices of the first column elements of the Frontal matrix, obtained in the range [2, n], and used for the outer and inner loops respectively; This indicates that the values ​​of x and y are both positive integers;

[0028] The element calculation submodule and the element to be processed sending submodule communicate via FIFO channel Q. D Connected; the element calculation submodule from Q D Read in the pair of elements to be calculated (f) x ,f y ), calculate the result of element-wise floating-point multiplication m = f x ×f y Then, the element calculation submodule uses a loop of length equal to the number of elements in the update matrix from the FIFO channel Q. FA The following steps read the values ​​q from the subsequent columns of the Frontal matrix, calculate the value of qm, and push it into the FIFO channel Q. U , where Q U This represents the FIFO channel for storing the update matrix.

[0029] Preferably, the extended summation module includes an auxiliary matrix extension submodule and a summation operation submodule, wherein:

[0030] The auxiliary matrix expansion submodule reads the first column of the auxiliary matrix input from the CPU-side software via the AXI bus and expands it to obtain the complete auxiliary matrix. Upon startup, the submodule stores the read first column element into BRAM. Subsequently, it calculates subsequent columns of the auxiliary matrix using the first column element. Elements in the auxiliary matrix P take values ​​of 0 or 1, and the element p with row and column indices (r, c) in P... r,c Starting from the first element p r,1 and p c,1 The auxiliary matrix is ​​obtained through a logical AND operation; the subsequent columns of the calculated auxiliary matrix are then pushed sequentially to the FIFO channel Q. P In, among which, Q P This represents a FIFO channel that stores the complete auxiliary matrix;

[0031] The summation submodule, auxiliary matrix expansion submodule, matrix input and basic operation module, and update matrix generation module are connected via three FIFO channels Q. P QPF Q U Connected, specifically performing the following operations: The summation submodule uses a loop of length equal to the number of elements in the parent node's Frontal matrix, starting from Q each time. P Read an element p from the auxiliary matrix. If the element is 1, it means that the corresponding position in the result matrix is ​​obtained by summing the elements of the parent node's Frontal matrix and the updated matrix. In this case, the summation operation submodule reads from Q. PF and Q U Elements pf and u are read from the matrix, pf + u is calculated, and the result is written to DDR memory via the AXI bus. If the element is 0, it means that the corresponding position in the update matrix is ​​a zero element. In this case, the summation submodule reads from Q... PF The element pf is read into the memory and written to DDR memory via the AXI bus; the above operations realize the sparse matrix addition operation.

[0032] Preferably, the CPU-side software includes an auxiliary matrix generation module, a parallel scheduling module, and a fallback calculation module, wherein:

[0033] The auxiliary matrix generation module is used to find the same row element in the child node that corresponds to the current processing row of the parent node, thereby generating the first column of the auxiliary matrix for use by the extended summation module of the FPGA side hardware.

[0034] The parallel scheduling module is used to provide task scheduling schemes and memory resource management schemes for cases where the FPGA-side hardware has an arbitrary number of computing units. It takes the elimination tree structure of the problem to be solved and the number of computing units deployed in the FPGA-side hardware as input, returns the set of node tasks that can be processed in parallel at the current moment, and manages the ownership of fixed-size memory regions within the system during the solution process, and maintains the consistency mark of the memory regions.

[0035] The rollback calculation module is used to receive calculation tasks from the parallel scheduling module, calculate the column to be decomposed with high non-zero element density in the CPU-side software part, and write the single column decomposition results and the update of the parent node of the eliminated tree directly back to DDR memory.

[0036] Preferably, the auxiliary matrix generation module uses the current decomposition column w. i The column w corresponding to the parent node in the tree to be eliminated j The element data is taken as input, and the first column of the auxiliary matrix P used for the Extend-Add operation is output; when the auxiliary matrix generation module starts, it iterates through column w. j All rows, in column w i Searching for and listing w jElements in the same row; if an element that meets the condition is found, set the element in the corresponding row of the first column of the output auxiliary matrix P to 1, otherwise set the above element to 0.

[0037] Preferably, the parallel scheduling module includes a processing unit scheduling submodule and a memory scheduling submodule, wherein:

[0038] The processing unit scheduling submodule provides efficient task scheduling to maximize parallelism in the problem-solving process. It takes the elimination tree structure of the problem to be solved and the number of computing units deployed on the FPGA side as input, and returns a set of node tasks that can be processed in parallel at the current moment. Each time a task is returned, the submodule maintains scheduling-related data structures to quickly obtain new nodes that can be processed in parallel in the updated elimination tree structure. These scheduling-related data structures include a task stack and the equality of each node. Waiting queue; when a node is removed from the task stack, the scheduling submodule of this processing unit will check the parent node of the node in the elimination tree; if the out-degree of the parent node after the update is 0, then the following judgment is performed: if the parent node has no other child nodes in the task stack, then the parent node is pushed onto the task stack, otherwise the parent node is placed into the waiting queue of the next higher level node in its elimination tree; if the out-degree of the parent node after the update is not 0, then the following judgment is performed: if the waiting queue of the parent node is not empty, then a node is taken out from the queue and put into the task stack; in order to complete in O(1) time complexity Based on the above judgments, the processing unit scheduling submodule maintains a flag for each node to indicate whether the current node has child nodes in the task stack. Each time a node is removed from the task stack, the above flag of the parent node is updated according to the judgment result of whether the parent node's waiting queue is empty. After completing the scheduling and maintenance work, the processing unit scheduling submodule outputs a set of node tasks that can be processed in parallel, calls the memory scheduling submodule to allocate frontal matrix memory space for each task, generates auxiliary matrices, and judges whether it meets the requirements of the FPGA side hardware by comparing the number of non-zero elements in the corresponding column of the node in the task with the scale of BRAM deployed in the FPGA side hardware. If the requirements are met, the processing unit scheduling submodule inputs the memory address data of the node frontal matrix, the parent node frontal matrix, and the auxiliary matrix to the FPGA side hardware, as well as the task control bit information indicating whether the node is a leaf node in the elimination tree, and starts the kernel to run. If the requirements are not met, the processing unit scheduling submodule calls the rollback calculation module to use the CPU to complete the single column decomposition calculation.

[0039] The memory scheduling submodule includes a memory allocator and a memory pool scheduler. The memory allocator calls the system library to complete the initial memory region allocation, while the memory pool scheduler receives requests from the processing unit scheduling submodule and handles internal memory allocation and release. To maximize the reuse of node memory space while controlling the overall system memory usage, the memory scheduling submodule first sorts the nodes according to the number of non-zero elements in their corresponding columns and divides them into two categories based on the quantity. Nodes in the same category share a memory region in a memory pool. All memory elements in the memory pool managed by this memory scheduling submodule are of the same size, and the size of all memory elements is determined by the column with the largest number of non-zero elements in its corresponding category. Therefore, a memory element can be reused by multiple tasks at different times during the solution process. When a node completes its decomposition work, it releases its memory space, which is then placed into its corresponding memory pool by the memory scheduling submodule. Each memory pool in this memory scheduling submodule is managed through a stack structure. When a memory pool is not empty, the memory region allocated by the memory scheduling submodule to the requester upon receiving a memory allocation request is the most recently returned memory space.

[0040] Preferably, the rollback calculation module includes a cache consistency management submodule and a CPU rollback algorithm submodule, wherein:

[0041] The cache consistency management submodule is used to avoid potential inconsistencies caused by the CPU cache when the FPGA-side hardware and CPU-side software jointly read and write to the same memory region. The management framework listens to the read and write status of the two in different memory regions. When one side reads a memory region updated by the other side, the cache consistency management submodule intervenes and performs a cache refresh operation to eliminate the consistency problem. The cache consistency management submodule maintains a consistency flag for each memory region allocated by the parallel scheduling module. When the CPU-side software requests a memory region from the operating system, the memory region is first initialized to a consistent state. When the FPGA-side hardware or CPU-side software performs a write operation on the memory region, the above flag will be updated to the inconsistent state of the corresponding side. In actual calculation, when reading a memory region, if the flag of the region has been updated to an inconsistent state due to a previous write operation on the other side, the CPU cache needs to be flushed to obtain the latest data. The cache flush operation can ensure that all write operations of the CPU cache are executed correctly, while new read operations will request data again from DDR memory.

[0042] The CPU rollback algorithm submodule implements the sparse Cholesky decomposition algorithm in the CPU-side software. Its algorithm flow is identical to that of the FPGA-side hardware implementation. Leveraging the CPU's high efficiency in random access and memory writing, the algorithm directly performs calculations within the existing memory region, without introducing additional memory space for single-column decomposition calculations. This CPU rollback algorithm submodule receives computation tasks from the parallel scheduling module in the CPU-side software and completes single-column decomposition calculations according to the processes described in the matrix input and basic operation module, the update matrix generation module, and the extended summation module. Unlike the module deployed in the FPGA-side hardware, the CPU rollback algorithm submodule eliminates the need for indirect data reading from DDR memory, directly performing random access and updates to memory. When performing read / write operations on a memory region, the CPU rollback algorithm submodule calls the cache consistency management submodule to ensure that the operated data does not produce consistency issues. After completing the calculation, the CPU rollback algorithm submodule writes the results to the corresponding columns of the matrix storing the calculation results, as well as the Frontal matrix with the parent nodes of the tree removed.

[0043] This invention also provides a solution method for the above-mentioned hardware-accelerated sparse Cholesky decomposition system for embedded platforms, comprising the following steps:

[0044] 1) The CPU-side software reads the matrix to be decomposed, the matrix symbolic decomposition result, and the matrix elimination tree structure from the user terminal;

[0045] 2) The parallel scheduling module of the CPU-side software obtains all columns that can be computed in parallel and allocates computing tasks; the auxiliary matrix generation module generates the first column of the auxiliary matrix used to extend the summation operation and stores it in memory; the parallel scheduling module then transmits task data and starts the kernel to execute.

[0046] 3) The FPGA-side hardware uses the designed data flow model to read the corresponding data from the DDR memory from the AXI bus according to the given address offset; each module of the FPGA-side hardware executes the calculation task and writes the calculation results back to the DDR memory through the AXI bus.

[0047] 4) If the parallel scheduling module detects a task that does not meet the operating requirements of the FPGA-side hardware, the rollback calculation module completes the single-column decomposition calculation in the CPU-side software and writes the calculation result to DDR memory.

[0048] 5) The memory space occupied by the Frontal matrix after the columns have been decomposed is returned to the memory pool through the memory scheduling submodule, thus completing the decomposition of one column; if there are still columns to be decomposed, the decomposition process is repeated from step 2) until all columns of the matrix have been decomposed.

[0049] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0050] 1. This invention implements a data flow model through inter-module FIFO channels, which reduces the demand for FPGA-side memory resources, lowers the complexity of hardware design, and enables the design proposed in this invention to be deployed on embedded FPGA development boards of different specifications.

[0051] 2. This invention achieves parallel computing among modules by synchronizing modules with different data processing rates through an inter-module FIFO channel. Elements processed by the upstream module flow to the downstream module along the FIFO channel. Most modules do not need to wait for the upstream module to output complete calculation results before starting the calculation work, thus reducing the overall processing latency of small-scale data.

[0052] 3. This invention uses a combination of FPGA-side hardware and CPU-side software to achieve sparse Cholesky decomposition. The core computations that are more pipelined and parallelizable are deployed on the FPGA-side hardware, while the scheduling and memory management that have high requirements for random read and write performance are deployed on the CPU-side software, making full use of the processing capabilities of each part of the heterogeneous platform.

[0053] 4. This invention designs a backoff calculation module, which, together with the parallel scheduling module, eliminates the limitation of the FPGA platform's resource scale on the solvable problems. It can handle problems that cannot be solved by the FPGA hardware part in the CPU side software part, and provide reliable solution results for inputs with different characteristics in practical applications.

[0054] 5. This invention implements an efficient task scheduling algorithm. With the help of the design of task stack and waiting queues for each node, the single-node scheduling operation can achieve a time complexity of O(1), which reduces the pressure on the computing resources of the CPU software and improves the overall performance of the sparse Cholesky decomposition hardware acceleration system. Attached Figure Description

[0055] Figure 1 This is an architecture diagram of the system of the present invention.

[0056] Figure 2 This is an FPGA hardware design diagram.

[0057] Figure 3 To update the structure diagram of the matrix generation module.

[0058] Figure 4 This is a structural diagram of the addition operation submodule. Detailed Implementation

[0059] The present invention will be further described below with reference to specific embodiments.

[0060] like Figure 1 As shown, this embodiment discloses a hardware acceleration system for sparse Cholesky decomposition on an embedded platform, comprising an FPGA-side hardware component and a CPU-side software component, wherein:

[0061] The FPGA-side hardware is used to implement the decomposition of a single column of a matrix in the sparse Cholesky decomposition algorithm, generating the decomposition result of the single column and updating the matrix. The FPGA-side hardware uses a data flow model to synchronize internal modules at different rates, and realizes data transfer between modules through a FIFO channel. The intermediate results of the calculation are pushed to the channel element by element, thereby realizing the parallelization of calculation between modules. Figure 2 The connection relationships between the various sub-modules of the FPGA-side hardware are shown.

[0062] The CPU-side software receives the input matrix information to be decomposed, outputs a task scheduling sequence, allocates memory regions for the FPGA-side hardware in each round of computation, generates auxiliary data, and performs on-demand CPU rollback calculations. This CPU-side software manages memory and generates auxiliary data at the start of each column decomposition. When the column to be decomposed meets the calculation conditions of the FPGA-side hardware, it uses the AXI bus to transfer the address of the aforementioned memory region and auxiliary data to the FPGA-side hardware, initiating the FPGA-side hardware to complete the single-column decomposition. Conversely, if the column does not meet the conditions, the CPU-side software employs a CPU rollback calculation strategy, implementing the single-column decomposition calculation on the CPU.

[0063] Specifically, the FPGA-side hardware includes a matrix input and basic operation module, an updated matrix generation module, and an extended summation module, among which:

[0064] The matrix input and basic operation module is used to read a column of the matrix to be decomposed from the host DDR memory, and then perform floating-point square root and division operations on each element on the diagonal and below of the column to generate the decomposition result. Finally, the result is written back to the DDR memory and pushed to the FIFO channel.

[0065] The update matrix generation module is used to receive processing results from the matrix input and basic operation module, calculate the Cartesian product of the result set to generate a set of element pairs, and then calculate the product of each element with respect to its two quantities; the above product is subtracted from the corresponding element of the frontal matrix of the parent node of the elimination tree to generate an update matrix and push it to the FIFO channel connected to the downstream module.

[0066] The extended summation module receives the updated matrix from the updated matrix generation module, completes the sparse matrix extended summation operation with the help of auxiliary data input from the CPU-side software and the current frontal matrix data of the eliminated tree parent node in memory, generates a new frontal matrix of the eliminated tree parent node, and then writes the result back to DDR memory through the AXI bus.

[0067] Specifically, the matrix input and basic operation module includes a matrix input submodule, a basic operation submodule, and a result write-back submodule, wherein:

[0068] The matrix input submodule reads a specified length of data from the host DDR memory via the AXI bus, processes the data, and pushes it into the FIFO channel within the module. Upon startup, the matrix input submodule uses task control bits transmitted from the CPU-side software to determine if the current node is a leaf node in the elimination tree. If it is a leaf node, the matrix input submodule outputs all non-zero elements of the column to be decomposed to the FIFO channel Q. FF If it is not a leaf node, the matrix input submodule will sum the first column of the current node's Frontal matrix with all non-zero elements of the column to be decomposed, and then output the sum to the FIFO channel Q. FF It also outputs the subsequent columns of the current node's Frontal matrix to the FIFO channel Q. FA Since the frontal matrix is ​​a symmetric matrix, the number of elements in the first column to be output is the order Fn of the matrix, and the number of elements in subsequent columns is Fn×(Fn-1)÷2. Simultaneously, this matrix input submodule will output the frontal matrix, excluding the parent node of the current node in the tree, to the FIFO channel Q. PF ;

[0069] The basic operation submodule and the matrix input submodule are connected via a FIFO channel Q. FF Connected; the basic operation submodule from Q FF The first column of the current node's Frontal matrix is ​​read in, and the first element read is the diagonal element (trig) of that column. This basic operation submodule uses a square root logic circuit to calculate the square root of the diagonal element. Push it to two FIFO channels Q L Q FFD Both of the above FIFO channels are used to store the decomposition results of the current column, where channel Q... L Connected to the result write-back submodule, channel Q FFD Connected to the update matrix generation module; then, the basic operations submodule processes all elements t below the first diagonal of the Frontal matrix. i Calculate floating-point division t i ÷trig, and similarly push the calculation results to the two FIFO channels Q mentioned above.L Q FFD middle;

[0070] The result write-back submodule and the matrix input submodule communicate via FIFO channel Q. L The CPU-side software sends the base address of the memory containing the calculation results and the offset of the current decomposition column to the FPGA-side hardware during startup. The result write-back submodule calculates the actual memory address where the calculation results of the current decomposition column are stored using the offset, where the actual memory address is the base address plus the offset. Then, the result write-back submodule sequentially writes Q values ​​to this actual memory address via the AXI bus. L Element.

[0071] Specifically, the update matrix generation module includes a submodule for sending elements to be processed and a submodule for calculating elements, wherein:

[0072] The element-to-be-processed sending submodule internally uses BRAM to temporarily store the first column element of the node's frontal matrix; upon startup, the element-to-be-processed sending submodule uses a loop with a length equal to the order of the node's frontal matrix to send elements from the FIFO channel Q. FFD Read the first column of elements and store them sequentially into the BRAM; after storing the first column of elements, the element sending submodule uses a double-nested loop to send the elements to Q. D Push element pairs, where Q D This represents a FIFO channel storing the Cartesian product of the first column of elements; from the FIFO channel Q... FFD The element received in is F first ={f1,f2,...,f n}, where f n This represents the nth element received, that is, the nth element in the first column of the lower triangular frontal matrix, F. first Let F' represent the set of elements in the first column of the lower triangular frontal matrix; after removing the diagonal elements, we obtain the set F'. first =F first f1 = {f2, f3, ..., f n Nested loops are used to push collections. The element pairs in the matrix, where x and y are the indices of the first column elements of the Frontal matrix, obtained in the range [2, n], and used for the outer and inner loops respectively; This indicates that the values ​​of x and y are both positive integers; Figure 3 The upper part shows the internal structure of the element sending submodule;

[0073] The element calculation submodule and the element to be processed sending submodule communicate via FIFO channel Q. DConnected; the element calculation submodule from Q D Read in the pair of elements to be calculated (f) x ,f y ), calculate the result of element-wise floating-point multiplication m = f x ×f y Then, the element calculation submodule uses a loop of length equal to the number of elements in the update matrix from the FIFO channel Q. FA The following steps read the values ​​q from the subsequent columns of the Frontal matrix, calculate the value of qm, and push it into the FIFO channel Q. U ; where Q U This represents the FIFO channel for storing the update matrix; Figure 3 The lower half shows the internal structure of the element calculation submodule.

[0074] Specifically, the extended summation module includes an auxiliary matrix extension submodule and a summation operation submodule, wherein:

[0075] The auxiliary matrix expansion submodule reads the first column of the auxiliary matrix input from the CPU-side software via the AXI bus and expands it to obtain the complete auxiliary matrix. Upon startup, this submodule stores the read first column element into BRAM. Subsequently, it calculates subsequent columns of the auxiliary matrix using the first column element. Elements in the auxiliary matrix P take values ​​of 0 or 1, and the element p with row and column indices (r, c) in P... r,c Starting from the first element p r,1 and p c,1 The auxiliary matrix is ​​obtained through a logical AND operation; the subsequent columns of the calculated auxiliary matrix are then pushed sequentially to the FIFO channel Q. P In, among which, Q P This represents a FIFO channel that stores the complete auxiliary matrix;

[0076] The summation submodule, auxiliary matrix expansion submodule, matrix input and basic operation module, and update matrix generation module are connected via three FIFO channels Q. P Q PF Q U Connected, specifically performing the following operations: The summation submodule uses a loop of length equal to the number of elements in the parent node's Frontal matrix, starting from Q each time. P Read an element p from the auxiliary matrix. If the element is 1, it means that the corresponding position in the result matrix is ​​obtained by summing the elements of the parent node's Frontal matrix and the updated matrix. In this case, the summation operation submodule reads from Q. PF and Q UElements pf and u are read from the matrix, pf + u is calculated, and the result is written to DDR memory via the AXI bus. If the element is 0, it means that the corresponding position in the update matrix is ​​a zero element. In this case, the summation submodule reads from Q... PF The element pf is read into the memory and written to DDR memory via the AXI bus; the above operations realize the sparse matrix addition operation. Figure 4 The internal structure of the addition operation submodule is shown.

[0077] Specifically, the CPU-side software includes an auxiliary matrix generation module, a parallel scheduling module, and a fallback computation module, among which:

[0078] The auxiliary matrix generation module is used to find the same row element in the child node that corresponds to the current processing row of the parent node, thereby generating the first column of the auxiliary matrix for use by the extended summation module of the FPGA side hardware.

[0079] The parallel scheduling module is used to provide task scheduling schemes and memory resource management schemes for cases where the FPGA-side hardware has an arbitrary number of computing units. It takes the elimination tree structure of the problem to be solved and the number of computing units deployed in the FPGA-side hardware as input, returns the set of node tasks that can be processed in parallel at the current moment, and manages the ownership of fixed-size memory regions within the system during the solution process, and maintains the consistency mark of the memory regions.

[0080] The rollback calculation module is used to receive calculation tasks from the parallel scheduling module, calculate the column to be decomposed with a high density of non-zero elements in the CPU-side software part, and write the single column decomposition results and the update of the parent node of the eliminated tree directly back to DDR memory.

[0081] Specifically, the auxiliary matrix generation module uses the current decomposition column w i The column w corresponding to the parent node in the tree to be eliminated j The element data is taken as input, and the first column of the auxiliary matrix P used for the Extend-Add operation is output; when the auxiliary matrix generation module starts, it iterates through column w. j All rows, in column w i Searching for and listing w j Elements in the same row; if an element that meets the condition is found, set the element in the corresponding row of the first column of the output auxiliary matrix P to 1, otherwise set the above element to 0.

[0082] Specifically, the parallel scheduling module includes a processing unit scheduling submodule and a memory scheduling submodule, wherein:

[0083] The processing unit scheduling submodule provides efficient task scheduling to maximize parallelism in the problem-solving process. It takes the elimination tree structure of the problem to be solved and the number of computing units deployed on the FPGA side as input, and returns a set of node tasks that can be processed in parallel at the current moment. Each time a task is returned, the submodule maintains scheduling-related data structures to quickly obtain new nodes that can be processed in parallel in the updated elimination tree structure. These scheduling-related data structures include a task stack and the equality of each node. Waiting queue; when a node is removed from the task stack, the scheduling submodule of this processing unit will check the parent node of the node in the elimination tree; if the out-degree of the parent node after the update is 0, then the following judgment is performed: if the parent node has no other child nodes in the task stack, then the parent node is pushed onto the task stack, otherwise the parent node is placed into the waiting queue of the next higher level node in its elimination tree; if the out-degree of the parent node after the update is not 0, then the following judgment is performed: if the waiting queue of the parent node is not empty, then a node is taken out from the queue and put into the task stack; in order to complete in O(1) time complexity Based on the above judgments, the processing unit scheduling submodule maintains a flag for each node to indicate whether the current node has child nodes in the task stack. Each time a node is removed from the task stack, the above flag of the parent node is updated according to the judgment result of whether the parent node's waiting queue is empty. After completing the scheduling and maintenance work, the processing unit scheduling submodule outputs a set of node tasks that can be processed in parallel, calls the memory scheduling submodule to allocate frontal matrix memory space for each task, generates auxiliary matrices, and judges whether it meets the requirements of the FPGA side hardware by comparing the number of non-zero elements in the corresponding column of the node in the task with the scale of BRAM deployed in the FPGA side hardware. If the requirements are met, the processing unit scheduling submodule inputs the memory address data of the node frontal matrix, the parent node frontal matrix, and the auxiliary matrix to the FPGA side hardware, as well as the task control bit information indicating whether the node is a leaf node in the elimination tree, and starts the kernel to run. If the requirements are not met, the processing unit scheduling submodule calls the rollback calculation module to use the CPU to complete the single column decomposition calculation.

[0084] The memory scheduling submodule includes a memory allocator and a memory pool scheduler. The memory allocator calls the system library to complete the initial memory region allocation, while the memory pool scheduler receives requests from the processing unit scheduling submodule and handles internal memory allocation and release. To maximize the reuse of node memory space while controlling the overall system memory usage, the memory scheduling submodule first sorts the nodes according to the number of non-zero elements in their corresponding columns and divides them into two categories based on the quantity. Nodes in the same category share a memory region in a memory pool. All memory elements in the memory pool managed by this memory scheduling submodule are of the same size, and the size of all memory elements is determined by the column with the largest number of non-zero elements in its corresponding category. Therefore, a memory element can be reused by multiple tasks at different times during the solution process. When a node completes its decomposition work, it releases its memory space, which is then placed into its corresponding memory pool by the memory scheduling submodule. Each memory pool in this memory scheduling submodule is managed through a stack structure. When a memory pool is not empty, the memory region allocated by the memory scheduling submodule to the requester upon receiving a memory allocation request is the most recently returned memory space.

[0085] Specifically, the rollback calculation module includes a cache consistency management submodule and a CPU rollback algorithm submodule, wherein:

[0086] The cache consistency management submodule is used to avoid potential inconsistencies caused by the CPU cache when the FPGA-side hardware and CPU-side software jointly read and write to the same memory region. The management framework listens to the read and write status of the two in different memory regions. When one side reads a memory region updated by the other side, the cache consistency management submodule intervenes and performs a cache refresh operation to eliminate the consistency problem. The cache consistency management submodule maintains a consistency flag for each memory region allocated by the parallel scheduling module. When the CPU-side software requests a memory region from the operating system, the memory region is first initialized to a consistent state. When the FPGA-side hardware or CPU-side software performs a write operation on the memory region, the above flag will be updated to the inconsistent state of the corresponding side. In actual calculation, when reading a memory region, if the flag of the region has been updated to an inconsistent state due to a previous write operation on the other side, the CPU cache needs to be flushed to obtain the latest data. The cache flush operation can ensure that all write operations of the CPU cache are executed correctly, while new read operations will request data again from DDR memory.

[0087] The CPU rollback algorithm submodule implements the sparse Cholesky decomposition algorithm in the CPU-side software. Its algorithm flow is identical to that of the FPGA-side hardware implementation. Leveraging the CPU's high efficiency in random accessing and writing memory without requiring additional data transfer, the submodule performs calculations directly within the existing memory region, without introducing additional memory space for single-column decomposition calculations. This submodule receives computation tasks from the parallel scheduling module in the CPU-side software and completes single-column decomposition calculations according to the processes described in the matrix input and basic operation module, the update matrix generation module, and the extended summation module. Unlike the module deployed in the FPGA-side hardware, the CPU rollback algorithm submodule eliminates the need for indirect data reading from DDR memory, directly performing random access and updates to memory. When performing read / write operations on a memory region, the submodule calls the cache consistency management submodule to ensure that the data being operated on does not produce consistency issues. After completing the calculation, the submodule writes the results to the corresponding column of the matrix storing the calculation results, as well as the Frontal matrix with the parent nodes of the tree removed.

[0088] The following is the solution method for the sparse Cholesky decomposition hardware acceleration system for embedded platforms described in this embodiment, including the following steps:

[0089] 1) The CPU-side software reads the matrix to be decomposed, the matrix symbolic decomposition result, and the matrix elimination tree structure from the user terminal;

[0090] 2) The parallel scheduling module of the CPU-side software obtains all columns that can be computed in parallel and allocates computing tasks; the auxiliary matrix generation module generates the first column of the auxiliary matrix used to extend the summation operation and stores it in memory; the parallel scheduling module then transmits task data and starts the kernel to execute.

[0091] 3) The FPGA-side hardware uses the designed data flow model to read the corresponding data from the DDR memory from the AXI bus according to the given address offset; each module of the FPGA-side hardware executes the calculation task and writes the calculation results back to the DDR memory through the AXI bus.

[0092] 4) If the parallel scheduling module detects a task that does not meet the operating requirements of the FPGA-side hardware, the rollback calculation module completes the single-column decomposition calculation in the CPU-side software and writes the calculation result to DDR memory.

[0093] 5) The memory space occupied by the Frontal matrix after the columns have been decomposed is returned to the memory pool through the memory scheduling submodule, thus completing the decomposition of one column; if there are still columns to be decomposed, the decomposition process is repeated from step 2) until all columns of the matrix have been decomposed.

[0094] This invention was tested on the publicly available benchmark dataset SuiteSparse Matrix Collection. This dataset collects data from real-world applications such as structural computation, fluid simulation, and statistical problems, and can measure the performance of the sparse matrix factorization framework under practical loads. The proposed computational framework was verified for correctness and its performance was compared with the commonly used open-source solver library CSparse. Test results show that the proposed solution has better performance than CPU computation on embedded FPGA development boards, demonstrating a significant acceleration effect. Specific test results are shown in Table 1.

[0095] Table 1 Performance test of the proposed solution and the open-source solver library CSparse

[0096]

[0097] Table 1 shows the total time consumed by the framework under test in processing sparse matrix factorization in the test cases. Ours represents the time measured using the proposed scheme, and CSparse represents the time measured by calling the standard API of the CSparse framework. According to the data in this table, the accelerated framework proposed in this invention can achieve a performance improvement of approximately 10% to 148% compared to the A53 CPU + CSparse framework for practical matrix factorization and solution problems. However, for extremely small matrices, since communication between the CPU and FPGA accounts for most of the time, the solution efficiency on the CPU may be slightly higher than that of the framework proposed in this invention.

[0098] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A sparse Cholesky decomposition hardware acceleration system for embedded platforms, characterized in that, include: The FPGA-side hardware is used to implement the decomposition of a single column of the matrix in the sparse Cholesky decomposition algorithm, generate the decomposition result of the single column, and update the matrix. The FPGA-side hardware uses a data flow model to synchronize internal modules at different rates, and uses a FIFO channel to transfer data between modules. The intermediate results of the calculation are pushed into the channel in units of elements, thereby achieving parallelization of the calculation between modules. The CPU-side software receives the input matrix information to be decomposed, outputs a task scheduling sequence, allocates memory regions for the FPGA-side hardware in each round of computation, generates auxiliary data, and performs on-demand CPU rollback calculations. This CPU-side software manages memory and generates auxiliary data at the start of each column decomposition. When the column to be decomposed meets the calculation conditions of the FPGA-side hardware, it uses the AXI bus to transfer the address of the aforementioned memory region and auxiliary data to the FPGA-side hardware, initiating the FPGA-side hardware to complete the single-column decomposition. Conversely, if the column does not meet the conditions, the CPU-side software employs a CPU rollback calculation strategy, implementing the single-column decomposition calculation on the CPU. The FPGA-side hardware includes a matrix input and basic operation module, an updated matrix generation module, and an extended summation module, wherein: The matrix input and basic operation module is used to read a column of the matrix to be decomposed from the host DDR memory, and then perform floating-point square root and division operations on each element on the diagonal and below of the column to generate the decomposition result. Finally, the result is written back to the DDR memory and pushed to the FIFO channel. The update matrix generation module is used to receive processing results from the matrix input and basic operation module, calculate the Cartesian product of the result set to generate a set of element pairs, and then calculate the product of each element with respect to its two quantities; the above product is subtracted from the corresponding element of the frontal matrix of the parent node of the elimination tree to generate an update matrix and push it to the FIFO channel connected to the downstream module. The extended summation module is used to receive the update matrix from the update matrix generation module, and complete the sparse matrix extended summation operation with the help of auxiliary data input from the CPU-side software and the current frontal matrix data of the eliminated tree parent node in memory, to generate a new frontal matrix of the eliminated tree parent node, and then write the result back to DDR memory through the AXI bus. The CPU-side software includes an auxiliary matrix generation module, a parallel scheduling module, and a fallback calculation module, wherein: The auxiliary matrix generation module is used to find the same row element in the child node that corresponds to the current processing row of the parent node, thereby generating the first column of the auxiliary matrix for use by the extended summation module of the FPGA side hardware. The parallel scheduling module is used to provide task scheduling schemes and memory resource management schemes for cases where the FPGA-side hardware has an arbitrary number of computing units. It takes the elimination tree structure of the problem to be solved and the number of computing units deployed in the FPGA-side hardware as input, returns the set of node tasks that can be processed in parallel at the current moment, and manages the ownership of fixed-size memory regions within the system during the solution process, and maintains the consistency mark of the memory regions. The rollback calculation module is used to receive calculation tasks from the parallel scheduling module, calculate the column to be decomposed with high non-zero element density in the CPU-side software part, and write the single column decomposition results and the update of the parent node of the eliminated tree directly back to DDR memory.

2. The sparse Cholesky decomposition hardware acceleration system for embedded platforms of claim 1, wherein: The matrix input and basic operation module includes a matrix input submodule, a basic operation submodule, and a result write-back submodule, wherein: The matrix input submodule reads a specified length of data from the host DDR memory via the AXI bus, processes the data, and pushes it into the FIFO channel within the module. Upon startup, the matrix input submodule uses task control bits transmitted from the CPU-side software to determine if the current node is a leaf node in the elimination tree. If it is a leaf node, the matrix input submodule outputs all non-zero elements of the column to be decomposed to the FIFO channel. If it is not a leaf node, the matrix input submodule will sum the first column of the current node's Frontal matrix with all non-zero elements of the column to be decomposed and output the sum to the FIFO channel. It also outputs the subsequent columns of the current node's Frontal matrix to the FIFO channel. Since the frontal matrix is ​​a symmetric matrix, the number of elements in the first column to be output is equal to the order of the matrix. The number of elements in the subsequent columns is Simultaneously, this matrix input submodule outputs the Frontal matrix (which eliminates the parent node of the current node in the tree) to the FIFO channel. ; The basic operation submodule and the matrix input submodule are connected via a FIFO channel. Connected; the basic operation submodule from Read the first column of the current node's Frontal matrix. The first element read is the diagonal element of that column. This basic operation submodule uses square root logic circuitry to calculate the square root of the diagonal elements. And push it to two FIFO channels Both of the above FIFO channels are used to store the decomposition results of the current column. The channel... Connected to the result write-back submodule, channel Connected to the update matrix generation module; then, the basic operations submodule processes all elements below the first diagonal of the Frontal matrix. Calculate floating-point division The calculation results are also pushed to the two FIFO channels mentioned above. middle; The result write-back submodule and the matrix input submodule communicate via a FIFO channel. The CPU-side software sends the base address of the memory containing the calculation results and the offset of the current decomposition column to the FPGA-side hardware during startup. The result write-back submodule calculates the actual memory address where the calculation results for the current decomposition column are stored using the offset. The actual memory address is the base address plus the offset. Then, the result write-back submodule sequentially writes the results to this actual memory address via the AXI bus. Element.

3. The sparse Cholesky decomposition hardware acceleration system for embedded platforms of claim 2, wherein: The update matrix generation module includes a submodule for sending elements to be processed and a submodule for calculating elements, wherein: The element-to-be-processed sending submodule internally uses BRAM to temporarily store the first column element of the node's frontal matrix; upon startup, the element-to-be-processed sending submodule uses a cyclic FIFO channel with a length equal to the order of the node's frontal matrix. Read the first column of elements and store them sequentially into the BRAM; after storing the first column of elements, the element sending submodule uses a double-nested loop to send the elements to be processed. Push element pairs, where, This represents a FIFO channel that stores the Cartesian product of the first column of elements; from the FIFO channel... The element received in is ,in, This represents the nth element received, which is the nth element in the first column of the lower triangular frontal matrix. Let represent the set of elements in the first column of the lower triangular frontal matrix; after removing the diagonal elements, we obtain the set . Nested loops are used to push collections. The element pairs in, where, The index of the first column element of the Frontal matrix, in The values ​​are obtained within the specified range and used for the outer and inner loops respectively; express The values ​​of are all positive integers; The element calculation submodule and the element to be processed sending submodule are connected via a FIFO channel. Connected; the element calculation submodule from Read in the pairs of elements to be calculated Calculate the result of element-wise floating-point multiplication. Then, the element calculation submodule uses a loop of length equal to the number of elements in the update matrix from the FIFO channel. Read the values ​​of subsequent columns of the Frontal matrix ,calculate The value is pushed to the FIFO channel. ,in, This represents the FIFO channel for storing the update matrix.

4. The sparse Cholesky decomposition hardware acceleration system for embedded platforms according to claim 3, characterized in that: The extended summation module includes an auxiliary matrix expansion submodule and a summation operation submodule, wherein: The auxiliary matrix expansion submodule reads the first column of the auxiliary matrix input from the CPU-side software via the AXI bus and expands it to obtain the complete auxiliary matrix. Upon startup, the submodule stores the read first column elements of the auxiliary matrix into BRAM. Subsequently, it calculates the subsequent columns of the auxiliary matrix using these first column elements. The elements in the array can take the value 0 or 1. The row and column indexes are elements From the first column element and The auxiliary matrix is ​​obtained through a logical AND operation; subsequent columns of the calculated matrix are then pushed sequentially to the FIFO channel. In, among them, This represents a FIFO channel that stores the complete auxiliary matrix; The summation submodule, auxiliary matrix expansion submodule, matrix input and basic operation module, and update matrix generation module are connected through three FIFO channels. Connected, specifically performing the following operations: The summation submodule uses a loop of length equal to the number of elements in the parent node's Frontal matrix, each time starting from... Read an element from the auxiliary matrix If the element is 1, it means that the corresponding position in the result matrix is ​​obtained by summing the elements of the parent node's Frontal matrix and the updated matrix. In this case, the summation operation submodule starts from... and Read elements into the middle respectively ,calculate After determining the value, the result is written to DDR memory via the AXI bus; if the element is 0, it means the corresponding position in the update matrix is ​​a zero element. In this case, the summation submodule... Reading elements Similarly, via the AXI bus Write to DDR memory; the above operation implements sparse matrix summation.

5. The sparse Cholesky decomposition hardware acceleration system for embedded platforms according to claim 4, characterized in that: The auxiliary matrix generation module uses the current decomposition column Columns corresponding to the parent nodes in the tree to be eliminated The element data is taken as input, and the output is an auxiliary matrix used for the Extend-Add operation. The first column; when this auxiliary matrix generation module starts, it iterates through the columns. All rows in the column Searching for and listing Elements in the same row; if an element that meets the criteria is found, set the auxiliary matrix for output. The element in the first column of the corresponding row is set to 1, and the element in the next column is set to 0.

6. The sparse Cholesky decomposition hardware acceleration system for embedded platforms of claim 5, wherein: The parallel scheduling module includes a processing unit scheduling submodule and a memory scheduling submodule, wherein: The processing unit scheduling submodule provides efficient task scheduling to maximize parallelism in the problem-solving process. It takes the elimination tree structure of the problem to be solved and the number of computing units deployed on the FPGA side as input, and returns a set of node tasks that can be processed in parallel at the current moment. Each time a task is returned, the submodule maintains scheduling-related data structures to quickly obtain new nodes that can be processed in parallel in the updated elimination tree structure. These data structures include a task stack and a waiting queue for each node. When a node is removed from the task stack, the submodule checks the node's parent node in the elimination tree. If the updated out-degree of the parent node is 0, the following judgment is made: if the parent node has no other child nodes in the task stack, the parent node is pushed onto the task stack; otherwise, the parent node is placed in the waiting queue of the node at the next higher level in the elimination tree. If the updated out-degree of the parent node is not 0, the following judgment is made: if the parent node's waiting queue is not empty, a node is taken from the queue and placed into the task stack. Within a time complexity, the above judgments are completed. The scheduling submodule of this processing unit maintains a flag for each node to indicate whether the current node has child nodes in the task stack. Each time a node is removed from the task stack, the flag of the parent node is updated according to the result of judging whether the parent node's waiting queue is empty. After completing the scheduling and maintenance work, the scheduling submodule of this processing unit outputs a set of node tasks that can be processed in parallel, calls the memory scheduling submodule to allocate frontal matrix memory space for each task, generates auxiliary matrices, and judges whether it meets the requirements of the FPGA side hardware by comparing the number of non-zero elements in the corresponding column of the node in the task with the scale of BRAM deployed in the FPGA side hardware. If the requirements are met, the scheduling submodule of this processing unit inputs the memory address data of the node frontal matrix, the parent node frontal matrix, and the auxiliary matrix, as well as the task control bit information indicating whether the node is a leaf node in the elimination tree, and starts the kernel to run. If the requirements are not met, the scheduling submodule of this processing unit calls the rollback calculation module and uses the CPU to complete the single column decomposition calculation. The memory scheduling submodule includes a memory allocator and a memory pool scheduler. The memory allocator calls the system library to complete the initial memory region allocation, while the memory pool scheduler receives requests from the processing unit scheduling submodule and handles internal memory allocation and release. To maximize the reuse of node memory space while controlling the overall system memory usage, the memory scheduling submodule first sorts the nodes according to the number of non-zero elements in their corresponding columns and divides them into two categories based on the quantity. Nodes in the same category share a memory region in a memory pool. All memory elements in the memory pool managed by this memory scheduling submodule are of the same size, and the size of all memory elements is determined by the column with the largest number of non-zero elements in its corresponding category. Therefore, a memory element can be reused by multiple tasks at different times during the solution process. When a node completes its decomposition work, it releases its memory space, which is then placed into its corresponding memory pool by the memory scheduling submodule. Each memory pool in this memory scheduling submodule is managed through a stack structure. When a memory pool is not empty, the memory region allocated by the memory scheduling submodule to the requester upon receiving a memory allocation request is the most recently returned memory space.

7. The sparse Cholesky decomposition hardware acceleration system for embedded platforms of claim 6, wherein: The rollback calculation module includes a cache consistency management submodule and a CPU rollback algorithm submodule, wherein: The cache consistency management submodule is used to avoid potential inconsistencies caused by the CPU cache when the FPGA-side hardware and CPU-side software jointly read and write to the same memory region. The management framework listens to the read and write status of the two in different memory regions. When one side reads a memory region updated by the other side, the cache consistency management submodule intervenes and performs a cache refresh operation to eliminate the consistency problem. The cache consistency management submodule maintains a consistency flag for each memory region allocated by the parallel scheduling module. When the CPU-side software requests a memory region from the operating system, the memory region is first initialized to a consistent state. When the FPGA-side hardware or CPU-side software performs a write operation on the memory region, the above flag will be updated to the inconsistent state of the corresponding side. In actual calculation, when reading a memory region, if the flag of the region has been updated to an inconsistent state due to a previous write operation on the other side, the CPU cache needs to be flushed to obtain the latest data. The cache flush operation can ensure that all write operations of the CPU cache are executed correctly, while new read operations will request data again from DDR memory. The CPU rollback algorithm submodule implements the sparse Cholesky decomposition algorithm in the CPU-side software. Its algorithm flow is identical to that of the FPGA-side hardware implementation. Leveraging the CPU's high efficiency in random access memory and the fact that algorithms don't require additional data transfer, the submodule performs calculations directly within the existing memory area, without introducing additional memory space for single-column decomposition calculations. This submodule receives computation tasks from the parallel scheduling module in the CPU-side software and completes single-column decomposition calculations according to the processes described in the matrix input and basic operation module, the update matrix generation module, and the extended summation module. Unlike the module deployed in the FPGA-side hardware, the CPU rollback algorithm submodule eliminates the need for indirect data reading from DDR memory, directly performing random access and updates to memory. When performing read / write operations on a memory area, the submodule calls the cache consistency management submodule to ensure that the data being operated on does not produce consistency issues. After completing the calculation, the submodule writes the results to the corresponding column of the matrix storing the calculation results, as well as the Frontal matrix with the parent nodes of the tree removed.

8. The solution method for a hardware-accelerated sparse Cholesky decomposition system for embedded platforms as described in any one of claims 1-7, characterized in that, Includes the following steps: 1) The CPU-side software reads the matrix to be decomposed, the matrix symbolic decomposition result, and the matrix elimination tree structure from the user end; 2) The parallel scheduling module of the CPU-side software obtains all columns that can be computed in parallel and allocates computing tasks; The auxiliary matrix generation module generates the first column of the auxiliary matrix used for the extended addition operation and stores it in memory; The parallel scheduling module then transmits the task data and starts kernel execution; 3) The FPGA-side hardware uses the designed data flow model to read the corresponding data from the DDR memory from the AXI bus according to the given address offset; each module of the FPGA-side hardware executes the calculation task and writes the calculation results back to the DDR memory through the AXI bus. 4) If the parallel scheduling module detects a task that does not meet the operating requirements of the FPGA-side hardware, the rollback calculation module completes the single-column decomposition calculation in the CPU-side software and writes the calculation result to DDR memory. 5) The memory space occupied by the Frontal matrix after the columns have been decomposed is returned to the memory pool through the memory scheduling submodule, thus completing the decomposition of one column; if there are still columns to be decomposed, the decomposition process is repeated from step 2) until all columns of the matrix have been decomposed.

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