Integrated circuit for increasing the connection density of a port

Abstract

The application discloses an integrated circuit capable of increasing port connection distribution rate, which comprises a hard core circuit, a hardware access module, a hardware output module and a programmable gate array device, the hard core circuit is connected with the hardware access module, the hardware access module is connected with the programmable gate array device and the hardware output module respectively, and the hardware output module is connected with the programmable gate array device; the programmable gate array device transmits data to the hard core circuit through the hardware access module, and the hard core circuit transmits data to the programmable gate array device through the hardware access module and the hardware output module in sequence. The application can directly connect the port of a switch box with the port of the hard core circuit, so that the hard core circuit directly communicates with the programmable gate array device through the switch box; on the basis of not increasing the number of connection boxes, the programmable gate array device can be connected with the hard core circuit which has high performance and multiple ports; the number of wirings is reduced, the structure of the circuit is simplified, and the performance of the circuit is improved.

Description

Technical Field

[0001] This invention relates to the field of circuit structure technology, and in particular to an integrated circuit that increases port connection throughput. Background Technology

[0002] As electronic device manufacturing processes become increasingly sophisticated, the size of readily available programmable gate array (PGA) devices, programmable logic resources, switch boxes, and connector boxes is shrinking. Through programmable logic resources, switch boxes, and connector boxes, PGA devices can be integrated with multiple different hard-core circuits, enabling various functional applications in fields such as communications, industrial control, and accelerator boards, including high-speed interfaces, digital signal processors, and block memory.

[0003] Because embedded hard-core circuits are typically designed to perform various functions, a massive amount of logic is incorporated into the initial design for optimization. This logic often requires numerous ports for direct control, resulting in high-performance or feature-rich hard-core circuits having a large number of input / output ports. These ports can only interact with programmable gate arrays (PGAs) via a connector box. Therefore, the common connection method between hard-core circuits and PGAs is that the hard-core circuit is directly connected to the PGA via a connector box and then a switch box. Data output from the hard-core circuit must pass through the connector box and switch box before being transmitted to the PGA.

[0004] However, the commonly used connection methods have the following technical problems: Due to the limitations of the programmable gate array (PGA) device architecture, the number of ports in the connection box is finite. When connecting high-performance hard-core circuits with a large number of ports, a large number of connection boxes are required to interconnect the PGA devices with the hard-core circuits. Increasing the number of connection boxes not only reduces the number of switch boxes but also compresses the wiring layout, thereby affecting circuit performance and reducing the interconnectivity and flexibility of the PGA devices. Summary of the Invention

[0005] This invention proposes an integrated circuit that increases port connectivity. The circuit directly connects the ports of the switch box to the ports of the hard core circuit, enabling the hard core circuit to communicate directly with the programmable gate array (PGA) device through the switch box. This allows the PGA device to connect to the high-performance, multi-port hard core circuit without increasing the number of connection boxes, thereby improving circuit performance while simplifying the circuit structure.

[0006] A first aspect of the present invention provides an integrated circuit for increasing port connection routing rate. The circuit includes: a hard core circuit, a hardware access module, a hardware output module, and a programmable gate array (PGA). The hard core circuit is connected to the hardware access module. The hardware access module is connected to both the PGA and the hardware output module. The hardware output module is connected to the PGA. The programmable gate array device transmits data to the hard core circuit through the hardware access module, and the hard core circuit transmits data to the programmable gate array device in sequence through the hardware access module and the hardware output module; The switch box of the hardware access module and the switch box of the hardware output module are respectively connected to the hard core circuit.

[0007] In one possible implementation of the first aspect, the hardware access module is provided, and the hardware output module is provided; The hardware access module and the hardware output module are respectively located on two sides of the hard core circuit.

[0008] In one possible implementation of the first aspect, there are multiple hardware access modules and multiple hardware output modules; Each of the hardware access modules and each of the hardware output modules are respectively disposed on two sides of the hard core circuit. Multiple hardware access modules are connected in sequence, and multiple hardware output modules are connected in sequence to form an array structure.

[0009] In one possible implementation of the first aspect, the hardware output module includes: a first output switch box, a second output switch box, a first output connection box, a second output connection box, a first programmable logic block, and a second programmable logic block; The first output connection box, the first output switch box, and the first programmable logic block are connected in sequence. The second output connection box, the second output switch box, and the second programmable logic block are connected in sequence; The port of the second output switch box is connected to the port of the hard core circuit.

[0010] In one possible implementation of the first aspect, the hardware access module includes: an access connection box and an access switch box, the access connection box and the access switch box being respectively connected to the hard core circuit, and the access switch box being connected to the programmable gate array device.

[0011] In one possible implementation of the first aspect, the access switch box, the first output switch box, and the second output switch box are provided with a plurality of input terminals and a plurality of output terminals on their sides, and the plurality of input terminals and the plurality of output terminals are used to connect to the hard core circuit or the connection box. Each of the input terminals or each of the output terminals corresponds to an interconnection coefficient.

[0012] In one possible implementation of the first aspect, an output terminal of the access switch box is connected to an input terminal of the programmable gate array device; One input terminal of the second output switch box is connected to one output terminal of the programmable gate array device; The interconnection coefficient of one output terminal of the access switch box is the same as the interconnection coefficient of one input terminal of the second output switch box.

[0013] In one possible implementation of the first aspect, an input terminal of the access switch box is connected to an output terminal of the programmable gate array device; One output terminal of the second output switch box is connected to one input terminal of the programmable gate array device; The interconnection coefficient of one input terminal of the access switch box is the same as the interconnection coefficient of one output terminal of the second output switch box.

[0014] In one possible implementation of the first aspect, the access connection box, the first output connection box and the second output connection box are respectively provided with a switch input terminal and a switch output terminal connected to the switch box, and are respectively provided with a hardware input terminal and a hardware output terminal connected to the hard core circuit, and each port is a set of buses, and each set of buses contains several connection lines.

[0015] In one possible implementation of the first aspect, the first programmable logic block and the second programmable logic block are respectively provided with connection input terminals and connection output terminals connected to the connection box, and each port is a set of buses, and each set of buses contains several connection lines.

[0016] Compared with the prior art, the integrated circuit provided by the embodiments of the present invention to increase the port connection throughput has the following advantages: the present invention can directly connect the port of the switch box to the port of the hard core circuit, so that the hard core circuit can communicate directly with the programmable gate array device through the switch box. Without increasing the number of connection boxes, the programmable gate array device can be connected to the high-performance and multi-port hard core circuit, which can not only reduce the number of wiring and simplify the circuit structure, but also greatly improve the performance of the circuit. Attached Figure Description

[0017] Figure 1This is a schematic diagram of the structure of an integrated circuit that increases port connection throughput according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a switch box provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a connecting box provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a programmable logic block provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of a single-layer array of an integrated circuit that increases port connection throughput according to an embodiment of the present invention; Figure 6 This is a schematic diagram of a multilayer array of an integrated circuit that increases port connection throughput according to an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] To address the aforementioned issues, the following detailed description and explanation will be provided through specific embodiments of an integrated circuit that increases port connection throughput according to the present application.

[0020] Reference Figure 1 The diagram shows a schematic of the structure of an integrated circuit that increases port connection throughput according to an embodiment of the present invention.

[0021] As an example, the integrated circuit that increases port connection throughput may include: a hard core circuit, a hardware access module, a hardware output module, and a programmable gate array (FPGA).

[0022] The hard core circuit is connected to the hardware access module, the hardware access module is connected to the programmable gate array device and the hardware output module respectively, and the hardware output module is connected to the programmable gate array device.

[0023] The programmable gate array device transmits data to the hard core circuit through the hardware access module, and the hard core circuit transmits data to the programmable gate array device in sequence through the hardware access module and the hardware output module.

[0024] The switch box of the hardware access module and the switch box of the hardware output module are respectively connected to the hard core circuit.

[0025] It should be noted that the switch box (SB) can be a network switching switch box. In a hard-core circuit, all logic ports that can be operated by the FPGA user are connected to the switch box (SB). In practice, the more ports the hard-core circuit can have connected to the switch box, the greater its flexibility and operability within the FPGA.

[0026] In one embodiment, the hardware output module includes: a first output switch box, a second output switch box, a first output connection box, a second output connection box, a first programmable logic block, and a second programmable logic block; The first output connection box, the first output switch box, and the first programmable logic block are connected in sequence. The second output connection box, the second output switch box, and the second programmable logic block are connected in sequence; The port of the second output switch box is connected to the port of the hard core circuit.

[0027] In one embodiment, the hardware access module includes an access connection box and an access switch box, the access connection box and the access switch box being connected to the hard core circuit respectively, and the access switch box being connected to the programmable gate array device.

[0028] In one embodiment, the access switch box, the first output switch box, and the second output switch box can be the same switch box.

[0029] Specifically, the switch box can be the network switching switch box (SB) described above.

[0030] In one embodiment, the access connection box, the first output connection box, and the second output connection box can be the same connection box.

[0031] Specifically, the connection box can be a cable connection box (CB).

[0032] In one embodiment, the first programmable logic block and the second programmable logic block may be the same programmable logic block.

[0033] Specifically, the programmable logic block can be a programmable logic resource (CLB, Configurable Logic Block).

[0034] In one embodiment, the access switch box, the first output switch box, and the second output switch box are provided with a plurality of input terminals and a plurality of output terminals on their sides, and the plurality of input terminals and the plurality of output terminals are used to connect to the hard core circuit or the connection box. Each of the input terminals or each of the output terminals corresponds to an interconnection coefficient.

[0035] Reference Figure 2 The diagram shows a schematic structural diagram of a switch box provided in an embodiment of the present invention.

[0036] In one implementation, the aforementioned access switch box, first output switch box, and second output switch box are provided with an input terminal TIN and an output terminal TOUT on one side. The two ports can be used to connect to a programmable gate array (FPGA). The FPGA transmits data to the switch box through the input terminal TIN, and the switch box transmits data to the FPGA through the output terminal TOUT.

[0037] Reference Figure 2 Each of the aforementioned access switch box, first output switch box, and second output switch box has an input terminal (BIN) and an output terminal (BOUT) on one side. These two ports can be used to connect to other switch boxes, enabling data transmission between them.

[0038] Reference Figure 2 The aforementioned access switch box, first output switch box, and second output switch box each have three input terminals and three output terminals on one side. The three input terminals are L1in, L0.5in, and L0.25in, respectively; the three output terminals are L1out, L0.5out, and L0.25out, respectively. The three input terminals can be used to connect to switch boxes on the same array layer or side to receive data from switch boxes on the same side. The three output ports can also be used to connect to switch boxes on the same array layer or side to transmit data to switch boxes on the same side.

[0039] In this diagram, the numbers 1, 0.5, and 0.25 represent the interconnection coefficients, with each port corresponding to one coefficient. The interconnection coefficient indicates the flexibility of port interconnection; a higher number indicates greater flexibility. The maximum interconnection coefficient is 1, and the minimum is 0.

[0040] For example, when the interconnect factor is 1, it means that all input ports can be connected one-to-one to the output port via a selector (MUX) in the switch box circuit. When the interconnect factor is 0.5, it means that only half of the input ports can be connected one-to-one to the output port via a selector (MUX) in the switch box circuit. When the interconnect factor is 0.25, only one-quarter of the input ports can be connected one-to-one to the output port via a selector (MUX) in the switch box circuit.

[0041] Correspondingly, three input terminals and three output terminals are also provided on the other side of the access switch box, the first output switch box, and the second output switch box. The three input terminals are R1in, R0.5in, and R0.25in, respectively; the three output terminals are R1out, R0.5out, and R0.25out, respectively. The numbers of each port can also be represented as interconnection coefficients.

[0042] Similarly, the three input ports can also be used to connect to individual switch boxes on the same array layer or side to receive data from switch boxes on the same side. The three output ports can also be used to connect to individual switch boxes on the same array layer or side to transmit data to switch boxes on the same side.

[0043] Figure 3 This is a schematic diagram of the structure of a connection box provided in an embodiment of the present invention.

[0044] In one embodiment, one side of the access connection box, the first output connection box, and the second output connection box is provided with a switch input terminal SBIN and a switch output terminal SBOUT connected to the switch box; the other side of the access connection box, the first output connection box, and the second output connection box is provided with a hardware input terminal IPIN and a hardware output terminal IPOUT connected to the hard core circuit.

[0045] In one embodiment, the switch input terminal SBIN is used to receive data transmitted from the switch box, and the switch output terminal SBOUT is used to transmit data to the switch box. The hardware input terminal IPIN is used to receive data transmitted from the hard core circuit, and the hardware output terminal IPOUT is used to transmit data to the hard core circuit.

[0046] It should be noted that the switch input terminal SBIN, the switch output terminal SBOUT, the hardware input terminal IPIN, and the hardware output terminal IPOUT are all part of a bus group, and each bus group contains several connection lines. Specifically, each bus group contains 8 connection lines.

[0047] Figure 4 This is a schematic diagram of the structure of a programmable logic block provided in an embodiment of the present invention.

[0048] In one embodiment, the first programmable logic block and the second programmable logic block are respectively provided with a connection input terminal CLB_CBIN and a connection output terminal CLB_CBOUT connected to the connection box.

[0049] The connection input terminal CLB_CBIN is used to receive data transmitted from the connection box, and the connection output terminal CLB_CBOUT is used to transmit data to the connection box.

[0050] It should be noted that the input terminal CLB_CBIN and the output terminal CLB_CBOUT form a bus group, and each bus group contains several connection lines. Specifically, each bus group contains 8 connection lines.

[0051] Reference Figure 5 The diagram shows a schematic of a single-layer array of an integrated circuit that increases port connectivity according to an embodiment of the present invention.

[0052] In an optional embodiment, the hardware access module is provided, and the hardware output module is provided; The hardware access module and the hardware output module are respectively located on two sides of the hard core circuit.

[0053] To distinguish between the various switch boxes, connection boxes, and programmable logic blocks, refer to the following: Figure 5 The first output switch box is SBx0y3, the second output switch box is SBx2y3, the first output connection box is CB-x0y3L, the second output connection box is CB-x2y3R, the first programmable logic block is CLB-x0y3L, and the second programmable logic block is CLB-x2y3R. The access connection box is CB-x1y3L, and the access switch box is SBx1y3.

[0054] Reference Figure 6 The diagram shows a schematic of a multilayer array of an integrated circuit that increases port connectivity according to an embodiment of the present invention.

[0055] In another optional embodiment, there are multiple hardware access modules and multiple hardware output modules.

[0056] Each of the hardware access modules and each of the hardware output modules are respectively located on two sides of the hard core circuit.

[0057] Multiple hardware access modules are connected sequentially, and multiple hardware output modules are connected sequentially to form an array-like structure, as shown in the following example. Figure 6 As shown.

[0058] In an FPGA, the hard core circuit needs to interact with the FPGA by sending signals, which can be done according to... Figure 6 The connection is made using the following method. To distinguish between the various switch boxes, connection boxes, and programmable logic blocks, specifically, as follows: Figure 6 As shown, the FPGA is presented in an array form. A two-dimensional rectangular coordinate system can be established with the horizontal axis as the x-coordinate, the vertical axis as the y-coordinate, the switch box as the counting unit, and the switch box in the lower left corner as the origin. Then, each device is labeled according to the coordinate system.

[0059] Correspondingly, in Figure 6In this example, there are four hardware access modules and four hardware output modules. The switch boxes, connection boxes, and programmable logic blocks in each row are numbered as follows: Specifically, the switch box, connection box, and programmable logic block in the first row are as follows: the first output switch box is SBx0y0, the second output switch box is SBx2y0, the first output connection box is CB-x0y0L, the second output connection box is CB-x2y0R, the first programmable logic block is CLB-x0y0L, the second programmable logic block is CLB-x2y0R, the access connection box is CB-x1y0L, and the access switch box is SBx1y0.

[0060] The switch box, connection box, and programmable logic block in the second row are as follows: the first output switch box is SBx0y1, the second output switch box is SBx2y1, the first output connection box is CB-x0y1L, the second output connection box is CB-x2y1R, the first programmable logic block is CLB-x0y1L, the second programmable logic block is CLB-x2y1R, the access connection box is CB-x1y1L, and the access switch box is SBx1y1.

[0061] The switch box, connection box, and programmable logic block in the third row are as follows: the first output switch box is SBx0y2, the second output switch box is SBx2y2, the first output connection box is CB-x0y2L, the second output connection box is CB-x2y2R, the first programmable logic block is CLB-x0y2L, the second programmable logic block is CLB-x2y2R, the access connection box is CB-x1y2L, and the access switch box is SBx1y2.

[0062] The switch box, connection box, and programmable logic block in the fourth row are as follows: the first output switch box is SBx0y3, the second output switch box is SBx2y3, the first output connection box is CB-x0y3L, the second output connection box is CB-x2y3R, the first programmable logic block is CLB-x0y3L, the second programmable logic block is CLB-x2y3R, the access connection box is CB-x1y3L, and the access switch box is SBx1y3.

[0063] When it is necessary to connect a switch box and a programmable gate array (PLA) device, in one embodiment, an output terminal of the access switch box is connected to an input terminal of the PLA device; an input terminal of the second output switch box is connected to an output terminal of the PLA device; and the interconnection coefficient of the output terminal of the access switch box is the same as the interconnection coefficient of the input terminal of the second output switch box.

[0064] Specifically, you can refer to Figure 5Alternatively, 6. When the number of ports in the hard-core circuit is large, in order to solve the port resource problem, the interface of the switch box port can be disconnected and given to the hard-core circuit as an interface resource, such as... Figure 5 As shown or as Figure 6 As shown in the fourth line, the output terminal of the access switch box passing through the hard core circuit in the R direction is connected to the input terminal of the hard core circuit, and the input terminal of the second output switch box passing through the hard core circuit in the L direction is connected to the output terminal of the hard core circuit. This doubles the number of ports while keeping the circuit itself unchanged. Simultaneously, since the hard core circuit is directly connected to the switch box, it can quickly reach other CLBs and interact with the FPGA via highly interconnected traces.

[0065] Similarly, if the core circuit has a large number of interfaces and the interface requirements are still high, referring to the above method, in one embodiment, one input terminal of the access switch box can be connected to one output terminal of the programmable gate array device; one output terminal of the second output switch box can be connected to one input terminal of the programmable gate array device; and the interconnection coefficient of one input terminal of the access switch box is the same as the interconnection coefficient of one output terminal of the second output switch box.

[0066] Specifically, refer to Figure 5 or Figure 6 As shown in the fourth line, the output terminal of the second output switch box passing through the hard core circuit in the L direction can be connected to the input terminal of the hard core circuit, and the input terminal of the access switch box passing through the hard core circuit in the R direction can be connected to the output terminal of the hard core circuit, further increasing the port connectivity.

[0067] When there are multiple hardware access modules and multiple hardware output modules, and the hard core circuit has a large number of ports, in one embodiment, one output terminal of each row of access switch boxes can be connected to one input terminal of the programmable gate array (PGA) device, and one input terminal of the second output switch box can be connected to one output terminal of the PGA device. Furthermore, one input terminal of the access switch box can be connected to one output terminal of the PGA device, and one output terminal of the second output switch box can be connected to one input terminal of the PGA device.

[0068] Since the interconnection coefficients of different ports may differ, in a preferred embodiment, ports with an interconnection coefficient of 0.25 in each row can be connected first. For example, the switch box ports with an interconnection coefficient of 0.25 in the first row can be connected to the hard core circuit; then, the switch box ports with an interconnection coefficient of 0.25 in the second row can be connected to the hard core circuit, and so on, until all switch box ports with an interconnection coefficient of 0.25 in each row are connected. Then, the switch box ports with an interconnection coefficient of 0.5 in the first row can be connected to the hard core circuit, and so on.

[0069] Using cabling resources with high throughput or high interconnectivity will consume internal switching nodes, thus reducing the throughput. Conversely, using cabling with low throughput or low interconnectivity, which is used less frequently, will prioritize its throughput, occupying previously occupied cabling channels and forcing high-throughput cabling to switch cabling methods, thereby further improving the throughput.

[0070] The primary purpose of this invention is to reduce wiring congestion when hard-core circuits are used in FPGAs, which is the fundamental mechanism. Using the above circuitry offers the following advantages: First, it reduces additional connecting lines, simplifies the wiring structure, and reduces surge signals, avoiding their impact. Because excessively congested or dense wiring requires constantly depleting the switching transistors in the switching box for selection, a large number of transistors conducting simultaneously and transmitting transition signals can cause the chip voltage to drop during these signal transitions. Furthermore, wiring congestion can lead to a surge in the number of signals, which can easily cause signal integrity issues. The structure disclosed in this invention avoids these problems.

[0071] Secondly, it reduces chip operating temperature and avoids signal timing issues. Chip speed performance is affected by process technology, voltage, and temperature. Low throughput leading to voltage drops further reduces chip speed, resulting in performance degradation. The simplified structure described above avoids these problems.

[0072] Compared to traditional methods that sacrifice programmable logic blocks (CLBs) to replace them with connection boxes (CBs), or methods that control the number of hard-core circuit ports via a bus, this invention provides additional routing ports to the hard-core circuit without consuming CLBs or increasing the hard-core circuit area. This enhances the interoperability between the hard-core circuit ports and the FPGA, further making the FPGA more flexible. It is worth noting that although the routing around the hard-core resources of the FPGA is reduced, the overall routing efficiency is not affected because we use low-route-rate routing resources. Furthermore, the routing directly connecting the switch box (SB) to the hard-core circuit mentioned in this invention is not limited to a specific direction or number; it can be adjusted according to the needs of the chip scenario, further increasing the flexibility of circuit layout.

[0073] In this embodiment, the present invention provides an integrated circuit that increases port connection throughput. Its beneficial effects are as follows: the present invention can directly connect the port of the switch box to the port of the hard core circuit, so that the hard core circuit can communicate directly with the programmable gate array device through the switch box. Without increasing the number of connection boxes, the programmable gate array device can be connected to the high-performance and multi-port hard core circuit. This not only reduces the number of wiring and simplifies the circuit structure, but also greatly improves the performance of the circuit.

[0074] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application for those skilled in the art.

Claims

1. An integrated circuit that increases port connection routing rate, characterized in that, The circuit includes: a hard core circuit, a hardware access module, a hardware output module, and a programmable gate array (PGA). The hard core circuit is connected to the hardware access module. The hardware access module is connected to both the PGA and the hardware output module. The hardware output module is connected to the PGA. The programmable gate array device transmits data to the hard core circuit through the hardware access module, and the hard core circuit transmits data to the programmable gate array device in sequence through the hardware access module and the hardware output module; The switch box of the hardware access module and the switch box of the hardware output module are respectively connected to the hard core circuit. The hardware output module includes: a first output switch box, a second output switch box, a first output connection box, a second output connection box, a first programmable logic block, and a second programmable logic block; The first output connection box, the first output switch box, and the first programmable logic block are connected in sequence. The second output connection box, the second output switch box, and the second programmable logic block are connected in sequence; The port of the second output switch box is connected to the port of the hard core circuit; The hardware access module includes an access connection box and an access switch box, the access connection box and the access switch box being connected to the hard core circuit respectively, and the access switch box being connected to the programmable gate array device; The access switch box, the first output switch box, and the second output switch box are provided with a plurality of input terminals and a plurality of output terminals on their sides, and the plurality of input terminals and the plurality of output terminals are used to connect to the hard core circuit or the connection box. Each of the input terminals or each of the output terminals corresponds to an interconnection coefficient.

2. The integrated circuit for increasing port connection throughput according to claim 1, characterized in that, One hardware access module and one hardware output module are provided; The hardware access module and the hardware output module are respectively located on two sides of the hard core circuit.

3. The integrated circuit for increasing port connection throughput according to claim 1, characterized in that, The hardware access module is provided in multiple ways, and the hardware output module is provided in multiple ways; Each of the hardware access modules and each of the hardware output modules are respectively disposed on two sides of the hard core circuit. Multiple hardware access modules are connected in sequence, and multiple hardware output modules are connected in sequence to form an array structure.

4. The integrated circuit for increasing port connection throughput according to claim 1, characterized in that, One output terminal of the access switch box is connected to one input terminal of the programmable gate array device; One input terminal of the second output switch box is connected to one output terminal of the programmable gate array device; The interconnection coefficient of one output terminal of the access switch box is the same as the interconnection coefficient of one input terminal of the second output switch box.

5. The integrated circuit for increasing port connection throughput according to claim 1, characterized in that, One input terminal of the access switch box is connected to one output terminal of the programmable gate array device; One output terminal of the second output switch box is connected to one input terminal of the programmable gate array device; The interconnection coefficient of one input terminal of the access switch box is the same as the interconnection coefficient of one output terminal of the second output switch box.

6. The integrated circuit for increasing port connection throughput according to claim 1, characterized in that, The access connection box, the first output connection box, and the second output connection box are respectively provided with a switch input terminal and a switch output terminal connected to the switch box, and respectively provided with a hardware input terminal and a hardware output terminal connected to the hard core circuit. Each port is a bus, and each bus contains several connection lines.

7. The integrated circuit for increasing port connection throughput according to claim 1, characterized in that, The first programmable logic block and the second programmable logic block are respectively provided with connection input terminals and connection output terminals connected to the connection box, and each port is a group of buses, and each group of buses contains several connection lines.

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