Shift register, pixel driving circuit and display device

Abstract

This disclosure provides a shift register, belonging to the field of display technology. The shift register of this disclosure includes a pre-charge sub-circuit, a storage sub-circuit, a duty cycle adjustment sub-circuit, a NOT gate, and an output sub-circuit; wherein, the pre-charge sub-circuit includes a third transistor; the storage sub-circuit includes a storage capacitor; the duty cycle adjustment sub-circuit includes a first transistor and a second transistor; the NOT gate includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; and the output sub-circuit includes an eighth transistor, a ninth transistor, and a tenth transistor.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a shift register, a pixel driving circuit, and a display device. Background Technology

[0002] With the development of Augmented Reality (AR) and Virtual Reality (VR) technologies, the pixel density (PPI) of display products has been greatly improved. To better accommodate display products with high PPI and extremely narrow bezels, the area of ​​the GoA (Graphical Object Array) circuit needs to be further reduced. However, the thin-film transistors (TFTs) in existing GOA circuits have a large aspect ratio, a large number of signals, and complex noise reduction.

[0003] Based on the above problems, the inventors proposed a novel GOA circuit, which includes fewer TFTs and uses the same aspect ratio design, which can significantly reduce the area occupied by the TFTs, thereby reducing the GOA area. In addition, the GOA circuit in this disclosure only requires the previous row to trigger the output of the current row, without the need for reset and complex noise reduction design, which simplifies the manufacturing process, reduces the defect rate, and increases stability. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art, and to provide a shift register, a pixel driving circuit and a display device.

[0005] In a first aspect, embodiments of this disclosure provide a shift register, which includes: a precharge sub-circuit, a storage sub-circuit, a duty cycle adjustment sub-circuit, a NOT gate, and an output sub-circuit;

[0006] The pre-charge sub-circuit is configured to transmit a first-level signal to a first node in response to an input signal; the first node is the connection node of the pre-charge sub-circuit, the storage sub-circuit, and the duty cycle adjustment sub-circuit.

[0007] The duty cycle adjustment sub-circuit is configured to transmit a first clock signal to the first node in response to the first node voltage;

[0008] The storage sub-circuit is configured to control the operating duration of the duty cycle adjustment sub-circuit based on the signal output voltage and the first node voltage; the NOT gate is configured to transmit either the first level signal or the second level signal to the second node in response to the first node voltage; the output sub-circuit is configured to output either the second clock signal or the second level signal to the signal output terminal in response to the first node voltage and the input signal voltage; or, the output sub-circuit is configured to output the second level signal to the signal output terminal in response to the second node voltage and the third node voltage; the second node is the connection node between the NOT gate and the output sub-circuit; the third node is the connection node between the signal input terminal and the output sub-circuit.

[0009] Alternatively, the storage sub-circuit is configured to control the operating duration of the duty cycle adjustment sub-circuit based on the signal output voltage and the first node voltage; the NOT gate is configured to transmit the second level signal or the fifth level signal to the third node in response to the input signal; the output sub-circuit is configured to output the first level signal or the second level signal to the signal output terminal in response to the second node voltage and the third node voltage; the second node is the connection node between the duty cycle adjustment sub-circuit and the output sub-circuit; the third node is the connection node between the NOT gate and the output sub-circuit.

[0010] Alternatively, the storage sub-circuit is configured to control the operating duration of the duty cycle adjustment sub-circuit based on the second level signal and the first node voltage; the NOT gate is configured to transmit either the first level signal or the second level signal to the second node in response to the first node voltage; the output sub-circuit is configured to output either the first level signal or the second level signal to the signal output terminal in response to the second node voltage and the third node voltage; the second node is the connection node between the NOT gate and the output sub-circuit; and the third node is the connection node between the signal input terminal and the output sub-circuit.

[0011] Preferably, the pre-charge sub-circuit includes: a third transistor; the control electrode of the third transistor is connected to the signal input terminal, the first electrode is connected to the first node, and the second electrode is connected to the first level signal terminal.

[0012] Preferably, the duty cycle adjustment sub-circuit includes: a first transistor and a second transistor; the control electrode of the first transistor is connected to the first node, the first electrode is connected to the first clock signal terminal, and the second electrode is connected to the first electrode of the second transistor;

[0013] The control electrode of the second transistor is connected to the first node, the first electrode is connected to the second electrode of the first transistor, and the second electrode is connected to the first node.

[0014] Preferably, the storage sub-circuit includes a first storage capacitor.

[0015] Preferably, when the storage sub-circuit is configured to control the operating duration of the duty cycle adjustment sub-circuit based on the signal output voltage and the first node voltage, one terminal of the first storage capacitor is connected to the signal output terminal, and the other terminal is connected to the first node.

[0016] Preferably, when the storage sub-circuit is configured to control the operating duration of the duty cycle adjustment sub-circuit according to the second level signal and the first node voltage, one terminal of the first storage capacitor is connected to the second level signal terminal, and the other terminal is connected to the first node.

[0017] Preferably, the NOT gate includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor.

[0018] Preferably, when the NOT gate is configured to respond to the first node voltage,

[0019] The control electrode of the fourth transistor is connected to the first node, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the fourth node; the fourth node is the connection node between the second electrode of the fourth transistor and the first electrode of the fifth transistor.

[0020] The control electrode of the fifth transistor is connected to the first level signal terminal, the first electrode is connected to the fourth node, and the second electrode is connected to the first level signal terminal.

[0021] The control electrode of the sixth transistor is connected to the first node, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the second node.

[0022] The control electrode of the seventh transistor is connected to the fourth node, the first electrode is connected to the second node, and the second electrode is connected to the first level signal terminal.

[0023] Preferably, when the NOT gate is configured to respond to an input signal,

[0024] The control electrode of the fourth transistor is connected to the fifth level signal terminal, the first electrode is connected to the fifth level signal terminal, and the second electrode is connected to the fourth node.

[0025] The control electrode of the fifth transistor is connected to the signal input terminal, the first electrode is connected to the fourth node, and the second electrode is connected to the second level signal terminal.

[0026] The control electrode of the sixth transistor is connected to the fourth node, the first electrode is connected to the fifth level signal terminal, and the second electrode is connected to the third node.

[0027] The control electrode of the seventh transistor is connected to the signal input terminal, the first electrode is connected to the third node, and the second electrode is connected to the second level signal terminal.

[0028] Preferably, the output sub-circuit includes: an eighth transistor, a ninth transistor, and a tenth transistor.

[0029] Preferably, when the output sub-circuit is configured to output a second clock signal or a second level signal to the signal output terminal in response to the first node voltage and the input signal voltage, or when the output sub-circuit is configured to output a second level signal to the signal output terminal in response to the second node voltage and the third node voltage,

[0030] The control electrode of the eighth transistor is connected to the signal input terminal, the first electrode is connected to the signal output terminal, and the second electrode is connected to the second level signal terminal;

[0031] The control electrode of the ninth transistor is connected to the second node, the first electrode is connected to the signal output terminal, and the second electrode is connected to the second level signal terminal.

[0032] The control electrode of the tenth transistor is connected to the first node, the first electrode is connected to the second clock signal terminal, and the second electrode is connected to the signal output terminal.

[0033] Preferably, when the output sub-circuit is configured to output either the first level signal or the second level signal to the signal output terminal in response to the second node voltage and the third node voltage,

[0034] The control electrode of the eighth transistor is connected to the third node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first electrode of the ninth transistor;

[0035] The control electrode of the ninth transistor is connected to the second node, the first electrode is connected to the second electrode of the eighth transistor, and the second electrode is connected to the signal output terminal;

[0036] The control electrode of the tenth transistor is connected to the fourth level signal terminal, the first electrode is connected to the signal output terminal, and the second electrode is connected to the second level signal terminal.

[0037] Preferably, when the output sub-circuit is configured to output either the first level signal or the second level signal to the signal output terminal in response to the second node voltage and the third node voltage,

[0038] The control electrode of the eighth transistor is connected to the signal input terminal, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the signal output terminal;

[0039] The control electrode of the ninth transistor is connected to the second node, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the signal output terminal.

[0040] The control electrode of the tenth transistor is connected to the first level signal terminal, the first electrode is connected to the signal output terminal, and the second electrode is connected to the first level signal terminal.

[0041] Secondly, embodiments of this disclosure provide a pixel driving circuit, wherein the pixel driving circuit includes: a plurality of cascaded shift registers as described above;

[0042] The signal input terminal of the shift register described in this stage is connected to the signal output terminal of the shift register described in the previous stage.

[0043] Thirdly, embodiments of this disclosure provide a display device, wherein the display device includes the pixel driving circuit described above. Attached Figure Description

[0044] Figure 1 A schematic diagram of the structure of a shift register for the first example provided in this disclosure;

[0045] Figure 2 A schematic diagram of the structure of a shift register for the second example provided in this disclosure;

[0046] Figure 3 A schematic diagram of the shift register structure provided in this disclosure for the third example;

[0047] Figure 4 Simulation results of a shift register for the first example provided in this disclosure;

[0048] Figure 5 Simulation results of the shift registers for the first to third examples provided in this disclosure;

[0049] Figure 6 Simulation results of a three-stage cascaded circuit of a shift register, which is the first example provided in this disclosure;

[0050] Figure 7 A schematic diagram of the shift register structure for the fourth example provided in this disclosure;

[0051] Figure 8 A schematic diagram of the shift register structure provided in this disclosure for the fifth example;

[0052] Figure 9A schematic diagram of the shift register structure provided in this disclosure for the sixth example;

[0053] Figure 10 Simulation results of the shift register for the fourth example provided in this disclosure;

[0054] Figure 11 Simulation results for the shift registers of the fourth to sixth examples provided in this disclosure;

[0055] Figure 12 Simulation results of a three-stage cascaded circuit of a shift register, which is the fourth example provided in this disclosure. Detailed Implementation

[0056] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0057] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0058] It should be noted that the transistors in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. The switching characteristics of the transistors in the embodiments of this disclosure can be N-type or P-type. In order to achieve duty cycle adjustment, the switching characteristics of each transistor in the same embodiment are the same.

[0059] In this embodiment, the source and drain of each transistor are structurally identical and interchangeable. The terminology used here is to distinguish the two terminals (excluding the gate), with one terminal referred to as the source and the other as the drain. The first terminal can be the source, and the second terminal can be the drain. For an N-type transistor, the transistor is turned on when a high-level signal is input to the gate and turned off when a low-level signal is input to the gate. For a P-type transistor, the transistor is turned on when a low-level signal is input to the gate and turned off when a high-level signal is input to the gate.

[0060] In this embodiment of the disclosure, the first level signal can be a high level signal or a low level signal, depending on the switching characteristics of the transistor. The input signal can be an STV signal or the output signal of the previous stage circuit. The first clock signal and the second clock signal are both square wave signals with a certain duty cycle, and the period of the second clock signal is half of the period of the first clock signal.

[0061] In this embodiment of the disclosure, the first node is the connection node of the storage sub-circuit, the pre-charge sub-circuit and the duty cycle adjustment sub-circuit, the second node is the node of the control electrode port of the ninth transistor, and the third node is the node of the control electrode port of the eighth transistor.

[0062] In a first aspect, embodiments of this disclosure provide a shift register with duty cycle adjustment function, the shift register including a precharge sub-circuit, a storage sub-circuit, a duty cycle adjustment sub-circuit, an NOT gate, and an output sub-circuit.

[0063] In some examples, the precharge sub-circuit includes a third transistor. The gate of the third transistor is connected to the signal input terminal, the first terminal of the third transistor is connected to the first node, and the second terminal of the third transistor is connected to the first level signal terminal. The gate of the third transistor responds to the input signal and is turned on or off under the control of the input signal. When the third transistor is on, it transmits the first level signal to the first node. The first node is the connection node of the precharge sub-circuit, the storage sub-circuit, and the duty cycle adjustment sub-circuit. By adjusting the duty cycle of the input signal, the duration of the high voltage signal at the first node can be adjusted.

[0064] In some examples, the storage sub-circuit includes a first storage capacitor, one pole of which is connected to a first node and the other pole is connected to a signal output terminal. The discharge and charging time of the first storage capacitor is controlled by the voltage difference between the two poles, thereby controlling the operating time of the duty cycle adjustment sub-circuit.

[0065] In other examples, the storage sub-circuit includes a first storage capacitor, one pole of which is connected to a first node and the other pole is connected to a second level signal terminal. The discharge and charging time of the first storage capacitor is controlled by the voltage difference between the two poles, thereby controlling the operating time of the duty cycle adjustment sub-circuit.

[0066] In some examples, the duty cycle adjustment sub-circuit includes a first transistor and a second transistor. The gates of both the first and second transistors are connected to a first node. The first terminal of the first transistor is connected to a first clock signal, and the second terminal of the first transistor is connected to the first terminal of the second transistor. The second terminal of the second transistor is connected to the first node. The gates of both transistors are turned on or off in response to the voltage of the first node. When the first and second transistors are on, the first clock signal is transmitted to the first node. The duty cycle adjustment sub-circuit can adjust the duration for which the first clock signal is written to the first node.

[0067] In some examples, the NOT gate includes a fourth, fifth, sixth, and seventh transistor, and is configured to respond to a first node voltage. The control electrode of the fourth transistor is connected to the first node, its first electrode is connected to a second-level signal terminal, and its second electrode is connected to the fourth node, which is a connection point between the second electrode of the fourth transistor and the first electrode of the fifth transistor. The control electrode of the fifth transistor is connected to the first-level signal terminal, its first electrode is connected to the fourth node, and its second electrode is also connected to the first-level signal terminal. The control electrode of the sixth transistor is connected to the first node, its first electrode is connected to the second-level signal terminal, and its second electrode is connected to the second node. The control electrode of the seventh transistor is connected to the fourth node, its first electrode is connected to the second node, and its second electrode is connected to the first-level signal terminal. A high-level signal passes through the NOT gate and outputs a low-level signal; a low-level signal passes through the NOT gate and outputs a high-level signal.

[0068] In other examples, the NOT gate includes a fourth, fifth, sixth, and seventh transistor, and is configured to respond to an input signal. The control electrode of the fourth transistor is connected to a fifth-level signal terminal, its first electrode is connected to the fifth-level signal terminal, and its second electrode is connected to a fourth node. The control electrode of the fifth transistor is connected to the signal input terminal, its first electrode is connected to the fourth node, and its second electrode is connected to a second-level signal terminal. The control electrode of the sixth transistor is connected to the fourth node, its first electrode is connected to the fifth-level signal terminal, and its second electrode is connected to a third node. The control electrode of the seventh transistor is connected to the signal input terminal, its first electrode is connected to the third node, and its second electrode is connected to a level signal terminal. A high-level signal passes through the NOT gate and outputs a low-level signal; a low-level signal passes through the NOT gate and outputs a high-level signal.

[0069] In some examples, the output sub-circuit includes an eighth, ninth, and tenth transistor, and is configured to output a second clock signal or a second-level signal to a signal output terminal in response to a first node voltage and an input signal voltage; alternatively, the output sub-circuit is configured to output a second-level signal to a signal output terminal in response to a second node voltage and a third node voltage. The control electrode of the eighth transistor is connected to the signal input terminal, while its first electrode is connected to the signal output terminal and its second electrode is connected to the second-level signal terminal. The control electrode of the ninth transistor is connected to the second node, its first electrode is connected to the signal output terminal, and its second electrode is connected to the second-level signal terminal. The control electrode of the tenth transistor is connected to the first node, its first electrode is connected to the second clock signal terminal, and its second electrode is connected to the signal output terminal. The eighth, ninth, and tenth transistors together constitute a NOR gate or a NAND gate to output the signal.

[0070] In other examples, the output sub-circuit includes an eighth, ninth, and tenth transistor, and is configured to output a first-level signal or a second-level signal to a signal output terminal in response to the second and third node voltages. The control electrode of the eighth transistor is connected to the third node, its first electrode is connected to the first-level signal terminal, its second electrode is connected to the first electrode of the ninth transistor, the control electrode of the ninth transistor is connected to the second node, its first electrode is connected to the second electrode of the eighth transistor, and its second electrode is connected to the signal output terminal. The control electrode of the tenth transistor is connected to a fourth-level signal terminal, its first electrode is connected to the signal output terminal, and its second electrode is connected to the second-level signal terminal. The eighth, ninth, and tenth transistors together form an AND or OR gate to output the signal.

[0071] In other examples, the output sub-circuit includes an eighth, ninth, and tenth transistor, and is configured to output a first-level signal or a second-level signal to a signal output terminal in response to the second node voltage and the third node voltage. The control electrode of the eighth transistor is connected to the signal input terminal, its first electrode is connected to the second-level signal terminal, and its second electrode is connected to the signal output terminal. The control electrode of the ninth transistor is connected to the second node, its first electrode is connected to the second-level signal terminal, and its second electrode is connected to the signal output terminal. The control electrode of the tenth transistor is connected to the first-level signal terminal, its first electrode is connected to the signal output terminal, and its second electrode is connected to the first-level signal terminal. The eighth, ninth, and tenth transistors together constitute a NOR gate or a NAND gate to output the signal.

[0072] The shift register provided in this embodiment is equipped with a duty cycle adjustment sub-circuit, which can generate a clock signal with an adjustable duty cycle. In this case, the trigger circuit can be applied to the pixel driving circuit to control the turn-on time of the driving transistor according to the clock signal generated by the shift register, thereby controlling the light emission brightness of the light-emitting device.

[0073] To better illustrate the shift register in the embodiments of this disclosure, the touch controller circuit in the embodiments of this disclosure will be specifically described below with reference to specific examples.

[0074] First example: Figure 1 This is a schematic diagram of a shift register according to a first example of an embodiment of this disclosure; as shown Figure 1 As shown, the shift register includes a precharge sub-circuit 1, a storage sub-circuit 2, a duty cycle adjustment sub-circuit 3, a NOT gate 4, and a NOR gate 501. The following simulation uses only the following conditions: the first level signal VDD = 10V, the second level signal VSS = -10V, the high level of the first clock signal CLK1 is 15V, the low level is -15V, the high level of the second clock signal CLKH1 is 10V, and the low level is -10V; the storage capacitor C1 = 1μf; and the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are all N-type transistors. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0075] The circuit includes a pre-charge sub-circuit 1, a third transistor M3, a storage sub-circuit 2, a C1, a duty cycle adjustment sub-circuit 3, a first transistor M1, and a second transistor M2. A NOT gate 4 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. The NOT gate 4 is configured to transmit a first-level signal VDD or a second-level signal VSS to a second node Q2 in response to the voltage at the first node Q1. A NOR gate 501 includes an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The first node Q1 is the connection node between the pre-charge sub-circuit 1, the storage sub-circuit 2, and the duty cycle adjustment sub-circuit 3. The second node Q2 is the node controlling the eighth transistor M8. The third node Q3 is the node controlling the ninth transistor M9. The fourth node Q4 is the connection node between the second terminal of the fourth transistor M4 and the first terminal of the fifth transistor M5. The input signal can be an STV signal or the output signal of the previous stage circuit.

[0076] For details, please refer to... Figure 1The control electrode of the third transistor M3 is connected to the input signal, its first electrode is connected to the first node Q1, and its second electrode is connected to the first level signal VDD. This first level signal VDD is transmitted to the first node Q1 to control the control electrode voltages of the first transistor M1 and the second transistor M2, thereby controlling the on / off state of the first transistor M1 and the second transistor M2. Simultaneously, the first level signal VDD transmitted to the first node Q1 serves as the voltage of one electrode of the storage capacitor C1, which, together with the voltage of the signal output terminal OUTPUT connected to the other electrode of the storage capacitor C1, controls the charging or discharging speed of the storage capacitor C1. The control electrodes of both the first transistor M1 and the second transistor M2 are connected to the first node Q1. The first electrode of the first transistor M1 is connected to the first clock signal CLK1, and the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2. The second electrode of the second transistor M2 is connected to the first node Q1. Responding to the voltages of the first clock signal CLK1 and the first node Q1, the first transistor M1 and the second transistor M2 are connected in series to control the duration of the transmission of the first clock signal CLK1 to the first node Q1, i.e., adjusting the duty cycle of the first clock signal CLK1. The control electrode of the fourth transistor M4 is connected to the first node Q1. The first electrode of the fourth transistor M4 is connected to the second level signal VSS, and the second electrode is connected to the fourth node Q4. The control electrode and the second electrode of the fifth transistor M5 are both connected to the first level signal VDD. The first electrode of the fifth transistor M5 is connected to the fourth node Q4. The control electrode of the sixth transistor M6 is connected to the first node Q1. The first electrode of the sixth transistor M6 is connected to the second level signal VSS, and the second electrode of the sixth transistor M6 is connected to the second node Q2. The control electrode of the seventh transistor M7 is connected to the fourth node. The first electrode of the seventh transistor M7 is connected to the second node Q2, and the second electrode of the seventh transistor M7 is connected to the first level signal VDD. The fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 together constitute NOT gate 4. The control electrode of the eighth transistor M8 is connected to the input signal, the first electrode of the eighth transistor M8 is connected to the signal output terminal OUTPUT, and the second electrode of the eighth transistor M8 is connected to the second level signal VSS. The control electrode of the ninth transistor M9 is connected to the second node Q2, the first electrode of the ninth transistor M9 is connected to the signal output terminal OUTPUT, and the second electrode of the ninth transistor M9 is connected to the second level signal VSS. The control electrode of the tenth transistor M10 is connected to the first node Q1, the first electrode of the tenth transistor M10 is connected to the second clock signal CLKH1, and the second electrode of the tenth transistor M10 is connected to the signal output terminal OUTPUT. The eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 together constitute an NOR gate 501, which transmits the second clock signal CLKH1 or the second level signal VSS to the signal output terminal OUTPUT.

[0077] The operation of the first example shift register will be described next. (Refer to...) Figure 1 and Figure 4 The steps for generating each clock cycle signal of the clock signal using the shift register in the first example include:

[0078] In the first stage, no signal is written to the input signal terminal, the first clock signal terminal, and the second clock signal terminal. At this time, the voltages of the first node Q1, the second node Q2, and the third node Q3 are all 0V.

[0079] In the second stage, the input signal written to the input signal terminal is 10V, and the first clock signal CLK1 written to the first clock signal terminal is 15V. That is, both the input signal and the first clock signal CLK1 are high-level signals. At this time, the first transistor M1 and the second transistor M2 are both turned off, the third transistor M3 is turned on, and the first level signal VDD = 10V is transmitted to the first node Q1. After passing through the NOT gate 4, the second level signal VSS = -10V is transmitted to the second node Q2. The eighth transistor M8 and the tenth transistor M10 are both turned on. At this time, the second clock signal CLKH1 written to the second clock signal terminal is -10V, and this voltage signal is output through the signal output terminal OUTPUT.

[0080] In the third stage, the input signal written to the input signal terminal is a -10V voltage, and the first clock signal CLK1 written to the first clock signal terminal is a 15V voltage. That is, the input signal is a low-level signal, and the first clock signal CLK1 is a high-level signal. At this time, the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off. The high level stored in the storage voltage C1 becomes a low level after passing through the NOT gate 4. The eighth transistor M8 and the ninth transistor M9 are both turned off, and the tenth transistor M10 is turned on. At this time, the second clock signal CLKH1 written to the second clock signal terminal is a 10V voltage, which is output through the signal output terminal OUTPUT.

[0081] In the fourth stage, the input signal written to the input signal terminal is a voltage of -10V, and the first clock signal CLK1 written to the first clock signal terminal is a voltage of -15V. That is, both the input signal and the first clock signal CLK1 are low-level signals. At this time, the first transistor M1 and the second transistor M2 are turned on, and the third transistor M3 is turned off. The low-level signal written to the first clock signal terminal is transmitted to the first node Q1 through the first transistor M1 and the second transistor M2. The low-level signal becomes a high level after passing through the NOT gate 4. The ninth transistor M9 is turned on, and the second level signal VSS = -10V is transmitted to the signal output terminal OUTPUT through the ninth transistor M9.

[0082] The above four stages constitute the specific driving process of a single-row GOA circuit. Multiple GOA circuits are cascaded, and the next-row GOA circuit continues to output a square wave signal with a certain duty cycle under the control of its clock signal CLKA and the output signal of the previous-row GOA circuit. Simulation results are as follows... Figure 6 As shown.

[0083] Second example: Figure 2 This is a schematic diagram of a shift register according to a first example of an embodiment of this disclosure; as shown Figure 2 As shown, the shift register includes a precharge sub-circuit 1, a storage sub-circuit 2, a duty cycle adjustment sub-circuit 3, a NOT gate 4, and an AND gate 502. The following simulation uses only the following parameters: first level signal VDD = 10V, second level signal VSS = -10V, third level signal VGH = 15V, fourth level signal VSSH = -7V, first clock signal CLK1 with a high level of 15V and a low level of -15V; storage capacitor C1 = 1μf; and transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, and M10 all being N-type transistors. It should be understood that in actual product use, these parameters can be adjusted according to specific requirements.

[0084] The pre-charge sub-circuit 1 includes a third transistor M3. The storage sub-circuit 2 includes C1. The duty cycle adjustment sub-circuit 3 includes a first transistor M1 and a second transistor M2. The NOT gate 4 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. The NOT gate 4 is configured to transmit a second-level signal VSS or a third-level signal VGH to the third node Q3 in response to the voltage of the input signal. The AND gate 502 includes an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The first node Q1 is the connection node of the pre-charge sub-circuit 1, the storage sub-circuit 2, and the duty cycle adjustment sub-circuit 3. The second node Q2 is the node of the control electrode of the eighth transistor M8. The third node Q3 is the node of the control electrode of the ninth transistor M9. The fourth node Q4 is the connection node of the second electrode of the fourth transistor M4 and the first electrode of the fifth transistor M5. In this embodiment, the voltages of the first node Q1 and the second node Q2 are equal. The input signal can be an STV signal or the output signal of the previous stage circuit.

[0085] For details, please refer to... Figure 2The control electrode of the third transistor M3 is connected to the input signal, its first electrode is connected to the first node Q1, and its second electrode is connected to the first level signal VDD. This first level signal VDD is transmitted to the first node Q1 to control the control electrode voltages of the first transistor M1 and the second transistor M2, thereby controlling the on / off state of the first transistor M1 and the second transistor M2. Simultaneously, the first level signal VDD transmitted to the first node Q1 serves as the voltage of one electrode of the storage capacitor C1, which, together with the voltage of the signal output terminal OUTPUT connected to the other electrode of the storage capacitor C1, controls the charging or discharging speed of the storage capacitor C1. The control electrodes of both the first transistor M1 and the second transistor M2 are connected to the first node Q1. The first electrode of the first transistor M1 is connected to the first clock signal CLK1, and the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2. The second electrode of the second transistor M2 is connected to the first node Q1. Responding to the voltages of the first clock signal CLK1 and the first node Q1, the first transistor M1 and the second transistor M2 are connected in series to control the duration of the transmission of the first clock signal CLK1 to the first node Q1, i.e., adjusting the duty cycle of the first clock signal CLK1. The control electrode and first electrode of the fourth transistor M4 are both connected to the third-level signal VGH. The second electrode of the fourth transistor M4 is connected to the fourth node Q4. The control electrode of the fifth transistor M5 is connected to the input signal. The first electrode of the fifth transistor M5 is connected to the fourth node Q4. The second electrode of the fifth transistor M5 is connected to the second-level signal VSS. The control electrode of the sixth transistor M6 is connected to the fourth node Q4. The first electrode of the sixth transistor M6 is connected to the third-level signal VGH. The second electrode of the sixth transistor M6 is connected to the third node Q3. The control electrode of the seventh transistor M7 is connected to the input signal. The first electrode of the seventh transistor M7 is connected to the third node Q3. The second electrode of the seventh transistor M7 is connected to the second-level signal VSS. The fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 together constitute NOT gate 4. The control electrode of the eighth transistor M8 is connected to the third node Q3. The first electrode of the eighth transistor M8 is connected to the first level signal VDD. The second electrode of the eighth transistor M8 is connected to the first electrode of the ninth transistor M9. The control electrode of the ninth transistor M9 is connected to the second node Q2. The second electrode of the ninth transistor M9 is connected to the signal output terminal OUTPUT. The control electrode of the tenth transistor M10 is connected to the fourth level signal VSSH. The first electrode of the tenth transistor M10 is connected to the signal output terminal OUTPUT. The second electrode of the tenth transistor M10 is connected to the second level signal VSS. The eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 together constitute an NOR gate 501, which transmits the first level signal VDD or the second level signal VSS to the signal output terminal OUTPUT.

[0086] The operation of the second example shift register will be described next. (Refer to...) Figure 2 and Figure 5The steps for generating each clock cycle signal of the clock signal using the shift register in the second example include:

[0087] In the first stage, no signal is written to the input signal terminal, the first clock signal terminal, and the second clock signal terminal. At this time, the voltages of the first node Q1, the second node Q2, and the third node Q3 are all 0V.

[0088] In the second stage, the input signal written to the input signal terminal is 10V, and the first clock signal CLK1 written to the first clock signal terminal is 15V. That is, both the input signal and the first clock signal CLK1 are high-level signals. At this time, the first transistor M1 and the second transistor M2 are both turned off, the third transistor M3 is turned on, and the first level signal VDD = 10V is transmitted to the first node Q1. The high-level input signal becomes low-level after passing through NOT gate 4. The eighth transistor M8 is turned off, the tenth transistor M10 is normally open, and the second level signal VSS = -10V is transmitted to the signal output terminal OUTPUT through the tenth transistor M10.

[0089] In the third stage, the input signal written to the input signal terminal is a voltage of -10V, and the first clock signal CLK1 written to the first clock signal terminal is a voltage of 15V. That is, the input signal is a low-level signal and the first clock signal CLK1 is a high-level signal. At this time, the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off. The low level of the input signal becomes a high level after passing through the NOT gate 4. The eighth transistor M8 is turned on, and the high voltage stored in the storage voltage C1 turns on the ninth transistor M9. The first level signal VDD = 10V is transmitted to the signal output terminal OUTPUT through the eighth transistor M8 and the ninth transistor M9.

[0090] In the fourth stage, the input signal written to the input signal terminal is -10V, and the first clock signal CLK1 written to the first clock signal terminal is -15V. That is, both the input signal and the first clock signal CLK1 are low-level signals. At this time, the first transistor M1 and the second transistor M2 are turned on, the third transistor M3 is turned off, the low level of the input signal becomes high level after passing through NOT gate 4, the eighth transistor M8 is turned on, the low-level signal written to the first clock signal terminal is transmitted to the first node Q1 through the first transistor M1 and the second transistor M2, the ninth transistor M9 is turned off, the tenth transistor M10 is normally open, and the second level signal VSS = -10V is transmitted to the signal output terminal OUTPUT for output through the tenth transistor M10.

[0091] The above four stages constitute the specific driving process of a row of GOA circuits. Multiple GOA circuits are cascaded, and the GOA circuit in the next row continues to output a square wave signal with a certain duty cycle under the control of its clock signal CLKA and the output signal of the GOA circuit in the previous row.

[0092] Third example: Figure 3 This is a schematic diagram of a shift register according to a third example of an embodiment of this disclosure; as shown Figure 3 As shown, the shift register includes a precharge sub-circuit 1, a storage sub-circuit 2, a duty cycle adjustment sub-circuit 3, a NOT gate 4, and a NOR gate 503. The following simulation uses only the following example: a first level signal VDD = 10V, a second level signal VSS = -10V, a high level of 15V and a low level of -15V for the first clock signal CLK1; a storage capacitor C1 = 1μf; and N-type transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, and M10. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0093] The circuit includes: a pre-charge sub-circuit 1, a third transistor M3; a storage sub-circuit 2, a C1; a duty cycle adjustment sub-circuit 3, a first transistor M1 and a second transistor M2; a NOT gate 4, comprising a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7, configured to transmit a first-level signal VDD or a second-level signal VSS to a second node Q2 in response to the voltage at the first node Q1; and an AND gate 502, comprising an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The first node Q1 connects the pre-charge sub-circuit 1, the storage sub-circuit 2, and the duty cycle adjustment sub-circuit 3. The second node Q2 is the control terminal of the eighth transistor M8, the third node Q3 is the control terminal of the ninth transistor M9, and the fourth node Q4 connects the second terminal of the fourth transistor M4 and the first terminal of the fifth transistor M5. The input signal can be an STV signal or the output signal of the previous stage circuit.

[0094] For details, please refer to... Figure 3The control electrode of the third transistor M3 is connected to the input signal, its first electrode is connected to the first node Q1, and its second electrode is connected to the first level signal VDD. This first level signal VDD is transmitted to the first node Q1 to control the control electrode voltages of the first transistor M1 and the second transistor M2, thereby controlling the on / off state of the first transistor M1 and the second transistor M2. Simultaneously, the first level signal VDD transmitted to the first node Q1 serves as the voltage of one electrode of the storage capacitor C1, working together with the second level signal VSS connected to the other electrode of the storage capacitor C1 to control the charging or discharging speed of the storage capacitor C1. The control electrodes of both the first transistor M1 and the second transistor M2 are connected to the first node Q1. The first electrode of the first transistor M1 is connected to the first clock signal CLK1, and the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2. The second electrode of the second transistor M2 is connected to the first node Q1. Responding to the voltage of the first clock signal CLK1 and the first node Q1, the first transistor M1 and the second transistor M2 are connected in series to control the duration of the transmission of the first clock signal CLK1 to the first node Q1, i.e., adjusting the duty cycle of the first clock signal CLK1. The control electrode of the fourth transistor M4 is connected to the first node Q1. The first electrode of the fourth transistor M4 is connected to the second level signal VSS, and the second electrode is connected to the fourth node Q4. The control electrode and the second electrode of the fifth transistor M5 are both connected to the first level signal VDD. The first electrode of the fifth transistor M5 is connected to the fourth node Q4. The control electrode of the sixth transistor M6 is connected to the first node Q1. The first electrode of the sixth transistor M6 is connected to the second level signal VSS, and the second electrode of the sixth transistor M6 is connected to the second node Q2. The control electrode of the seventh transistor M7 is connected to the fourth node. The first electrode of the seventh transistor M7 is connected to the second node Q2, and the second electrode of the seventh transistor M7 is connected to the first level signal VDD. The fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 together constitute NOT gate 4. The control electrode of the eighth transistor M8 is connected to the input signal, the first electrode of the eighth transistor M8 is connected to the second-level signal VSS, and the second electrode of the eighth transistor M8 is connected to the signal output terminal OUTPUT. The control electrode of the ninth transistor M9 is connected to the second node Q2, the first electrode of the ninth transistor M9 is connected to the second-level signal VSS, and the second electrode of the ninth transistor M9 is connected to the signal output terminal OUTPUT. The control electrode and the second electrode of the tenth transistor M10 are both connected to the first-level signal VDD, and the first electrode of the tenth transistor M10 is connected to the signal output terminal OUTPUT. The eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 together form an AND gate 503, which transmits the first-level signal VDD or the second-level signal VSS to the signal output terminal OUTPUT.

[0095] The operation of the third example shift register will be described next. (Refer to...) Figure 3 and Figure 5The steps for generating each clock cycle signal of the clock signal using the shift register in the third example include:

[0096] In the first stage, no signal is written to the input signal terminal, the first clock signal terminal, and the second clock signal terminal. At this time, the voltages of the first node Q1, the second node Q2, and the third node Q3 are all 0V.

[0097] In the second stage, the input signal written to the input signal terminal is 10V, and the first clock signal CLK1 written to the first clock signal terminal is 15V. That is, both the input signal and the first clock signal CLK1 are high-level signals. At this time, the first transistor M1 and the second transistor M2 are both turned off, the third transistor M3 is turned on, and the first level signal VDD = 10V is transmitted to the first node Q1. After passing through the NOT gate 4, the second level signal VSS = -10V is transmitted to the second node Q2. The eighth transistor M8 is turned on, the ninth transistor M9 is turned off, and the second level signal VSS = -10V is transmitted to the signal output terminal OUTPUT through the eighth transistor M8.

[0098] In the third stage, the input signal written to the input signal terminal is a -10V voltage, and the first clock signal CLK1 written to the first clock signal terminal is a 15V voltage. That is, the input signal is a low-level signal, and the first clock signal CLK1 is a high-level signal. At this time, the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off. The high level stored in the storage voltage C1 becomes a low level after passing through the NOT gate 4. The eighth transistor M8 and the ninth transistor M9 are both turned off, and the tenth transistor M10 is turned on. The first level signal VDD = 10V is transmitted to the signal output terminal OUTPUT for output.

[0099] In the fourth stage, the input signal written to the input signal terminal is a voltage of -10V, and the first clock signal CLK1 written to the first clock signal terminal is a voltage of -15V. That is, both the input signal and the first clock signal CLK1 are low-level signals. At this time, the first transistor M1 and the second transistor M2 are turned on, and the third transistor M3 is turned off. The low-level signal written to the first clock signal terminal is transmitted to the first node Q1 through the first transistor M1 and the second transistor M2. The low-level signal becomes a high level after passing through the NOT gate 4. The ninth transistor M9 is turned on, and the second level signal VSS = -10V is transmitted to the signal output terminal OUTPUT through the ninth transistor M9.

[0100] The above four stages constitute the specific driving process of a row of GOA circuits. Multiple GOA circuits are cascaded, and the GOA circuit in the next row continues to output a square wave signal with a certain duty cycle under the control of its clock signal CLKA and the output signal of the GOA circuit in the previous row.

[0101] Fourth example: Figure 7This is a schematic diagram of a shift register according to a first example of an embodiment of this disclosure; as shown Figure 7 As shown, the shift register includes a precharge sub-circuit 1, a storage sub-circuit 2, a duty cycle adjustment sub-circuit 3, a NOT gate 4, and a NAND gate 504. The difference between the fourth example and the first example is that the switching characteristics of all transistors are reversed. The eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 together constitute NAND gate 4 as the output sub-circuit 5. The following simulation uses the following parameters as an example: first level signal VSS = -10V, second level signal VDD = 10V, first clock signal CLK1 high level 15V, low level -15V, second clock signal CLKH1 high level 10V, low level -10V; storage capacitor C1 = 1μf; and first transistor M1, second transistor M2, third transistor M3, fourth transistor M4, fifth transistor M5, sixth transistor M6, seventh transistor M7, eighth transistor M8, ninth transistor M9, and tenth transistor M10 are all P-type transistors. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0102] The circuit includes a pre-charge sub-circuit 1, a third transistor M3, a storage sub-circuit 2, a C1, a duty cycle adjustment sub-circuit 3, a first transistor M1, and a second transistor M2. A NOT gate 4 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. The NOT gate 4 is configured to transmit a first-level signal VSS or a second-level signal VDD to a second node Q2 in response to the voltage at the first node Q1. A NAND gate 501 includes an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The first node Q1 is the connection node between the pre-charge sub-circuit 1, the storage sub-circuit 2, and the duty cycle adjustment sub-circuit 3. The second node Q2 is the node controlling the eighth transistor M8. The third node Q3 is the node controlling the ninth transistor M9. The fourth node Q4 is the connection node between the second terminal of the fourth transistor M4 and the first terminal of the fifth transistor M5. The input signal can be an STV signal or the output signal of the previous stage circuit.

[0103] For details, please refer to... Figure 7The control electrode of the third transistor M3 is connected to the input signal, its first electrode is connected to the first node Q1, and its second electrode is connected to the first level signal VSS. This first level signal VSS is transmitted to the first node Q1 to control the control electrode voltages of the first transistor M1 and the second transistor M2, thereby controlling the on / off state of the first transistor M1 and the second transistor M2. Simultaneously, the first level signal VSS transmitted to the first node Q1 serves as the voltage of one electrode of the storage capacitor C1, which, together with the voltage of the signal output terminal OUTPUT connected to the other electrode of the storage capacitor C1, controls the charging or discharging speed of the storage capacitor C1. The control electrodes of both the first transistor M1 and the second transistor M2 are connected to the first node Q1. The first electrode of the first transistor M1 is connected to the first clock signal CLK1, and the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2. The second electrode of the second transistor M2 is connected to the first node Q1. Responding to the voltages of the first clock signal CLK1 and the first node Q1, the first transistor M1 and the second transistor M2 are connected in series to control the duration of the transmission of the first clock signal CLK1 to the first node Q1, i.e., adjusting the duty cycle of the first clock signal CLK1. The control electrode of the fourth transistor M4 is connected to the first node Q1. The first electrode of the fourth transistor M4 is connected to the second-level signal VDD, and the second electrode is connected to the fourth node Q4. The control electrode and the second electrode of the fifth transistor M5 are both connected to the first-level signal VSS. The first electrode of the fifth transistor M5 is connected to the fourth node Q4. The control electrode of the sixth transistor M6 is connected to the first node Q1. The first electrode of the sixth transistor M6 is connected to the second-level signal VDD, and the second electrode of the sixth transistor M6 is connected to the second node Q2. The control electrode of the seventh transistor M7 is connected to the fourth node. The first electrode of the seventh transistor M7 is connected to the second node Q2, and the second electrode of the seventh transistor M7 is connected to the first-level signal VSS. The fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 together constitute NOT gate 4. The control electrode of the eighth transistor M8 is connected to the input signal, the first electrode of the eighth transistor M8 is connected to the signal output terminal OUTPUT, and the second electrode of the eighth transistor M8 is connected to the second level signal VDD. The control electrode of the ninth transistor M9 is connected to the second node Q2, the first electrode of the ninth transistor M9 is connected to the signal output terminal OUTPUT, and the second electrode of the ninth transistor M9 is connected to the second level signal VDD. The control electrode of the tenth transistor M10 is connected to the first node Q1, the first electrode of the tenth transistor M10 is connected to the second clock signal CLKH1, and the second electrode of the tenth transistor M10 is connected to the signal output terminal OUTPUT. The eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 together constitute an NOR gate 501, which transmits the second clock signal CLKH1 or the second level signal VDD to the signal output terminal OUTPUT.

[0104] The operation of the fourth example shift register will be described next. (Refer to...) Figure 7 and Figure 10 The steps for generating each clock cycle signal of the clock signal using the shift register in the fourth example include:

[0105] In the first stage, no signal is written to the input signal terminal, the first clock signal terminal, and the second clock signal terminal. At this time, the voltages of the first node Q1, the second node Q2, and the third node Q3 are all 0V.

[0106] In the second stage, the input signal written to the input signal terminal is a voltage of -10V, and the first clock signal CLK1 written to the first clock signal terminal is a voltage of -15V. That is, both the input signal and the first clock signal CLK1 are low-level signals. At this time, the first transistor M1 and the second transistor M2 are both turned off, the third transistor M3 is turned on, and the first level signal VSS = -10V is transmitted to the first node Q1. After passing through the NOT gate 4, the second level signal VDD = 10V is transmitted to the second node Q2. The eighth transistor M8 and the tenth transistor M10 are both turned on. At this time, the second clock signal CLKH1 written to the second clock signal terminal is a voltage of 10V, and this voltage signal is output through the signal output terminal OUTPUT.

[0107] In the third stage, the input signal written to the input signal terminal is a 10V voltage, and the first clock signal CLK1 written to the first clock signal terminal is a -15V voltage. That is, the input signal is a high-level signal and the first clock signal CLK1 is a low-level signal. At this time, the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off. The low level stored in the storage voltage C1 becomes a high level after passing through the NOT gate 4. The eighth transistor M8 and the ninth transistor M9 are both turned off, and the tenth transistor M10 is turned on. At this time, the second clock signal CLKH1 written to the second clock signal terminal is a -10V voltage, which is output through the signal output terminal OUTPUT.

[0108] In the fourth stage, the input signal written to the input signal terminal is 10V, and the first clock signal CLK1 written to the first clock signal terminal is 15V. That is, both the input signal and the first clock signal CLK1 are high-level signals. At this time, the first transistor M1 and the second transistor M2 are turned on, and the third transistor M3 is turned off. The high-level signal written to the first clock signal terminal is transmitted to the first node Q1 through the first transistor M1 and the second transistor M2. The high-level signal becomes low-level after passing through NOT gate 4. The ninth transistor M9 is turned on, and the second level signal VDD = 10V is transmitted to the signal output terminal OUTPUT through the ninth transistor M9.

[0109] The above four stages constitute the specific driving process of a single-row GOA circuit. Multiple GOA circuits are cascaded, and the next-row GOA circuit continues to output a square wave signal with a certain duty cycle under the control of its clock signal CLKA and the output signal of the previous-row GOA circuit. Simulation results are as follows... Figure 12 As shown.

[0110] Fifth example: Figure 8 This is a schematic diagram of a shift register according to a first example of an embodiment of this disclosure; as shown Figure 8 As shown, the shift register includes a precharge sub-circuit 1, a storage sub-circuit 2, a duty cycle adjustment sub-circuit 3, a NOT gate 4, and an OR gate 505. The following simulation uses only the following example: the first level signal VSS = -10V, the second level signal VDD = 10V, the fourth level signal LVSS = -15V, the fourth level VDDL = 7V, the high level of the first clock signal CLK1 is 15V, and the low level is -15V; the storage capacitor C1 = 1μf; and the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are all P-type transistors. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0111] The pre-charge sub-circuit 1 includes a third transistor M3. The storage sub-circuit 2 includes C1. The duty cycle adjustment sub-circuit 3 includes a first transistor M1 and a second transistor M2. The NOT gate 4 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. The NOT gate 4 is configured to transmit a second-level signal VDD or a third-level signal LVSS to the third node Q3 in response to the voltage of the input signal. The OR gate 505 includes an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The first node Q1 is the connection node of the pre-charge sub-circuit 1, the storage sub-circuit 2, and the duty cycle adjustment sub-circuit 3. The second node Q2 is the node of the control electrode of the eighth transistor M8. The third node Q3 is the node of the control electrode of the ninth transistor M9. The fourth node Q4 is the connection node of the second electrode of the fourth transistor M4 and the first electrode of the fifth transistor M5. In this embodiment, the voltages of the first node Q1 and the second node Q2 are equal. The input signal can be an STV signal or the output signal of the previous stage circuit.

[0112] For details, please refer to... Figure 8The control electrode of the third transistor M3 is connected to the input signal, its first electrode is connected to the first node Q1, and its second electrode is connected to the first level signal VSS. This first level signal VSS is transmitted to the first node Q1 to control the control electrode voltages of the first transistor M1 and the second transistor M2, thereby controlling the on / off state of the first transistor M1 and the second transistor M2. Simultaneously, the first level signal VSS transmitted to the first node Q1 serves as the voltage of one electrode of the storage capacitor C1, which, together with the voltage of the signal output terminal OUTPUT connected to the other electrode of the storage capacitor C1, controls the charging or discharging speed of the storage capacitor C1. The control electrodes of both the first transistor M1 and the second transistor M2 are connected to the first node Q1. The first electrode of the first transistor M1 is connected to the first clock signal CLK1, and the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2. The second electrode of the second transistor M2 is connected to the first node Q1. Responding to the voltages of the first clock signal CLK1 and the first node Q1, the first transistor M1 and the second transistor M2 are connected in series to control the duration of the transmission of the first clock signal CLK1 to the first node Q1, i.e., adjusting the duty cycle of the first clock signal CLK1. The control electrode and first electrode of the fourth transistor M4 are both connected to the third-level signal LVSS. The second electrode of the fourth transistor M4 is connected to the fourth node Q4. The control electrode of the fifth transistor M5 is connected to the input signal. The first electrode of the fifth transistor M5 is connected to the fourth node Q4. The second electrode of the fifth transistor M5 is connected to the second-level signal VDD. The control electrode of the sixth transistor M6 is connected to the fourth node Q4. The first electrode of the sixth transistor M6 is connected to the third-level signal LVSS. The second electrode of the sixth transistor M6 is connected to the third node Q3. The control electrode of the seventh transistor M7 is connected to the input signal. The first electrode of the seventh transistor M7 is connected to the third node Q3. The second electrode of the seventh transistor M7 is connected to the second-level signal VDD. The fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 together constitute NOT gate 4. The control electrode of the eighth transistor M8 is connected to the third node Q3. The first electrode of the eighth transistor M8 is connected to the first level signal VSS. The second electrode of the eighth transistor M8 is connected to the first electrode of the ninth transistor M9. The control electrode of the ninth transistor M9 is connected to the second node Q2. The second electrode of the ninth transistor M9 is connected to the signal output terminal OUTPUT. The control electrode of the tenth transistor M10 is connected to the fourth level signal VDDL. The first electrode of the tenth transistor M10 is connected to the signal output terminal OUTPUT. The second electrode of the tenth transistor M10 is connected to the second level signal VDD. The eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 together constitute an NOR gate 501, which transmits the first level signal VSS or the second level signal VDD to the signal output terminal OUTPUT.

[0113] The operation of the fifth example shift register will be described next. (Refer to...) Figure 8 and Figure 11The steps for generating each clock cycle signal of the clock signal using the shift register in the fifth example include:

[0114] In the first stage, no signal is written to the input signal terminal, the first clock signal terminal, and the second clock signal terminal. At this time, the voltages of the first node Q1, the second node Q2, and the third node Q3 are all 0V.

[0115] In the second stage, the input signal written to the input signal terminal is a voltage of -10V, and the first clock signal CLK1 written to the first clock signal terminal is a voltage of -15V. That is, both the input signal and the first clock signal CLK1 are low-level signals. At this time, the first transistor M1 and the second transistor M2 are both turned off, the third transistor M3 is turned on, and the first level signal VSS = -10V is transmitted to the first node Q1. The low-level input signal becomes a high level after passing through the NOT gate 4. The eighth transistor M8 is turned off, the tenth transistor M10 is normally open, and the second level signal VDD = 10V is transmitted to the signal output terminal OUTPUT through the tenth transistor M10.

[0116] In the third stage, the input signal written to the input signal terminal is a 10V voltage, and the first clock signal CLK1 written to the first clock signal terminal is a -15V voltage. That is, the input signal is a high-level signal and the first clock signal CLK1 is a low-level signal. At this time, the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off. The high-level input signal becomes a low level after passing through the NOT gate 4. The eighth transistor M8 is turned on, and the low voltage stored in the storage voltage C1 turns on the ninth transistor M9. The first level signal VSS = -10V is transmitted to the signal output terminal OUTPUT through the eighth transistor M8 and the ninth transistor M9.

[0117] In the fourth stage, the input signal written to the input signal terminal is 10V, and the first clock signal CLK1 written to the first clock signal terminal is 15V. That is, both the input signal and the first clock signal CLK1 are high-level signals. At this time, the first transistor M1 and the second transistor M2 are turned on, the third transistor M3 is turned off, the high-level input signal becomes low-level after passing through NOT gate 4, the eighth transistor M8 is turned on, and the high-level signal written to the first clock signal terminal is transmitted to the first node Q1 through the first transistor M1 and the second transistor M2. The ninth transistor M9 is turned off, the tenth transistor M10 is normally open, and the second level signal VDD = 10V is transmitted to the signal output terminal OUTPUT for output through the tenth transistor M10.

[0118] The above four stages constitute the specific driving process of a row of GOA circuits. Multiple GOA circuits are cascaded, and the GOA circuit in the next row continues to output a square wave signal with a certain duty cycle under the control of its clock signal CLKA and the output signal of the GOA circuit in the previous row.

[0119] Sixth example: Figure 9 This is a schematic diagram of a shift register according to a third example of an embodiment of this disclosure; as shown Figure 9 As shown, the shift register includes a precharge sub-circuit 1, a storage sub-circuit 2, a duty cycle adjustment sub-circuit 3, a NOT gate 4, and an OR gate 506. The following simulation uses only the following example: a first level signal VSS = -10V, a second level signal VDD = 10V, a third level signal VGH = 15V, a high level of the first clock signal CLK1 of 15V, and a low level of -15V; a storage capacitor C1 = 1μf; and all transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, and M10 being P-type transistors. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0120] The circuit includes: a pre-charge sub-circuit 1, a third transistor M3; a storage sub-circuit 2, a storage capacitor C1; a duty cycle adjustment sub-circuit 3, a first transistor M1 and a second transistor M2; a NOT gate 4, comprising a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7, configured to transmit a first-level signal VSS or a second-level signal VDD to a second node Q2 in response to the voltage at the first node Q1; and an OR gate 506, comprising an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The first node Q1 connects the pre-charge sub-circuit 1, the storage sub-circuit 2, and the duty cycle adjustment sub-circuit 3. The second node Q2 is the control terminal of the eighth transistor M8, the third node Q3 is the control terminal of the ninth transistor M9, and the fourth node Q4 connects the second terminal of the fourth transistor M4 and the first terminal of the fifth transistor M5. The input signal can be an STV signal or the output signal of the previous stage circuit.

[0121] For details, please refer to... Figure 9The control electrode of the third transistor M3 is connected to the input signal, its first electrode is connected to the first node Q1, and its second electrode is connected to the first level signal VSS. This first level signal VSS is transmitted to the first node Q1 to control the control electrode voltages of the first transistor M1 and the second transistor M2, thereby controlling the on / off state of the first transistor M1 and the second transistor M2. Simultaneously, the first level signal VSS transmitted to the first node Q1 serves as the voltage of one electrode of the storage capacitor C1, working together with the second level signal VDD connected to the other electrode of the storage capacitor C1 to control the charging or discharging speed of the storage capacitor C1. The control electrodes of both the first transistor M1 and the second transistor M2 are connected to the first node Q1. The first electrode of the first transistor M1 is connected to the first clock signal CLK1, and the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2. The second electrode of the second transistor M2 is connected to the first node Q1. Responding to the voltage of the first clock signal CLK1 and the first node Q1, the first transistor M1 and the second transistor M2 are connected in series to control the duration of the transmission of the first clock signal CLK1 to the first node Q1, i.e., adjusting the duty cycle of the first clock signal CLK1. The control electrode of the fourth transistor M4 is connected to the first node Q1. The first electrode of the fourth transistor M4 is connected to the second-level signal VDD, and the second electrode is connected to the fourth node Q4. The control electrode and the second electrode of the fifth transistor M5 are both connected to the first-level signal VSS. The first electrode of the fifth transistor M5 is connected to the fourth node Q4. The control electrode of the sixth transistor M6 is connected to the first node Q1. The first electrode of the sixth transistor M6 is connected to the third-level signal VGH, and the second electrode of the sixth transistor M6 is connected to the second node Q2. The control electrode of the seventh transistor M7 is connected to the fourth node. The first electrode of the seventh transistor M7 is connected to the second node Q2, and the second electrode of the seventh transistor M7 is connected to the first-level signal VSS. The fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 together constitute NOT gate 4. The control electrode of the eighth transistor M8 is connected to the input signal, the first electrode of the eighth transistor M8 is connected to the second-level signal VDD, and the second electrode of the eighth transistor M8 is connected to the signal output terminal OUTPUT. The control electrode of the ninth transistor M9 is connected to the second node Q2, the first electrode of the ninth transistor M9 is connected to the second-level signal VDD, and the second electrode of the ninth transistor M9 is connected to the signal output terminal OUTPUT. The control electrode and the second electrode of the tenth transistor M10 are both connected to the first-level signal VSS, and the first electrode of the tenth transistor M10 is connected to the signal output terminal OUTPUT. The eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 together form an AND gate 503, which transmits the first-level signal VSS or the second-level signal VDD to the signal output terminal OUTPUT.

[0122] The operation of the sixth example shift register will be described next. (Refer to...) Figure 9 and Figure 11The steps for generating each clock cycle signal of the clock signal using the shift register in the sixth example include:

[0123] In the first stage, no signal is written to the input signal terminal, the first clock signal terminal, and the second clock signal terminal. At this time, the voltages of the first node Q1, the second node Q2, and the third node Q3 are all 0V.

[0124] In the second stage, the input signal written to the input signal terminal is a voltage of -10V, and the first clock signal CLK1 written to the first clock signal terminal is a voltage of -15V. That is, both the input signal and the first clock signal CLK1 are low-level signals. At this time, the first transistor M1 and the second transistor M2 are both turned off, the third transistor M3 is turned on, and the first level signal VSS = -10V is transmitted to the first node Q1. After passing through the NOT gate 4, the second level signal VDD = 10V is transmitted to the second node Q2. The eighth transistor M8 is turned on, the ninth transistor M9 is turned off, and the second level signal VDD = 10V is transmitted to the signal output terminal OUTPUT through the eighth transistor M8.

[0125] In the third stage, the input signal written to the input signal terminal is a 10V voltage, and the first clock signal CLK1 written to the first clock signal terminal is a -15V voltage. That is, the input signal is a high-level signal and the first clock signal CLK1 is a low-level signal. At this time, the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off. The low level stored in the storage voltage C1 becomes a high level after passing through the NOT gate 4. The eighth transistor M8 and the ninth transistor M9 are both turned off, and the tenth transistor M10 is turned on. The first level signal VSS = -10V is transmitted to the signal output terminal OUTPUT for output.

[0126] In the fourth stage, the input signal written to the input signal terminal is 10V, and the first clock signal CLK1 written to the first clock signal terminal is 15V. That is, both the input signal and the first clock signal CLK1 are high-level signals. At this time, the first transistor M1 and the second transistor M2 are turned on, and the third transistor M3 is turned off. The high-level signal written to the first clock signal terminal is transmitted to the first node Q1 through the first transistor M1 and the second transistor M2. The high-level signal becomes low-level after passing through NOT gate 4. The ninth transistor M9 is turned on, and the second level signal VDD = 10V is transmitted to the signal output terminal OUTPUT through the ninth transistor M9.

[0127] The above four stages constitute the specific driving process of a row of GOA circuits. Multiple GOA circuits are cascaded, and the GOA circuit in the next row continues to output a square wave signal with a certain duty cycle under the control of its clock signal CLKA and the output signal of the GOA circuit in the previous row.

[0128] Secondly, this disclosure provides a pixel driving circuit, which includes multiple cascaded shift registers as described in any of the above embodiments. The signal input terminal of the shift register in this stage is connected to the signal output terminal of the shift register in the previous stage. Its implementation principle is similar to the working principle of the shift registers described above, and will not be repeated here.

[0129] Thirdly, this disclosure provides a display device that includes the pixel driving circuit provided in any of the above embodiments. The display device can be any product or component with display functionality, such as a television, mobile phone, monitor, laptop computer, or navigator. Its implementation principle is similar to that of the shift register and gate driving circuit described above, and will not be repeated here.

[0130] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A shift register, comprising: Precharge sub-circuit, storage sub-circuit, duty cycle adjustment sub-circuit, NOT gate, output sub-circuit; The precharge sub-circuit is configured to transmit a first-level signal to the first node in response to an input signal; The first node is the connection node of the pre-charge sub-circuit, the storage sub-circuit, and the duty cycle adjustment sub-circuit; The duty cycle adjustment sub-circuit is configured to transmit a first clock signal to the first node in response to the first node voltage; The storage sub-circuit is configured to control the operating duration of the duty cycle adjustment sub-circuit based on the signal output voltage and the first node voltage. The NOT gate is configured to transmit either a first-level signal or a second-level signal to a second node in response to the first node voltage; the output sub-circuit is configured to output a second clock signal or a second-level signal to a signal output terminal in response to the first node voltage and the input signal voltage; or, the output sub-circuit is configured to output a second-level signal to a signal output terminal in response to the second node voltage and the third node voltage; the second node is the connection node between the NOT gate and the output sub-circuit; the third node is the connection node between the signal input terminal and the output sub-circuit. or, The storage sub-circuit is configured to control the operating duration of the duty cycle adjustment sub-circuit based on the signal output voltage and the first node voltage. The NOT gate is configured to transmit a second-level signal or a fifth-level signal to a third node in response to an input signal; the output sub-circuit is configured to output a first-level signal or a second-level signal to a signal output terminal in response to the voltage of the second node and the voltage of the third node; the second node is the connection node between the duty cycle adjustment sub-circuit and the output sub-circuit. The third node is the connection node between the NOT gate and the output sub-circuit; or, The storage sub-circuit is configured to control the operating duration of the duty cycle adjustment sub-circuit based on the second level signal and the first node voltage; The NOT gate is configured to transmit either the first level signal or the second level signal to the second node in response to the first node voltage; the output sub-circuit is configured to output either the first level signal or the second level signal to the signal output terminal in response to the second node voltage and the third node voltage; the second node is the connection node between the NOT gate and the output sub-circuit; the third node is the connection node between the signal input terminal and the output sub-circuit.

2. The shift register according to claim 1, wherein, The pre-charge sub-circuit includes: a third transistor; The control electrode of the third transistor is connected to the signal input terminal, the first electrode is connected to the first node, and the second electrode is connected to the first level signal terminal.

3. The shift register according to claim 2, wherein, The duty cycle adjustment sub-circuit includes: a first transistor and a second transistor; The control electrode of the first transistor is connected to the first node, the first electrode is connected to the first clock signal terminal, and the second electrode is connected to the first electrode of the second transistor. The control electrode of the second transistor is connected to the first node, the first electrode is connected to the second electrode of the first transistor, and the second electrode is connected to the first node.

4. The shift register according to claim 1, wherein, The storage sub-circuit includes: a first storage capacitor.

5. The shift register according to claim 4, wherein, When the storage sub-circuit is configured to control the operating duration of the duty cycle adjustment sub-circuit based on the signal output voltage and the first node voltage, one pole of the first storage capacitor is connected to the signal output terminal, and the other pole is connected to the first node.

6. The shift register according to claim 4, wherein, When the storage sub-circuit is configured to control the operating duration of the duty cycle adjustment sub-circuit according to the second level signal and the first node voltage, one terminal of the first storage capacitor is connected to the second level signal terminal, and the other terminal is connected to the first node.

7. The shift register according to claim 1, wherein, The NOT gate includes: a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor.

8. The shift register according to claim 7, wherein, When the NOT gate is configured to respond to the first node voltage The control electrode of the fourth transistor is connected to the first node, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the fourth node; the fourth node is the connection node between the second electrode of the fourth transistor and the first electrode of the fifth transistor. The control electrode of the fifth transistor is connected to the first level signal terminal, the first electrode is connected to the fourth node, and the second electrode is connected to the first level signal terminal. The control electrode of the sixth transistor is connected to the first node, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the second node. The control electrode of the seventh transistor is connected to the fourth node, the first electrode is connected to the second node, and the second electrode is connected to the first level signal terminal.

9. The shift register according to claim 7, wherein, When the NOT gate is configured to respond to an input signal The control electrode of the fourth transistor is connected to the third-level signal terminal, the first electrode is connected to the third-level signal terminal, and the second electrode is connected to the fourth node. The control electrode of the fifth transistor is connected to the signal input terminal, the first electrode is connected to the fourth node, and the second electrode is connected to the second level signal terminal. The control electrode of the sixth transistor is connected to the fourth node, the first electrode is connected to the third level signal terminal, and the second electrode is connected to the third node. The control electrode of the seventh transistor is connected to the signal input terminal, the first electrode is connected to the third node, and the second electrode is connected to the second level signal terminal.

10. The shift register according to claim 1, wherein, The output sub-circuit includes: an eighth transistor, a ninth transistor, and a tenth transistor.

11. The shift register according to claim 10, wherein, When the output sub-circuit is configured to output a second clock signal or a second level signal to the signal output terminal in response to the first node voltage and the input signal voltage, or when the output sub-circuit is configured to output a second level signal to the signal output terminal in response to the second node voltage and the third node voltage, The control electrode of the eighth transistor is connected to the signal input terminal, the first electrode is connected to the signal output terminal, and the second electrode is connected to the second level signal terminal; The control electrode of the ninth transistor is connected to the second node, the first electrode is connected to the signal output terminal, and the second electrode is connected to the second level signal terminal. The control electrode of the tenth transistor is connected to the first node, the first electrode is connected to the second clock signal terminal, and the second electrode is connected to the signal output terminal.

12. The shift register according to claim 10, wherein, When the output sub-circuit is configured to output either the first-level signal or the second-level signal to the signal output terminal in response to the second node voltage and the third node voltage, The control electrode of the eighth transistor is connected to the third node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first electrode of the ninth transistor; The control electrode of the ninth transistor is connected to the second node, the first electrode is connected to the second electrode of the eighth transistor, and the second electrode is connected to the signal output terminal; The control electrode of the tenth transistor is connected to the fourth level signal terminal, the first electrode is connected to the signal output terminal, and the second electrode is connected to the second level signal terminal.

13. The shift register according to claim 10, wherein, When the output sub-circuit is configured to output either the first-level signal or the second-level signal to the signal output terminal in response to the second node voltage and the third node voltage, The control electrode of the eighth transistor is connected to the signal input terminal, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the signal output terminal; The control electrode of the ninth transistor is connected to the second node, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the signal output terminal. The control electrode of the tenth transistor is connected to the first level signal terminal, the first electrode is connected to the signal output terminal, and the second electrode is connected to the first level signal terminal.

14. A pixel driving circuit, wherein, The pixel driving circuit includes: a plurality of cascaded shift registers as described in any one of claims 1-13; The signal input terminal of the shift register described in this stage is connected to the signal output terminal of the shift register described in the previous stage.

15. A display device, wherein, The display device includes the pixel driving circuit as described in claim 14.

Images