Array substrate, display panel and display device

Abstract

The application relates to an array substrate, a display panel and a display device. The array substrate comprises a first area and a second area, the second area is provided with a driving chip, and the array substrate comprises a substrate and an array layer. The array layer is located on one side of the substrate, the array layer comprises a pixel driving circuit and a multiplexer, at least part of the pixel driving circuit is arranged in the same layer as the multiplexer, the multiplexer is electrically connected with the driving chip, and at least part of the multiplexer is located in the first area. The application can reduce the space for arranging the multiplexer in the second area, thereby reducing the overall area of the second area, reducing the lower frame size of the display panel, and realizing the narrow frame of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display panels and other flat panel display panels that utilize light-emitting diode (LED) devices are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, digital cameras, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide range of applications, becoming the mainstream in display devices. Summary of the Invention

[0003] This application provides an array substrate, a display panel, and a display device, which can reduce the area of ​​the non-display area of ​​the display panel and facilitate the realization of a narrow bezel for the display panel.

[0004] An embodiment of the first aspect of this application provides an array substrate, including a first region and a second region, wherein a driver chip is disposed in the second region. The array substrate includes: a substrate; an array layer located on one side of the substrate, the array layer including a pixel driving circuit and a multiplexer, at least a portion of the pixel driving circuit being disposed on the same layer as the multiplexer, the multiplexer being electrically connected to the driver chip, and at least a portion of the multiplexer being located in the first region.

[0005] According to an embodiment of the first aspect of this application, the first region includes a first functional region and a second functional region arranged sequentially, with at least a portion of the pixel driving circuit located in the first functional region and at least a portion of the multiplexer located in the second functional region.

[0006] According to the first aspect of this application, the pixel driving circuits are all distributed in the first functional area, and the multiplexer is located in the second functional area.

[0007] According to an embodiment of the first aspect of this application, the pixel driving circuit includes a first pixel driving unit and a second pixel driving unit, the first pixel driving unit is located in a first functional area, the second pixel driving unit is located at least in a second functional area, and at least a portion of the multiplexer is located in the second functional area.

[0008] According to an embodiment of the first aspect of this application, a plurality of first pixel driving units are distributed in a plurality of first driving rows along a first direction, and a plurality of second pixel driving units are distributed in a plurality of second driving rows along the first direction. The spacing between two adjacent first driving rows is greater than the spacing between two adjacent second driving rows, and the first direction intersects with the thickness direction of the array substrate.

[0009] According to an embodiment of the first aspect of this application, the size of the first pixel driving unit is larger than the size of the second pixel driving unit, and the first direction intersects the thickness direction of the array substrate.

[0010] According to an embodiment of the first aspect of this application, a first functional area along a first direction includes a first sub-area and a second sub-area, the second functional area includes a third sub-area and a fourth sub-area, the second sub-area and the third sub-area are distributed adjacent to each other, a first pixel driving unit is distributed in the first sub-area, a second pixel driving unit is distributed in the second sub-area and the third sub-area, and at least a portion of the multiplexer is located in the fourth sub-area.

[0011] An embodiment of the second aspect of this application also provides a display panel, including a display area and a non-display area. The display panel includes: an array substrate, which is the array substrate as described above; and a light-emitting component located on the side of the array layer facing away from the substrate, the light-emitting component including a light-emitting unit located in the display area.

[0012] An embodiment of the third aspect of this application also provides a display panel, including a display area and a non-display area. The display panel includes: an array substrate, including multiple pixel driving circuits and multiple multiplexers, with the multiple pixel driving circuits distributed in N driving rows along a first direction in the display area, and at least a portion of the multiplexers distributed in M ​​data rows. A light-emitting component is disposed on the array substrate, and the light-emitting component includes multiple light-emitting units, which are distributed in N light-emitting rows along the first direction in the display area. The first direction intersects the thickness direction of the array substrate, wherein at least a portion of the light-emitting rows have their orthogonal projections on the array substrate covering the M data rows.

[0013] According to an embodiment of the third aspect of this application, along a first direction, the driving rows from row 1 to row i of the N driving rows are distributed with a first spacing, and the driving rows from row i+1 to row N are distributed with a second spacing, wherein the first spacing is greater than the second spacing. The orthographic projection of the light-emitting rows from row 1 to row i of the N light-emitting rows on the array substrate corresponds one-to-one with the driving rows from row 1 to row i, and the orthographic projection of the light-emitting rows from row i+1 to row N on the array substrate is staggered with the driving rows corresponding to themselves from row i+1 to row N, and covers the driving rows from row i to row N and the M data rows.

[0014] According to an embodiment of the third aspect of this application, along the first direction, adjacent driving rows in the N driving rows are equally spaced. The orthographic projection of the N light-emitting rows onto the array substrate covers the N driving rows and M data rows.

[0015] An embodiment of the fourth aspect of this application also provides a display device, including a display panel as described above.

[0016] In the array substrate, display panel, and display device provided in this application, the array substrate includes a first region and a second region, and the second region is provided with a driving chip. The array substrate includes a substrate and an array layer, and the array layer includes a pixel driving circuit and a multiplexer. At least some of the multiplexers are disposed in the first region, reducing the space for arranging the multiplexers in the second region, thereby reducing the overall area of ​​the second region, reducing the size of the bottom bezel of the display panel, and achieving a narrow bezel of the display panel. Attached Figure Description

[0017] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, wherein the same or similar reference numerals denote the same or similar features.

[0018] Figure 1 This is a top view of an array substrate provided in an embodiment of this application;

[0019] Figure 2 This is a top view schematic diagram of another array substrate provided in the embodiments of this application;

[0020] Figure 3 This is a top view schematic diagram of another array substrate provided in the embodiments of this application;

[0021] Figure 4 This is a schematic cross-sectional view of an array substrate provided in an embodiment of this application;

[0022] Figure 5 This is a top view schematic diagram of another array substrate provided in the embodiments of this application;

[0023] Figure 6 This is a top view of a display panel provided in an embodiment of this application;

[0024] Figure 7 yes Figure 6 A schematic diagram of the enlarged structure of Q;

[0025] Figure 8 This is a cross-sectional structural diagram of a display panel provided in an embodiment of this application;

[0026] Figure 9 This is a cross-sectional structural diagram of a display panel provided in an embodiment of this application.

[0027] Explanation of reference numerals in the attached figures:

[0028] 100, Array substrate; 200, Display panel;

[0029] SA1, First Zone; SA11, First Functional Zone; SA111, First Sub-zone; SA112, Second Sub-zone; SA12, Second Functional Zone; SA121, Third Sub-zone; SA122, Fourth Sub-zone; SA2, Second Zone; AA, Display Zone; NA, Non-Display Zone;

[0030] 10. Array layer; 11. Pixel driving circuit; 111. First pixel driving unit; 112. Second pixel driving unit; 12. Multiplexer; 13. Driving row; 131. First driving row; 132. Second driving row; 14. Data row;

[0031] 20. Driver chip;

[0032] 30. Light-emitting component; 31. Light-emitting unit; 32. Light-emitting row;

[0033] X, the first direction; Y, the second direction.

[0034] In the accompanying drawings, the same parts use the same reference numerals. The drawings are not drawn to scale. Detailed Implementation

[0035] The features and exemplary embodiments of various aspects of this application will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a comprehensive understanding of this application. However, it will be apparent to those skilled in the art that this application can be implemented without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of this application by illustrating examples. In the accompanying drawings and the following description, at least some well-known structures and techniques are not shown to avoid unnecessarily obscuring the application; and, for clarity, the dimensions of some structures may be exaggerated. Furthermore, the features, structures, or characteristics described below can be combined in any suitable manner in one or more embodiments.

[0036] In the description of this application, it should be noted that, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," etc., indicating orientation or positional relationships are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0037] The directional terms appearing in the following description refer to the directions shown in the figures and are not intended to limit the specific structure of the embodiments of this application. It should also be noted in the description of this application that, unless otherwise explicitly specified and limited, the terms "installation" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0038] With the increasing prevalence of full-screen smartphones and the growing popularity of high screen-to-body ratios, many narrow-bezel solutions have emerged, primarily targeting the left and right bezels. However, improving the bottom bezel remains a significant challenge for smartphones. Screen-to-body ratio refers to the ratio of screen area to the overall device area. A higher screen-to-body ratio provides a better visual experience for users. Flexible OLED displays are currently a key element enabling dual-curved designs, and as flexible OLED technology matures, future smartphone designs and physical forms will inevitably undergo further innovation and transformation.

[0039] Therefore, many manufacturers have adopted the COF (chip on film) solution for the bottom bezel of displays. Compared to the conventional COG (chip on glass) design, this reduces the width of the bottom bezel and increases the screen-to-body ratio. The COF solution involves bonding the chip (IC) to an FPC (Flexible Printed Circuit), which is then bent. This saves space that was previously used for bonding the chip on the panel. However, the COF solution also has many problems. For example, the multiplexing circuitry used to reduce the output signal lines of the driver chip, the fan-out traces, and the performance testing circuitry of the display panel are all located on the bottom bezel. Furthermore, these circuits cannot be bent along with the chip to the side of the display panel facing away from the light-emitting surface, causing them to occupy a certain amount of space on the bottom bezel, which is detrimental to achieving a narrower bezel for the display panel.

[0040] Therefore, in order to solve the above problems, this application provides an array substrate, a display panel, and a display device.

[0041] To better understand this application, the following will be combined with... Figures 1 to 9 The array substrate, display panel, and display device according to embodiments of this application will be described in detail.

[0042] Figure 1 This is a top view of an array substrate provided in an embodiment of this application.

[0043] like Figure 1As shown, this application embodiment provides an array substrate 100, including a first region SA1 and a second region SA2. A driver chip 20 is disposed in the second region SA2. The array substrate 100 includes a substrate and an array layer 10. The array layer 10 is located on one side of the substrate and includes a pixel driving circuit 11 and a multiplexer 12. At least a portion of the pixel driving circuit 11 is disposed on the same layer as the multiplexer 12. The multiplexer 12 is electrically connected to the driver chip 20. At least a portion of the multiplexer 12 is located in the first region SA1.

[0044] In this embodiment, the array substrate 100 includes a first region SA1 and a second region SA2. Optionally, the shape of the first region SA1 includes a rectangle, a circle, an annulus, or other shapes. Optionally, the second region SA2 is disposed around the first region SA1. For example, the second region SA2 is located on the periphery of the first region SA1, and the shape of the second region SA2 matches that of the first region SA1. A driver chip 20 is disposed within the second region SA2. Optionally, the driver chip can be disposed on the FPC using a COF (chip on film) scheme.

[0045] The array substrate 100 includes a substrate and an array layer 10. Optionally, the substrate may include a transparent or opaque insulating material. The substrate may include one or more layers. The substrate may include a flexible, transparent organic material layer, such as a polyimide resin layer. The substrate may also include an inorganic material layer, such as a silicon oxide layer or a silicon nitride layer. The inorganic material layer can block the penetration of water and oxygen. The structure of the substrate can be varied and can be selected according to actual needs. Optionally, the substrate can be a rigid substrate. The rigid substrate can be, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate. In this case, the array substrate 100 can be a rigid array substrate. Alternatively, the substrate can be a flexible substrate. The flexible substrate can be, for example, a PET (Polyethylene terephthalate) substrate, a PEN (Polyethylene naphthalate dimethyl methacrylate) substrate, or a PI (Polyimide) substrate. In this case, the array substrate 100 can be a flexible array substrate.

[0046] Optionally, the array layer 10 includes a pixel driving circuit 11 and a multiplexer 12. The pixel driving circuit 11 includes an active layer, a gate layer, and a source / drain layer stacked along the thickness direction of the array substrate 100. The multiplexer 12 is connected to an output / input signal bus and output / input signal branches. In some optional examples, the multiplexer 12 is electrically connected to the driver chip 20. The output signal of the driver chip 20 is transmitted to the pixel driving circuit 11 through the multiplexer 12, and the output signal of the pixel driving circuit 11 is transmitted to the driver chip 20 through the multiplexer 12. Each multiplexer 12 is electrically connected to the driver chip 20 through one output / input signal bus, and each multiplexer 12 is electrically connected to the pixel driving circuit 11 through multiple output / input signal branches. Optionally, at least some of the multiplexers 12 and the output / input signal branches are located in the first region SA1, and some of the output / input signal buses are located in the second region SA2. In other words, all multiplexers 12 are located in the first region SA1. Alternatively, some of the multiplexers 12 may be located in the first zone SA1, and some of the multiplexers 12 may be located in the second zone SA2.

[0047] Optionally, at least a portion of the pixel driving circuit 11 is disposed on the same layer as the multiplexer 12. For example, the multiplexer 12 and the pixel driving circuit 11 are spaced apart. Alternatively, the multiplexer 12 and the pixel driving circuit 11 are disposed adjacent to each other.

[0048] In the array substrate 100 provided in this application, the array substrate 100 includes a first region SA1 and a second region SA2, and the second region SA2 is provided with a driver chip 20. The array substrate 100 includes a substrate and an array layer 10. The array layer 10 includes a pixel driving circuit 11 and a multiplexer 121. At least a portion of the multiplexer 12 is disposed in the first region SA1, reducing the space for arranging the multiplexer 12 in the second region SA2, thereby reducing the overall area of ​​the second region SA2, reducing the size of the bottom bezel of the display panel 200, and achieving a narrow bezel of the display panel 200.

[0049] Figure 2 This is a top view of another array substrate provided in the embodiments of this application. Figure 3 This is a top view of another array substrate provided in the embodiments of this application. Figure 4 This is a cross-sectional structural diagram of an array substrate provided in an embodiment of this application.

[0050] Please see Figures 2 to 4 In some optional embodiments, the first region SA1 includes a first functional region SA11 and a second functional region SA12 arranged sequentially, with at least a portion of the pixel driving circuit 11 located in the first functional region SA11 and at least a portion of the multiplexer 12 located in the second functional region SA12.

[0051] In this embodiment of the application, by adjusting the pixel driving circuit 11 as described above, the second functional area SA12 has space to arrange the multiplexer 12, thereby reducing the space in the second area SA2 used to arrange the multiplexer 12 and reducing the overall area of ​​the second area SA2.

[0052] Optionally, taking the shape of the first area SA1 as a rectangle and the shape of the second area SA2 as a rectangular ring surrounding the first area SA1 as an example, the second functional area SA12 can be located in the area near the second area SA2 where the driver chip 20 is located, and the first functional area SA11 is located on the side of the second functional area SA12 away from the area where the second area SA2 is located where the driver chip 20 is located.

[0053] Optionally, the first functional area SA11 and the second functional area SA12 equally divide the first functional area SA1. Of course, the area of ​​the first functional area SA11 may be different from the area of ​​the second functional area SA12. For example, the area of ​​the first functional area SA11 is larger than the area of ​​the second functional area SA12. Or the area of ​​the first functional area SA11 is smaller than the area of ​​the second functional area SA12.

[0054] Optionally, all pixel driving circuits 11 may be located in the first functional area SA11. Alternatively, some pixel driving circuits 11 may be located in the first functional area SA11, and some pixel driving circuits 11 may be located in the second functional area SA12. Optionally, all multiplexers 12 may be located in the second functional area SA12. Alternatively, some multiplexers 12 may be located in the second functional area SA12, some multiplexers 12 may be located in the second functional area SA2, and some multiplexers 12 may be located in the first functional area SA11.

[0055] Please see Figure 2 In some optional embodiments, the pixel driving circuits 11 are all distributed in the first functional area SA11, and the multiplexer 12 is located in the second functional area SA12. By compressing the arrangement space of the pixel driving circuits 11 in the first area SA1, the arrangement space of the multiplexer 12 in the first area SA1 is increased.

[0056] Please see Figure 3 In some optional embodiments, the pixel driving circuit 11 includes a first pixel driving unit 111 and a second pixel driving unit 112. The first pixel driving unit 111 is located in a first functional area SA11, and the second pixel driving unit 112 is located at least in a second functional area SA12. At least part of the multiplexer 12 is located in the second functional area SA12.

[0057] Optionally, there may be multiple first pixel driving units 111, and the multiple first driving pixel units are arranged in an array in the first functional area SA11. Of course, the multiple first pixel driving units 111 may also be arranged in other ways.

[0058] Optionally, there may be multiple second pixel driving units 112, and the multiple second driving pixel units are arranged in an array in the second functional area SA12. Of course, the multiple second pixel driving units 112 may also be arranged in other ways.

[0059] Optionally, the second pixel driving unit 112 and the multiplexer 12 can be arranged alternately. Alternatively, the second pixel driving unit 112 and the multiplexer 12 can be arranged sequentially.

[0060] Please see Figure 3 In some optional embodiments, a plurality of first pixel driving units 111 are distributed in a plurality of first driving rows 131 along a first direction X, and a plurality of second pixel driving units 112 are distributed in a plurality of second driving rows 132 along the first direction X. The spacing between two adjacent first driving rows 131 is greater than the spacing between two adjacent second driving rows 132. The first direction X intersects with the thickness direction of the array substrate 100.

[0061] This application embodiment reduces the arrangement space of the second pixel driving unit 112 in the second functional area SA12 by reducing the spacing between two adjacent second driving rows 132. While ensuring the normal use of the pixel driving circuit, it increases the space for arranging the multiplexer 12 in the second functional area SA12, thereby reducing the arrangement space of the multiplexer 12 in the second area SA2 and reducing the overall area of ​​the second area SA2.

[0062] It should be noted that the driving row 13, data row 14 and light-emitting row 32 in this embodiment are illustrated by way of an arrangement that extends in a row along the second direction Y.

[0063] Optionally, the spacing between any two adjacent first drive rows 131 in the plurality of first drive rows 131 is set to be equal. Optionally, the spacing between any two adjacent first drive rows 131 in the plurality of second drive rows 132 is set to be equal. Optionally, the spacing between two adjacent first drive rows 131 in the plurality of second drive rows 132 is set to gradually increase or gradually decrease. Optionally, the first direction X can be the direction in which the first functional area SA11 and the second functional area SA12 are arranged sequentially.

[0064] Please see Figure 4 In some alternative embodiments, the size of the first pixel driving unit 111 is larger than the size of the second pixel driving unit 112, and the first direction X intersects the thickness direction of the array substrate 100.

[0065] This application embodiment reduces the arrangement space of the second pixel driving unit 112 in the second functional area SA12 by reducing the size of the second pixel driving unit 112 along the first direction X, thereby increasing the space for arranging the multiplexer 12 in the second functional area SA12, and thus reducing the arrangement space of the multiplexer 12 in the second area SA2 and reducing the overall area of ​​the second area SA2.

[0066] Optionally, the multiple first pixel driving units 111 have the same size along the first direction X.

[0067] Optionally, the plurality of second pixel driving units 112 have the same size along the first direction X. Alternatively, the plurality of second pixel driving units 112 include a first part and a second part, wherein the size of the first part of the second pixel driving unit 112 along the first direction X is smaller than the size of the second part of the second pixel driving unit 112 along the first direction X, and the size of the second part of the second pixel driving unit 112 along the first direction X is smaller than the size of the first pixel driving unit 111 along the first direction X.

[0068] As can be seen from the foregoing, in the array substrate 100, the spacing between two adjacent first driving rows 131 is greater than the spacing between two adjacent second driving rows 132, and the size of the first pixel driving unit 111 along the first direction X is greater than the size of the second pixel driving unit 112 along the first direction X.

[0069] Optionally, the size of the first pixel driving unit 111 along the second direction Y can be greater than or equal to the size of the second pixel driving unit 112 along the second direction Y, thereby reducing the space occupied by the second pixel driving unit 112 in the second functional area SA12 in the second direction Y. This allows at least a portion of the GIP (Gate in Panel) circuit and at least a portion of the electrostatic discharge circuit in the second area SA2 along the second direction Y to be disposed in the first area SA1, further reducing the overall area of ​​the second area SA2. Optionally, the first direction X, the second direction Y, and the thickness direction of the array substrate 100 intersect each other.

[0070] Figure 5 This is a top view of another array substrate provided in the embodiments of this application.

[0071] Please see Figure 5In some optional embodiments, along the first direction X, the first functional area SA11 includes a first sub-area SA111 and a second sub-area SA112, the second functional area SA12 includes a third sub-area SA121 and a fourth sub-area SA122, the second sub-area SA112 and the third sub-area SA121 are distributed adjacent to each other, the first pixel driving unit 111 is distributed in the first sub-area SA111, the second pixel driving unit 112 is distributed in the second sub-area SA112 and the third sub-area SA121, and at least a portion of the multiplexer 12 is located in the fourth sub-area SA122.

[0072] This application embodiment increases the arrangement space of the multiplexer 12 in the second functional area SA12 by compressing the arrangement space of the first pixel driving unit 111 in the first area SA1, thereby increasing the space for arranging the multiplexer 12 in the second functional area SA12, thereby reducing the arrangement space of the multiplexer 12 in the second area SA2 and reducing the overall area of ​​the second area SA2.

[0073] Optionally, the first sub-region SA111 and the second sub-region SA112 can equally divide the first functional area SA11. Of course, the area of ​​the first sub-region SA111 and the area of ​​the second sub-region SA112 can be different.

[0074] Optionally, the third sub-region SA121 and the fourth sub-region SA122 can equally divide the second functional area SA12. Of course, the area of ​​the third sub-region SA121 and the area of ​​the fourth sub-region SA122 can be different.

[0075] In some examples, the first pixel driving unit 111 can reduce its arrangement space in the first sub-region SA111 by reducing its own size along the first direction X. In other examples, the first pixel driving unit 111 can reduce its arrangement space in the first sub-region SA111 by reducing the spacing between two adjacent first driving rows 131. In still other examples, the first pixel driving unit 111 can reduce its arrangement space in the first sub-region SA111 by reducing both its own size along the first direction X and the spacing between two adjacent first driving rows 131.

[0076] Optionally, the second pixel driving unit 112 distributed in the second sub-region SA112 and the second pixel driving unit 112 distributed in the third sub-region SA121 can be the same, or they can be different. For example, the size of the second pixel driving unit 112 distributed in the second sub-region SA112 along the first direction X can be different from the size of the second pixel driving unit 112 distributed in the third sub-region SA121 along the first direction X. The spacing between two adjacent second driving rows 132 distributed in the second sub-region SA112 can be different from the spacing between two adjacent second driving rows 132 distributed in the third sub-region SA121.

[0077] Secondly, embodiments of this application also provide a display panel 200, including a display area AA and a non-display area NA. The display panel 200 includes: an array substrate 100, which is any of the array substrates 100 described above; and a light-emitting component 30 located on the side of the array layer 10 facing away from the substrate. The light-emitting layer includes light-emitting units 31, and the light-emitting units 31 are located in the display area AA. Since the display panel 200 provided in this application includes any of the array substrates 100 described above, the display panel 200 provided in this application has the beneficial effects of any of the array substrates 100 described above, which will not be repeated here.

[0078] Figure 6 This is a top view of a display panel provided in an embodiment of this application. Figure 7 yes Figure 6 A magnified schematic diagram of the Q-axis. Figure 8 This is a cross-sectional structural diagram of a display panel provided in an embodiment of this application.

[0079] Please see Figures 6 to 8 Thirdly, this application embodiment also provides a display panel 200, including a display area AA and a non-display area NA. The display panel 200 includes: an array substrate 100, including multiple pixel driving circuits 11 and multiple multiplexers 12, with the multiple pixel driving circuits 11 distributed in N driving rows 13 along a first direction X in the display area AA, and at least some of the multiplexers 12 distributed in M ​​data rows 14. A light-emitting component 30 is disposed on the array substrate 100, and the light-emitting component 30 includes multiple light-emitting units 31, which are distributed in N light-emitting rows 32 along the first direction X in the display area AA. The first direction X intersects the thickness direction of the array substrate 100, wherein at least some of the light-emitting rows 32 have their orthogonal projections on the array substrate 100 covering the M data rows 14.

[0080] The display panel 200 provided in this application embodiment includes an array substrate 100 and a light-emitting component 30. The pixel driving circuit 11 and the multiplexer 12 in the array substrate 100, as well as the light-emitting unit 31 in the light-emitting component 30, are all disposed in the display area AA. At least a portion of the light-emitting rows 32 are projected onto the array substrate 100 to cover M data rows 14, so that the multiplexer 12 occupies a portion of the display area AA. In related technologies, the multiplexer 12 is usually disposed in the non-display area NA. In this application embodiment, by adjusting the positions of the pixel driving circuit 11 and the multiplexer 12, the multiplexer 12 can be located in the display area AA, thereby reducing the overall space of the non-display area NA and reducing the bezel area of ​​the display panel 200.

[0081] In the embodiments of this application, repeated parts will not be described in detail, and only the differences will be explained.

[0082] Optionally, the display panel 200 may include an OLED display panel 200, a quantum dot light-emitting diode (QLED) display panel 200, etc.

[0083] Optionally, the light-emitting component 30 may include light-emitting units 31 of different colors. For example, the light-emitting component 30 includes red light-emitting units, green light-emitting units, and blue light-emitting units.

[0084] Optionally, the multiple pixel driving circuits 11 can be distributed in N driving rows 13. For example, the number of driving rows 13 includes 2, 3, 5, 10, 50, 100, 500, 1000 or more.

[0085] Optionally, at least a portion of the multiplexers 12 are distributed in M ​​data rows 14. For example, the number of data rows 14 may include 2, 3, 5, 10, 50, 100, 500, 1000 or more.

[0086] Please see Figures 6 to 8 In some optional embodiments, along the first direction X, the driving rows 13 from row 1 to row i of the N driving rows 13 are distributed with a first spacing, and the driving rows 13 from row i to row N are distributed with a second spacing, wherein the first spacing is greater than the second spacing. The orthographic projection of the light-emitting rows 32 from row 1 to row i of the N light-emitting rows 32 on the array substrate 100 corresponds one-to-one with the driving rows 13 from row 1 to row i, and the orthographic projection of the light-emitting rows 32 from row i+1 to row N on the array substrate 100 is staggered with the driving rows 13 corresponding to themselves from row i+1 to row N, and covers the driving rows 13 from row i+1 to row N and the M data rows 14.

[0087] This embodiment of the application increases the arrangement space of the data row 14 in the display area AA by adjusting the positional relationship between the driving row 13, the light-emitting row 32 and the data row 14, thereby reducing the overall area of ​​the non-display area NA.

[0088] It should be noted that, in Figure 8 In the diagram, the left side of the dashed line represents the driving row 13 from the first row to the i-th row and the luminous row 32 from the first row to the i-th row, while the right side of the dashed line represents the driving row 13 from the (i+1)-th row to the N-th row and the luminous row 32 from the (i+1)-th row to the N-th row.

[0089] It is understandable that, among the N driving rows 13, the spacing between two adjacent driving rows 13 from the first row to the i-th row is greater than the spacing between two adjacent driving rows 13 from the i-th row to the N-th row. Optionally, the N light-emitting rows 32 are arranged at equal intervals, such that the orthographic projection of the light-emitting rows 32 from the first row to the i-th row on the array substrate 100 corresponds one-to-one with the driving rows 13 from the first row to the i-th row. The area occupied by the light-emitting rows 32 from the i-th row to the N-th row in the display area AA is greater than the area occupied by the driving rows 13 from the i-th row to the N-th row in the display area AA. M data rows 14 can be arranged in the corresponding area of ​​the array substrate 100 where the light-emitting rows 32 from the i-th row to the N-th row do not cover the driving rows 13 in the display area AA.

[0090] Figure 9 This is a cross-sectional structural diagram of a display panel provided in an embodiment of this application.

[0091] Please see Figure 6 and Figure 9 In some optional embodiments, along the first direction X, adjacent driving rows 13 are equally spaced. The orthogonal projection of the N light-emitting rows 32 onto the array substrate 100 covers the N driving rows 13 and the M data rows 14.

[0092] This embodiment of the application increases the arrangement space of the data row 14 in the display area AA by adjusting the positional relationship between the driving row 13, the light-emitting row 32 and the data row 14, thereby reducing the overall area of ​​the non-display area NA.

[0093] Optionally, the arrangement space of the driving rows 13 in the display area AA can be reduced by compressing the spacing between the N driving rows 13 or by compressing the dimensions of the N driving rows 13 themselves along the first direction X. Optionally, the M data rows 14 can be distributed at equal intervals.

[0094] Fourthly, embodiments of this application also provide a display device, including any of the display panels described above. Since the display device provided in this application includes any of the display panels described above, it possesses the beneficial effects of any of the display panels described above, which will not be elaborated further here.

[0095] The display devices in this application include, but are not limited to, mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, control consoles, and other devices with display functions.

[0096] Although this application has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of this application. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A display panel, comprising a display area and a non-display area, characterized in that, The display panel includes: An array substrate includes multiple pixel driving circuits and multiple multiplexers. Along a first direction in the display area, the multiple pixel driving circuits are distributed in N driving rows, and at least some of the multiplexers are distributed in M ​​data rows. A light-emitting component is disposed on the array substrate. The light-emitting component includes multiple light-emitting units, which are distributed in N light-emitting rows in the display area along a first direction. The first direction intersects the thickness direction of the array substrate. Wherein, at least some of the light-emitting rows are projected onto the array substrate and cover the M data rows, and the N light-emitting rows are projected onto the array substrate and cover the N driving rows.

2. The display panel according to claim 1, characterized in that, Along the first direction, the driving rows from row 1 to row i of the N driving rows are distributed with a first spacing, and the driving rows from row i+1 to row N are distributed with a second spacing, wherein the first spacing is greater than the second spacing. The light-emitting rows 1 to i in the array substrate are projected onto the array substrate in a one-to-one correspondence with the driving rows 1 to i. The light-emitting rows i+1 to N in the array substrate are projected onto the array substrate in a staggered distribution with the driving rows i+1 to N corresponding to themselves, and cover the driving rows i+1 to N and M data rows.

3. The display panel according to claim 1, characterized in that, Along the first direction, adjacent drive rows in the N drive rows are all equally spaced; The orthographic projection of the N light-emitting rows onto the array substrate covers the N driving rows and the M data rows.

4. The display panel according to claim 1, characterized in that, The array substrate includes a first region and a second region, wherein a driving chip is disposed in the second region, and the array substrate includes: Substrate; An array layer is located on one side of the substrate. The array layer includes the pixel driving circuit and the multiplexer. At least a portion of the pixel driving circuit is disposed on the same layer as the multiplexer. The multiplexer is electrically connected to the driving chip. At least a portion of the multiplexer is located in the first region.

5. The display panel according to claim 4, characterized in that, The first area includes a first functional area and a second functional area arranged sequentially, with at least a portion of the pixel driving circuit located in the first functional area and at least a portion of the multiplexer located in the second functional area.

6. The display panel according to claim 5, characterized in that, The pixel driving circuits are all distributed in the first functional area, and the multiplexer is located in the second functional area.

7. The display panel according to claim 5, characterized in that, The pixel driving circuit includes a first pixel driving unit and a second pixel driving unit. The first pixel driving unit is located in the first functional area, and the second pixel driving unit is located at least in the second functional area. At least a portion of the multiplexer is located in the second functional area.

8. The display panel according to claim 7, characterized in that, The plurality of first pixel driving units are distributed in a plurality of first driving rows along a first direction, and the plurality of second pixel driving units are distributed in a plurality of second driving rows along the first direction. The spacing between two adjacent first driving rows is greater than the spacing between two adjacent second driving rows. The first direction intersects with the thickness direction of the array substrate.

9. The display panel according to claim 8, characterized in that, The size of the first pixel driving unit is larger than the size of the second pixel driving unit.

10. The display panel according to claim 7, characterized in that, Along a first direction, the first functional area includes a first sub-area and a second sub-area, the second functional area includes a third sub-area and a fourth sub-area, the second sub-area and the third sub-area are distributed adjacent to each other, the first pixel driving unit is distributed in the first sub-area, the second pixel driving unit is distributed in the second sub-area and the third sub-area, and the at least part of the multiplexer is located in the fourth sub-area.

11. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 10.

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