Method of accessing a memory and memory device using the same

Abstract

The present application provides a method for accessing a memory and a memory device using the method. The method includes: coupling, by a primary sense amplifier of the memory, a memory cell of the memory to receive data from the memory cell; coupling a first end of a transistor of the memory to the primary sense amplifier; coupling a first instruction end of a system on chip to a second end of the transistor and coupling a first input / output end of the system on chip to a third end of the transistor; and sending, by the system on chip, an access instruction to the second end of the transistor to access the data output by the primary sense amplifier through the third end of the transistor.

Description

Technical Field

[0001] The present invention relates to a method for accessing memory and a memory device using the method. Background Technology

[0002] Traditional dynamic random access memory (DRAM) access methods require a controller to issue row and column commands. The controller issues a row command along with the memory address to select a word line in the memory repository. After the word line is selected, data in the memory cell controlled by that word line is transferred to the memory's first-level sense amplifier. Next, the controller issues a column command to select a column select line. The enabled column select line transfers a small amount of data from the first-level sense amplifier to the second-level sense amplifier. Finally, the controller sends a command to the second-level sense amplifier to an external device.

[0003] The reason why the bar select line cannot transmit data to many first-stage sense amplifiers simultaneously is that the space available for placing the bar select line and data lines on a two-dimensional plane is limited. Furthermore, the cell array in dynamic random access memory (DRAM) is arranged in a dense manner. As the density of DRAM increases, the number of DRAM cell blocks increases, thus requiring an increase in the total path length of the bar select line. On the other hand, with increased density, the total path length of the main data line (MDQ) used to transmit data from the first-stage sense amplifier to the second-stage sense amplifier also needs to increase. When the lengths of the bar select line and the main data line (MDQ) are extremely long, the linewidth of the bar select line and MDQ cannot be significantly reduced. In other words, the linewidth of the bar select line and MDQ limits the number of first-stage sense amplifiers that can be accessed at any given time. Summary of the Invention

[0004] The present invention provides a method for accessing memory and a memory device using the method, which can improve the read / write bandwidth of memory based on three-dimensional chip stacking technology.

[0005] A memory device according to the present invention includes a memory and a system-on-a-chip (SoC). The memory includes a memory cell, a first-stage sense amplifier, and a transistor. The first-stage sense amplifier is coupled to the memory cell and receives data from the memory cell. A first terminal of the transistor is coupled to the first-stage sense amplifier. The SoC includes a first instruction terminal and a first input / output terminal, wherein the first instruction terminal is coupled to a second terminal of the transistor, and the first input / output terminal is coupled to a third terminal of the transistor, wherein the SoC sends an access command to the second terminal of the transistor to access data output by the first-stage sense amplifier through the third terminal of the transistor.

[0006] In one embodiment of the present invention, the first instruction terminal is coupled to a plurality of second terminals corresponding to a plurality of transistors, wherein the plurality of transistors comprise transistors and the plurality of second terminals comprise second terminals.

[0007] The present invention discloses a method for accessing memory, applicable to a system-on-a-chip (SoC) and a memory, comprising: coupling a primary sense amplifier of the memory to a memory cell to receive data from the memory cell; coupling a first terminal of a transistor of the memory to the primary sense amplifier; coupling a first instruction terminal of the SoC to a second terminal of the transistor, and coupling a first input / output terminal of the SoC to a third terminal of the transistor; and sending an access instruction from the SoC to the second terminal of the transistor to access data output by the primary sense amplifier through the third terminal of the transistor.

[0008] Based on the above, this invention utilizes three-dimensional chip stacking technology to increase memory access speed, enabling access speeds to reach or exceed 16K bits. For system-on-a-chip (SoC) applications that increasingly prioritize memory access speed and bandwidth, the performance of SoCs employing this invention can be significantly improved. Attached Figure Description

[0009] Figure 1 A schematic diagram of a traditional dynamic random access memory architecture is shown;

[0010] Figure 2 A schematic diagram of a conventional single-stage sense amplifier circuit is shown.

[0011] Figure 3 A schematic diagram of a memory device is shown according to an embodiment of the present invention;

[0012] Figure 4 A schematic diagram illustrating the connection of a system chip and a memory based on hybrid bonding technology according to an embodiment of the present invention is shown;

[0013] Figure 5 A flowchart of a method for accessing memory is shown according to an embodiment of the present invention.

[0014] Explanation of reference numerals in the attached figures

[0015] 10: Dynamic Random Access Memory cell block;

[0016] 11: Box;

[0017] 100: Memory device;

[0018] 20: Circuit;

[0019] 300: System-on-a-Chip (SoC);

[0020] 301, 302: Command line;

[0021] 303, 304: Input / output terminals;

[0022] 400: Memory;

[0023] 410, 420: Transistors;

[0024] 411, 412, 413, 421, 422, 423: End;

[0025] 430: First-stage sensing amplifier;

[0026] 431, 432: Inverters;

[0027] 440: Storage unit;

[0028] 450: Controller;

[0029] 610, 620: Bare crystal;

[0030] S501, S502, S503, S504: Steps. Detailed Implementation

[0031] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0032] Figure 1 A schematic diagram of a conventional dynamic random access memory (DRAM) architecture is shown. DRAM cell block 10 may contain multiple memory cells. After the controller selects the word line WL corresponding to DRAM cell block 10 via a row instruction, the word line WL enables DRAM cell block 10 to transmit data from multiple memory cells to multiple first-stage sense amplifiers respectively. Taking current memory manufacturing processes as an example, in... Figure 1 In the middle, the word line WL can enable multiple memory cells that can store a total of 16K bits of data, of which 8K bits of data are transmitted to multiple first-stage sense amplifiers located on the left side of the dynamic random access memory cell block 10, and another 8K bits of data are transmitted to multiple first-stage sense amplifiers located on the right side of the dynamic random access memory cell block 10.

[0033] After the controller selects the column select line corresponding to box 11, the four first-stage sense amplifiers on the left side of box 11 will output 4 bits of data, and the four first-stage sense amplifiers on the right side of box 11 will also output 4 bits of data. In other words, the controller can access 8 bits of data through a single column select line. Assume that the memory layout is limited by the available area, causing the controller to enable only 16 column select lines simultaneously. Therefore, the controller can only access 128 bits (8 * 16 = 128) of data at a time. If the controller wants to access the 16K bits of data enabled by the WL (Write-Only Line), it needs to enable the column select line 128 times, consuming a significant amount of time.

[0034] Figure 2 A schematic diagram of a conventional single-stage sense amplifier circuit 20 is shown. Circuit 20 mainly consists of two inverters connected end-to-end. Because the column select line CSL and main data line MDQ in circuit 20 need to span the entire cell array of the memory, the lengths of the column select line CSL and main data line MDQ are very long. Consequently, the linewidths of the column select line CSL and main data line MDQ cannot be significantly reduced. Much of the two-dimensional planar space of the memory is occupied by the column select line CSL and main data line MDQ, thus limiting the number of memory cells that a single column select line CSL can access.

[0035] In order to increase the access speed and bandwidth of memory, the present invention proposes a memory device 100. Figure 3 A schematic diagram of a memory device 100 is shown according to an embodiment of the present invention. The memory device 100 may include a system on a chip (SoC) 300 and a memory 400.

[0036] System-on-a-chip (SoC) 300 is an electronic system implemented by integrated circuits. SoC 300 may include, but is not limited to, an instruction terminal 301, an instruction terminal 302, an input / output (I / O) terminal 303, and an input / output terminal 304. SoC 300 can control memory 400 via instruction terminal 301 or instruction terminal 302, and can write data to or read data from memory 400 via input / output terminal 303 or input / output terminal 304.

[0037] The memory 400 may include, but is not limited to, dynamic random access memory or static random access memory (SRAM). The memory 400 may include, but is not limited to, transistors 410 and 420, a first-stage sense amplifier 430, a storage cell 440, and a controller 450.

[0038] In one embodiment, the system chip 300 and the memory 400 may be packaged in different dies. Figure 4 A schematic diagram of a system-on-a-chip (SoC) 300 and a memory 400 connected using hybrid bonding technology is shown according to an embodiment of the present invention. The SoC 300 may be packaged in a bare die 610, and the memory 400 may be packaged in a bare die 620. The bare die 610 may be bonded to the bare die 620 through one or more through silicon vias (TSVs) based on hybrid bonding technology. In other words, the memory device 100 may include a three-dimensional stacked architecture.

[0039] Back Figure 3 Transistor 410 may include terminals 411, 412, and 413. If transistor 410 is a bipolar junction transistor (BJT), terminal 411 may be the collector, terminal 412 may be the base, and terminal 413 may be the emitter. If transistor 410 is a field-effect transistor (FET), terminal 411 may be the drain, terminal 412 may be the gate, and terminal 413 may be the source. Terminal 411 may be coupled to the input / output terminal 303 of system chip 300, terminal 412 may be coupled to the instruction terminal 301 of system chip 300, and terminal 413 may be coupled to the inverted bit line BLB of first-stage sense amplifier 430.

[0040] Transistor 420 may include terminals 421, 422, and 423. If transistor 420 is a bipolar transistor, terminal 421 may be the collector, terminal 422 may be the base, and terminal 423 may be the emitter. If transistor 420 is a field-effect transistor, terminal 421 may be the drain, terminal 422 may be the gate, and terminal 423 may be the source. Terminal 421 may be coupled to the input / output terminal 304 of system chip 300, terminal 422 may be coupled to the instruction terminal 302 of system chip 300, and terminal 423 may be coupled to the bit line BL of the first-stage sense amplifier 430. If the value of bit line BL is 1, then the value of the inverted bit line BLB is 0. If the value of bit line BL is 0, then the value of the inverted bit line BLB is 1.

[0041] The primary sense amplifier 430 may include inverters 431 and 432. The input of inverter 431 may be coupled to the output of inverter 432, and the output of inverter 431 may be coupled to the input of inverter 432. The output of inverter 431 may be coupled to memory cell 440 via bit line BL. The output of inverter 432 may be coupled to memory cell 440 via inverted bit line BLB. The primary sense amplifier 430 may receive data from memory cell 440. Specifically, memory cell 440 may be coupled to controller 450 via word line WL. After controller 450 enables memory cell 440 via word line WL, data stored in memory cell 440 may be transferred to BL or BLB. The primary sense amplifier 430 may receive and store data from memory cell 440 via bit line BL or inverted bit line BLB. In other words, controller 450 may instruct memory cell 440 to transfer data to primary sense amplifier 430 via word line WL.

[0042] In one embodiment, the system-on-a-chip (SoC) 300 may be coupled to the controller 450. When the SoC 300 wishes to access data in the memory unit 440, it may send a command to the controller 450 to instruct the controller 450 to enable the memory unit 440 via word line WL. In one embodiment, the functionality of the controller 450 may be implemented by the SoC 300. When the SoC 300 wishes to access data in the memory unit 440, it may enable the memory unit 440 via word line WL.

[0043] After the memory cell 440 transmits data to the inverted bit line BLB, the instruction terminal 301 of the system chip 300 can send an access command to terminal 412 of transistor 410 to turn on terminals 411 and 413 of transistor 410. Then, the input / output terminal 303 of the system chip 300 can access the data on the inverted bit line BLB through terminals 411 and 413. On the other hand, after the memory cell 440 transmits data to the bit line BL, the instruction terminal 302 of the system chip 300 can send an access command to terminal 422 of transistor 420 to turn on terminals 421 and 423 of transistor 420. Then, the input / output terminal 304 of the system chip 300 can access the data on the bit line BL through terminals 421 and 423. In other words, the system chip 300 can access the data output by the first-stage sense amplifier 430 by sending an access command.

[0044] When the memory 400 contains N (N is any positive integer) memory cells 440, the system chip 300 can be designed to include N input / output terminals (e.g., input / output terminal 303 or input / output terminal 304). The system chip 300 can simultaneously access data in the N memory cells 440 by enabling N transistors 410 (or N transistors 420) corresponding to the N memory cells 440 respectively via an instruction terminal (e.g., instruction terminal 301 or instruction terminal 302). That is, the access rate or bandwidth of the memory 400 can increase as N increases. The access rate or bandwidth of the memory 400 will not be limited by the layout of the column select line CSL or the main data line MDQ. In one embodiment, the instruction terminal 301 (or instruction terminal 302) of the system chip 300 can be coupled to the N terminals 410 corresponding to the N transistors 410 (or N transistors 420). In this way, the system chip 300 can send a single access instruction through the instruction terminal 301 (or instruction terminal 302) to access N memory units 440, thereby reducing the number of instructions between the system chip 300 and the memory 400.

[0045] Figure 5 A flowchart of a method for accessing memory is shown according to an embodiment of the present invention, wherein the method may be performed by, for example Figure 3 The illustrated memory device 100 is implemented. In step S501, a primary sense amplifier of the memory is coupled to a memory cell to receive data from the memory cell. In step S502, a first terminal of a transistor of the memory is coupled to the primary sense amplifier. In step S503, a first instruction terminal of the system chip is coupled to a second terminal of the transistor, and a first input / output terminal of the system chip is coupled to a third terminal of the transistor. In step S504, the system chip sends an access command to the second terminal of the transistor to access the data output by the primary sense amplifier through the third terminal of the transistor.

[0046] In summary, the system-on-a-chip (SoC) of this invention can directly connect to the first-stage sense amplifier of memory in different bare dies via hybrid bonding technology to access data. Compared to traditional methods that require multiple column selects to read all data from the memory, the memory of this invention can directly transfer data from the first-stage sense amplifier to the SoC without performing column selects. Therefore, this invention can reduce the time required to perform column selects, thereby increasing the read / write bandwidth of the memory.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory device, characterized in that, include: Memory, including: Storage unit; A first-stage sense amplifier, coupled to the memory cell and receiving data from the memory cell; and A transistor, wherein a first terminal of the transistor is coupled to the first-stage sense amplifier; and A system-on-a-chip (SoC) includes a first instruction terminal and a first input / output terminal, wherein the first instruction terminal is coupled to a second terminal of a transistor, and the first input / output terminal is coupled to a third terminal of the transistor. The system chip sends an access command to the second terminal of the transistor to access the data output by the first-stage sense amplifier through the third terminal of the transistor, wherein The system chip is packaged on a first die, and the memory is packaged on a second die, wherein the first die is different from the second die. The first die is bonded to the second die via through-silicon vias using a hybrid bonding technique.

2. The memory device of claim 1, wherein the first instruction terminal is coupled to a plurality of second terminals corresponding to a plurality of transistors, wherein the plurality of transistors includes the transistors, and the plurality of second terminals includes the second terminals.

3. The memory device of claim 1, wherein the transistor is a bipolar transistor, wherein the first terminal of the transistor is the emitter, the second terminal of the transistor is the base, and the third terminal of the transistor is the collector.

4. The memory device of claim 1, wherein the transistor is a field-effect transistor, wherein the first terminal of the transistor is a source, the second terminal of the transistor is a gate, and the third terminal of the transistor is a drain.

5. The memory device according to claim 1, wherein the memory is a static random access memory.

6. The memory device according to claim 1, wherein the memory is a dynamic random access memory.

7. The memory device of claim 1, wherein the memory further comprises: A controller is coupled to the storage unit via a word line, wherein the controller instructs the storage unit to transmit the data to the first-stage sense amplifier via the word line.

8. A method for accessing memory, applicable to a system-on-a-chip and a memory, characterized in that, include: A primary sense amplifier of the memory is coupled to a storage cell of the memory to receive data from the storage cell; The first terminal of the transistor of the memory is coupled to the first-stage sense amplifier; The first instruction terminal of the system chip is coupled to the second terminal of the transistor, and the first input / output terminal of the system chip is coupled to the third terminal of the transistor; as well as The system chip sends an access command to the second terminal of the transistor to access the data output by the first-stage sense amplifier through the third terminal of the transistor, wherein... The system chip is packaged on a first die, and the memory is packaged on a second die, wherein the first die is different from the second die. The first die is bonded to the second die via through-silicon vias using a hybrid bonding technique.

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