Memory device and computing method using it

Abstract

This disclosure provides a memory device and a calculation method thereof. The memory device includes a memory array, word lines or word line pairs, bit line pairs, and common source lines. The memory array comprises a plurality of memory elements. Each memory element includes two memory cells. Word lines or word line pairs are connected to columns of the memory array. Bit line pairs and common source lines are connected to rows of the memory array. The memory device is configured to calculate an energy value based on a plurality of state signals and a plurality of coefficients, and the two memory cells of each memory element are configured to perform a selective selection such that one of them receives two corresponding state signals from a corresponding word line or word line pair and a corresponding bit line pair, and generates an output current to the corresponding common source line to calculate the energy value.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and computing methods using the same, and more particularly to memory devices and computing methods using the same. Background Technology

[0002] The study of optimization problems has been ongoing for a long time, resulting in various solutions such as Monte Carlo methods, simulated annealing, quantum annealing, genetic algorithms, tabu search, and neural networks. These algorithms are often inspired by natural phenomena. For example, annealing is a heat treatment commonly used in materials science, involving heating a material to a sufficiently high temperature, holding it at that temperature for an appropriate time, and then cooling it. At high temperatures, atoms in the material gain energy and migrate through the lattice. As the temperature decreases, the atoms slow down and rearrange themselves into new states with lower energies. Correspondingly, in annealing-inspired algorithms, the "temperature" can be gradually reduced over time, and at each time period, the algorithm can randomly select a new configuration close to the current configuration, compare their energy values, and then stop or move to the new configuration based on predetermined criteria. However, as the number of state signals in each configuration increases, the computation becomes more complex and difficult to execute. Summary of the Invention

[0003] This disclosure focuses on an optimized implementation of an algorithm, including a memory device for computation and a computation method.

[0004] According to some embodiments, a memory device is provided, comprising: a memory array, a plurality of word lines or word line pairs, a plurality of bit line pairs, and a plurality of common-source lines. The memory array is composed of a plurality of memory elements. Each memory element includes two memory cells. Word lines or word line pairs are connected to a plurality of columns of the memory array. Bit line pairs are connected to a plurality of rows of the memory array. Common-source lines are connected to the plurality of rows of the memory array. The memory device is configured to calculate an energy value based on a plurality of state signals and a plurality of coefficients, and the two memory cells of each memory element are configured to perform a selective selection such that one of the two memory cells of each memory element receives two corresponding state signals from a corresponding word line or a corresponding word line pair and a corresponding bit line pair, and generates an output current to a corresponding common-source line to calculate the energy value.

[0005] According to some embodiments, a calculation method is provided that calculates an energy value based on multiple state signals and multiple coefficients. The calculation method uses a memory device including a memory array comprising multiple memory elements, each memory element including two memory cells. The calculation method includes: setting state signals in the memory array, including: performing a complementary read operation to individually select one of the two memory cells of each memory element for receiving two corresponding state signals; and inputting the state signals to the selected memory cells of the memory elements, wherein the selected multiple memory cells generate multiple output currents; and calculating the energy value corresponding to the multiple state signals based on a sum of the output currents.

[0006] To provide a better understanding of the above and other aspects of this disclosure, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1A-1B This is a schematic diagram of the Yixin model;

[0008] Figure 2 This is a schematic diagram of the annealing algorithm;

[0009] Figure 3 This is a schematic diagram of a memory device according to the present disclosure;

[0010] Figure 4-9 This is a schematic diagram of various exemplary storage elements that can be used in a memory device according to the present disclosure.

[0011] Figures 10A-10F This is a schematic diagram illustrating various operations of an exemplary memory element of a memory device according to the present disclosure;

[0012] Figure 11 This is a schematic diagram of the complementary read operation according to this disclosure;

[0013] Figure 12 A schematic diagram illustrating the calculation method according to this disclosure;

[0014] Figure 13 A schematic diagram illustrating the application of the calculation method according to this disclosure;

[0015] Figure 14 A schematic diagram illustrating the advantages of the calculation method according to this disclosure;

[0016] Explanation of reference numerals in the attached figures:

[0017] 200: Configuration;

[0018] 202: Configuration;

[0019] 204: Configuration;

[0020] 206: Configuration;

[0021] BLa: First line;

[0022] BLb: Second bit line;

[0023] BLp: Bit line pair;

[0024] BL1a: First line;

[0025] BL1b: Second bit line;

[0026] BL1p: Bit line pair;

[0027] BL2a: First line;

[0028] BL2b: Second bit line;

[0029] BL2p: Bit line pair;

[0030] BL3a: First line;

[0031] BL3b: Second bit line;

[0032] BL3p: Bit line pair;

[0033] BLna: First line;

[0034] BLnb: Second bit line;

[0035] BLnp: Bit line pair;

[0036] CSL: Common Source Line;

[0037] L1: Output current;

[0038] L2: Output current;

[0039] L3: Output current;

[0040] L4: Output current;

[0041] M: Storage element;

[0042] Ma: Storage unit;

[0043] Mb: storage unit;

[0044] S1: Steps;

[0045] S2: Steps;

[0046] S3: Steps;

[0047] S4: Steps;

[0048] S5: Steps;

[0049] si: Status signal;

[0050] sj: Status signal;

[0051] WL: Word line;

[0052] WLa: First letter bar;

[0053] WLb: Second letter

[0054] WLp: Word line pair;

[0055] WL1a: First letter bar;

[0056] WL1b: Second letter line;

[0057] WL1p: Word line pair;

[0058] WL2a: First letter line;

[0059] WL2b: Second letter line;

[0060] WL2p: Word line pair;

[0061] WL3a: First letter line;

[0062] WL3b: Second letter line;

[0063] WL3p word lines;

[0064] WLna: First letter line;

[0065] WLnb: Second letter bar;

[0066] WLnp: Wordline Pair;

[0067] h1: Self-multiplication coefficient;

[0068] h2: Self-multiplication coefficient;

[0069] h3: Self-multiplication coefficient;

[0070] h N Self-multiplication coefficient;

[0071] J 12 : Interaction coefficient;

[0072] J 13 : Interaction coefficient;

[0073] J 1N : Interaction coefficient;

[0074] J 21 : Interaction coefficient;

[0075] J23 : Interaction coefficient;

[0076] J 2N : Interaction coefficient;

[0077] J 31 : Interaction coefficient;

[0078] J 32 : Interaction coefficient;

[0079] J 3N : Interaction coefficient;

[0080] J N1 : Interaction coefficient;

[0081] J N2 : Interaction coefficient;

[0082] J N3 : Interaction coefficient;

[0083] σ1: State signal;

[0084] σ2: State signal;

[0085] σ3: State signal;

[0086] σ i Status signals;

[0087] σ j Status signals;

[0088] σ N : Status signal. Detailed Implementation

[0089] The various embodiments will now be described in more detail with reference to the accompanying drawings. The descriptions and drawings are provided for illustrative purposes only and do not constitute a limitation of this disclosure. For clarity, elements may not be drawn to scale. Furthermore, some elements and / or symbols may be omitted in some drawings. It is contemplated that elements and features in one embodiment can be advantageously incorporated into another embodiment without further explanation.

[0090] Please refer to Figure 1A-1B This illustrates the Eising model. The Eising model is able to describe the energy of magnetic materials with a specific "spin". Figure 1AThis diagram illustrates a very simple Euclidean model. The model comprises two lattice sites, each with state signals σ1 and σ2. These state signals σ1 and σ2 correspond to the spins of the lattice sites, independently selected from +1 (i.e., upward spin, typically represented by an upward arrow) and -1 (i.e., downward spin, typically represented by a downward arrow). For each lattice site, the interaction between the external magnetic field and the lattice site is represented by a multiplication coefficient h1 or h2. Furthermore, the interaction between lattice sites is represented by an interaction coefficient J. 12 Therefore, the energy H of the configuration can be represented by equation (1).

[0091] H=h1σ1+h2σ2+J 12 σ1σ2 (1)

[0092] According to equation (1), the energy H of different configurations of state signals σ1 and σ2 (i.e., σ1 = -1, σ2 = -1, σ1 = -1, σ2 = +1, σ1 = +1, σ2 = +1, and σ1 = +1, σ2 = -1) can be calculated. For example, given h1 = 0.1, h2 = -0.2, J 12 =-0.3, will be as follows Figure 1B As shown, the minimum energy H is obtained when both σ1 and σ2 are +1. min At this point, the Yisin model has the optimal solution. That is, if an optimization problem corresponds to these conditions, its solution is the configuration where σ1 = +1 and σ2 = +1.

[0093] Figure 2 Identify the annealing algorithm. In each configuration 200, 202, 204, and 206, there are N state signals σ1, σ2…σ… N In the path of the corresponding simulated annealing algorithm, a temporary solution is configuration 200 with local minimum energy. With thermal perturbation, the state signal is updated to configuration 202, eventually reaching the configuration with the minimum energy H among all configurations. min Configuration 204. In the path corresponding to the quantum annealing algorithm, a temporary solution is configuration 206 with a local minimum energy. With quantum tunneling, the state signal is updated to have the minimum energy H among all configurations. min Configuration 204.

[0094] This disclosure provides a memory device capable of computation of an algorithm. The memory device includes a memory array, a plurality of word lines or word line pairs, a plurality of bit line pairs, and a plurality of common-source lines. The memory array comprises a plurality of memory elements. Each memory element includes two memory cells. Word lines or word line pairs are connected to a plurality of columns of the memory array. Bit line pairs are connected to a plurality of rows of the memory array. Common-source lines are connected to the plurality of rows of the memory array. The memory device is configured to calculate an energy value based on a plurality of state signals and a plurality of coefficients, and the two memory cells of each memory element are configured to perform a selective selection such that one of the two memory cells of each memory element receives two corresponding state signals from a corresponding word line or a corresponding word line pair and a corresponding bit line pair, and generates an output current to a corresponding common-source line to calculate the energy value.

[0095] Figure 3 An exemplary memory device according to the present disclosure is shown. The memory device includes a memory array comprising a plurality of memory elements M, a plurality of word line pairs WL1p…WLnp, a plurality of bit line pairs BL1p…BLnp, and a plurality of common source lines CSL. The word line pairs WL1p…WLnp are connected to a plurality of columns of the memory array. Each word line pair WL1p…WLnp includes first word lines WL1a…WLna and second word lines WL1b…WLnb, wherein word line pair WL1p includes a pair of first word lines WL1a and second word lines WL1b, word line pair WL2p includes a pair of first word lines WL2a and second word lines WL2b, and so on. The word line pairs WL1p…WLnp are configured to receive status signals σ1…σ1…σ2… N Bit line pairs BL1p…BLnp are connected to multiple rows of the memory array. Each bit line pair BL1p…BLnp includes first bit lines BL1a…BLna and second bit lines BL1b…BLnb, where bit line pair BL1p includes a pair of first bit lines BL1a and second bit lines BL1b, bit line pair BL2p includes a pair of first bit lines BL2a and second bit lines BL2b, and so on. Bit line pairs BL1p…BLnp are configured to receive status signals σ1…σ respectively. N The common-source line (CSL) is connected to the plurality of rows of the memory array.

[0096] Please refer to Figure 4 It shows the use of Figure 3An exemplary memory element M of the illustrated memory array is shown. Each memory element M includes two memory cells Ma and Mb. One of the two memory cells Ma and Mb is coupled to a word line in the corresponding word line pair WLp, a bit line in the corresponding bit line pair BLp, and a corresponding common-source line CSL. The other of the two memory cells Ma and Mb is coupled to another word line in the corresponding word line pair WLp, another bit line in the corresponding bit line pair BLp, and a corresponding common-source line CSL. For example, memory cell Mb is coupled to a first word line WLa, a first bit line BLa, and a corresponding common-source line CSL, and memory cell Mb is coupled to a second word line WLb, a second bit line BLb, and a corresponding common-source line CSL. Figure 4 In the diagram, the memory element M is represented as a floating-gate element with two transistors. Each memory cell Ma, Mb includes one transistor, and both transistors are of the same type, such as n-type. Each memory cell Ma, Mb may have an adjustable threshold voltage. Each memory cell Ma, Mb may be a floating-gate memory cell, a charge-trapping memory cell, or a ferroelectric field-effect transistor (FeFET) memory cell, etc.

[0097] It is understood that various memory elements can be used in the memory array according to this disclosure, with appropriate modifications to the corresponding routing and layout. According to some embodiments, each memory cell may have an adjustable threshold voltage or an adjustable resistor. According to some embodiments, each memory cell may include a transistor, or include a transistor and a resistor. According to some embodiments, each memory element M may include two transistors of the same type or two transistors of complementary types. According to some embodiments, each memory cell may be a floating-gate memory cell, a charge-trapping memory cell, a ferroelectric field-effect transistor memory cell, a resistive random access memory (ReRAM) memory cell, a bridge random access memory (CBRAM) memory cell, a phase-change (PCM) memory cell, or a magnetoresistive random access memory (MRAM) memory cell, but is not limited thereto.

[0098] Figure 5-9 Other exemplary memory elements that can be used in a memory device according to this disclosure are shown. Figure 5In the diagram, the memory element M is depicted as having a structure similar to an inverter. Each memory cell Ma, Mb includes a transistor. The two transistors are complementary. The two memory cells Ma and Mb are coupled to the same word line WL. That is, one of the two memory cells, Ma, is coupled to its corresponding word line WL, and the other memory cell, Mb, is coupled to its corresponding word line WL. It is anticipated that the memory device will include multiple word lines connected to multiple columns of the memory array, rather than word line pairs as described above. Each memory cell Ma, Mb may have an adjustable threshold voltage. Each memory cell Ma, Mb may be a floating-gate memory cell, a charge-trapping memory cell, or a ferroelectric field-effect transistor memory cell, etc.

[0099] exist Figure 6 In the diagram, the storage element M is represented as an element with two transistors and two resistors. Each storage cell Ma, Mb includes one transistor and one resistor. The two transistors are of the same type. The resistor is positioned between the transistor and the corresponding first bit line BLa or second bit line BLb. Each storage cell Ma, Mb may have an adjustable resistance. Each storage cell Ma, Mb can be a resistive random access memory cell, a bridge random access memory cell, a phase-change memory cell, or a magnetoresistive random access memory cell, etc.

[0100] exist Figure 7 In the diagram, the memory element M is represented as a component consisting of two transistors and two resistors. Each memory cell Ma, Mb includes one transistor and one resistor. The two transistors are of the same type. The resistor is positioned between the transistor and the common-source line CSL. Each memory cell Ma, Mb may have an adjustable resistance. Each memory cell Ma, Mb can be a resistive random access memory cell, a bridge random access memory cell, a phase-change memory cell, or a magnetoresistive random access memory cell, etc.

[0101] exist Figure 8 In the diagram, the memory element M is represented as an element with two transistors and two resistors. Each memory cell Ma, Mb includes one transistor and one resistor. The two transistors are complementary. The two memory cells Ma and Mb are coupled to the same word line WL. The resistor is configured between the transistor and the corresponding first bit line BLa or second bit line BLb. Each memory cell Ma, Mb may have an adjustable resistance. Each memory cell Ma, Mb can be a resistive random access memory cell, a bridge random access memory cell, a phase-change memory cell, or a magnetoresistive random access memory cell, etc.

[0102] exist Figure 9In the diagram, the memory element M is represented as a device with two transistors and two resistors. Each memory cell Ma, Mb includes one transistor and one resistor. The two transistors are complementary. The two memory cells Ma and Mb are coupled to the same word line WL. The resistor is positioned between the transistor and the common-source line CSL. Each memory cell Ma, Mb may have an adjustable resistance. Each memory cell Ma, Mb can be a resistive random access memory cell, a bridge random access memory cell, a phase-change memory cell, or a magnetoresistive random access memory cell, etc.

[0103] Please refer to now. Figures 10A-10F as well as Figure 3 and Figure 4 The following will be based on Figure 3 and Figure 4 The exemplary structure shown provides more detailed operation of the storage element M.

[0104] According to this disclosure, a memory device can be configured to calculate an energy value based on multiple state signals and multiple coefficients. Two memory cells Ma and Mb of each memory element M are configured to perform a selective selection, such that one memory cell Ma or Mb of each memory element M receives two corresponding state signals from a corresponding word line pair WLp and a corresponding bit line pair BLp, and generates an output current to the corresponding common-source line CSL to calculate the energy value.

[0105] According to some embodiments, storage elements M not configured on a diagonal of the memory array can be used to calculate energy interaction terms. An exemplary interaction coefficient J... 12 J 13 J 1N J 21 J 23 J 2N J 31 J 32 J 3N J N1 J N2 and J N3 Shown Figure 3 The corresponding storage element M. In this case, the two storage cells Ma and Mb of each storage element M not located on the diagonal of the memory array can perform the logic "XNOR", which can be represented by equation (2).

[0106] σ i XNORσ j =(-σ i )XNOR(-σ j (2)

[0107] Specifically, such as Figure 10AAs shown, when the state signal σ i When the voltage is -1, zero voltage is applied to the first word line WLa, and the word line voltage V WL Apply to the second word line WLb. When the status signal σ... j When the value is -1, zero voltage is applied to the first bit line BLa, and the bit line voltage V BL Apply to the second bit line BLb. In this case, as... Figure 10A As indicated by the arrow, current is output from the storage cell Mb. For example... Figure 10B As shown, when the state signal σ i When the voltage is -1, zero voltage is applied to the first word line WLa, and the word line voltage V WL Apply to the second word line WLb. When the status signal σ... j When it is +1, the bit line voltage V BL A voltage is applied to the first bit line BLa, and zero voltage is applied to the second bit line BLb. In this case, no current is output from the storage element M. Figure 10C As shown, when the state signal σ i When it is +1, the word line voltage V WL A zero voltage is applied to the first word line WLa, and a zero voltage is applied to the second word line WLb. When the status signal σ... j When the value is -1, zero voltage is applied to the first bit line BLa, and the bit line voltage V BL An application is made to the second bit line BLb. In this case, no current is output from the storage element M. (Example: ...) Figure 10D As shown, when the state signal σ i When it is +1, the word line voltage V WL A zero voltage is applied to the first word line WLa, and a zero voltage is applied to the second word line WLb. When the status signal σ... j When it is +1, the bit line voltage V BL A voltage is applied to the first bit line BLa, and zero voltage is applied to the second bit line BLb. In this case, as... Figure 10D As indicated by the arrow, current is output from storage cell Ma. Status signal σ i and σ j When both are -1, the output current will be equal to the state signal σ. i and σ j The output current when both are +1. This same output current I... Jij It can be represented by equation (3).

[0108]

[0109] In some embodiments, the plurality of idle storage elements M arranged diagonally across the memory array can be used to calculate the external field terms of energy. Exemplary self-multiplication coefficients h1, h2, h3, and h N Shown Figure 3The corresponding storage element M is located in the memory array. In this case, the two storage cells Ma and Mb of each storage element M located on a diagonal of the memory array can perform a logical "AND" operation.

[0110] Specifically, such as Figure 10E As shown, when the state signal σ i When the voltage is -1, zero voltage is applied to the first word line WLa, and the word line voltage V WL Apply to the second word line WLb. When the status signal σ... j When the value is -1, zero voltage is applied to the first bit line BLa, and the bit line voltage V BL An application is made to the second bit line BLb. However, the memory cell Mb has been pre-masked by a high threshold voltage. Therefore, no current is output from the memory element M. Figure 10F As shown, when the state signal σ i When it is +1, the word line voltage V WL A zero voltage is applied to the first word line WLa, and a zero voltage is applied to the second word line WLb. When the status signal σ... j When it is +1, the bit line voltage V BL A voltage is applied to the first bit line BLa, and zero voltage is applied to the second bit line BLb. In this case, as... Figure 10F As indicated by the arrow, current is output from storage cell Ma. This output current I... h It can be represented by equation (4).

[0111]

[0112] In such Figure 5 In the storage element M shown, when the state signal σ i When it is +1, the word line voltage V WL It is applied to the word line and further to the gates of the two transistors. When the status signal σ... i When it is -1, the word line voltage is -V WL It is applied to the word line and further to the gates of the two transistors. When the status signal σ... j When it is +1, the bit line voltage V BL Zero voltage is applied to the first bit line BLa and the second bit line BLb, respectively, and further applied to the drains of the transistors in memory cells Ma and Mb, respectively. When the state signal σ... j When the value is -1, the zero voltage and the bit line voltage V BL The first bit line BLa and the second bit line BLb are applied respectively, and further applied to the drains of the transistors in the memory cells Ma and Mb respectively.

[0113] As described above, each memory element M can couple two state signals σ from the corresponding word line pair WLp and bit line pair BLp. iand σ j It provides a coupled result based on, for example, an encoding strategy using a threshold voltage. Since the spin energy can be calculated in parallel, using a memory array for computation is advantageous.

[0114] like Figure 11 As shown, one of the memory cells in memory element M is sometimes damaged, for example, memory cell Ma. The individuality selection, used to select one of two memory cells to receive two corresponding state signals to calculate the energy value, ensures that at least for some cycles, the calculation is performed using the normal memory cell Mb, and therefore is not affected by the damaged memory cell Ma. Therefore, the threshold voltage or resistance used for calculation can tolerate a large standard deviation. Figure 11 The "flip" between the two cases shown is somewhat analogous to the vibration of atoms at lattice points in a crystal. Details of this operation will be provided in the following paragraphs on the calculation method.

[0115] This disclosure also provides a calculation method. The calculation method calculates an energy value based on multiple state signals and multiple coefficients. The calculation method uses a memory device. The memory device includes a memory array. The memory array consists of multiple memory elements. Each memory element includes two memory cells. The calculation method includes: setting state signals in the memory array, including: performing a complementary read operation to individually select one of the two memory cells of each memory element for receiving two corresponding state signals; and inputting the state signals to the selected memory cell of the memory element, wherein the selected multiple memory cells generate multiple output currents; and calculating the energy value corresponding to the multiple state signals based on a sum of the output currents.

[0116] Figure 12 A flowchart of an exemplary calculation method according to this disclosure is shown.

[0117] In step S1, the mapping coefficients are mapped to the memory array. According to some embodiments, the calculation can focus on energy-related interaction terms. Therefore, the plurality of coefficients are interaction coefficients between grid points. An exemplary interaction coefficient J 12 J 13 J 1N J 21 J 23 J 2N J 31 J 32 J 3N J N1 J N2 and J N3 Shown Figure 3 The corresponding storage element M. For example... Figure 3As shown, the calculation can be performed using memory elements not located on a diagonal of the memory array. For example, two memory cells of each memory element M, not located on a diagonal of the memory array, can perform a logical "XNOR" operation. In some embodiments, the calculation may also include an external field term for energy. The coefficients to be mapped include interaction coefficients and self-multiplication coefficients. Exemplary self-multiplication coefficients h1, h2, h3, and h N Shown Figure 3 The corresponding storage element M. For example... Figure 3 As shown, the calculation of the external field term can be performed by memory elements arranged diagonally on the memory array, whose memory cells can perform logical "AND" operations. Step S1 can be achieved by adjusting the threshold voltage or resistance of the two memory cells of each memory element.

[0118] In step S2, state signals are set in the memory array. For example, a state signal configured at the m-th position can be set in the memory array, where m is a positive integer. The state signal can correspond to the spin of a lattice point selected from +1 and -1. Step S2 includes: performing a complementary read operation to individually select one of two memory cells of each memory element to receive two corresponding state signals; and inputting the state signal to the selected memory cell of the memory element, wherein the selected plurality of memory cells generate a plurality of output currents. According to some embodiments, the complementary read operation may include: toggling a corresponding state signal if a trigger condition is met, such as... Figure 11 As shown. Generally, flipping does not affect the calculation result of a storage element. However, if a storage cell in a storage element is damaged, flipping helps prevent erroneous coupling results. The triggering condition can be expressed by equation (5).

[0119] R∈[0,1]>U (5)

[0120] In equation (5), R is a given random value, and U is a threshold. In some embodiments, U can be 0.5.

[0121] In step S3, based on the sum of the output currents, the energy value of the corresponding state signal is calculated. More specifically, the energy value corresponding to the state signal of the m-th configuration can be calculated. When the sum of the output currents is a serial output current such as... Figure 3 When the output currents are L1, L2, L3, or L4, the energy value corresponds to a local minimum energy. When the sum of the output currents is the output current of the entire memory array, that is, the sum of all serial output currents, the energy value corresponds to the overall minimum energy.

[0122] In step S4, the state signal is updated according to a transfer probability of the energy value. More specifically, if the transfer probability is greater than a predetermined value, the new (m+1)th configuration state signal will replace the original mth configuration state signal. In some embodiments, the transfer probability P can be represented by equation (6).

[0123]

[0124] In equation (6), L i For local spin energy, q i T is a hyperparameter.

[0125] Steps S2 to S4 can be repeated until a predetermined completion condition is met. After the repetition ends, step S5 can be performed. In step S5, the status signal can be observed. That is, the status signal corresponding to the final configuration of the optimal solution can be observed.

[0126] The calculation method according to this disclosure employs a quantum annealing algorithm using the Eisin model. In particular, the calculation method according to this disclosure employs a quantum annealing algorithm using an Eisin model that does not include external field terms. For example, the calculation method according to this disclosure can be applied to… Figure 13 The combinatorial clustering problem of machine learning shown is represented by equation (7).

[0127]

[0128] In equation (7), d represents the distance. When d is large, the state signal s i and s j It tends to use the opposite spin. When d is small, the state signal s i and s j They tend to use the same spin.

[0129] The calculation method according to this disclosure allows for setting the coefficient by adjusting the threshold voltage, for example, using... Figure 4-5 In the case of the storage element shown, it has a higher tolerance for variations in the threshold voltage. The threshold voltage typically follows a distribution pattern with a standard deviation. Please refer to... Figure 14 Compared to Comparative Example CE without complementary readout operation, Example E using the complementary readout operation of this disclosure can increase the acceptable variation of the threshold voltage by up to 60%. Similarly, the calculation method according to this disclosure allows for setting the coefficient by adjusting the resistor, for example using... Figure 6-9 In the case of the storage element shown, it has a higher tolerance for changes in resistance.

[0130] In summary, this disclosure provides a memory device and a computational method using the same, as an optimized implementation of the algorithm.

[0131] While this disclosure has been given above with reference to embodiments, it is not intended to limit the scope of this disclosure. Those skilled in the art to which this disclosure pertains can make various modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.

Claims

1. A memory device, characterized in that, include: A memory array consisting of multiple memory elements, each of which includes two memory cells; Multiple word lines or multiple word line pairs are connected to multiple columns of the memory array; Multiple bit line pairs are connected to multiple rows of the memory array; as well as Multiple common-source lines are connected to the multiple rows of the memory array; The memory device is configured to calculate an energy value based on multiple state signals and multiple coefficients, and the two memory cells of each memory element are configured to perform a selective selection such that one of the two memory cells of each memory element receives two corresponding state signals from a corresponding word line or a corresponding word line pair and a corresponding bit line pair, and generates an output current to a corresponding common source line to calculate the energy value. The individual selection is used to select one of the two storage cells to receive two corresponding state signals to calculate the energy value, which ensures that the calculation is performed using the normal storage cell Mb at least in some cycles, and is therefore not affected by the damaged storage cell Ma.

2. The memory device of claim 1, wherein in each memory element, no two memory cells arranged diagonally on the memory array perform a logical "XNOR" operation.

3. The memory device of claim 1, wherein each memory cell has an adjustable threshold voltage or an adjustable resistance.

4. The memory device of claim 1, wherein each memory cell includes a transistor.

5. The memory device of claim 1, wherein each memory cell includes a transistor and a resistor.

6. The memory device of claim 1, wherein each of the memory elements comprises two transistors of the same type or two transistors of complementary types.

7. The memory device of claim 1, wherein each of the memory cells is a floating-gate memory cell, a charge trapping memory cell, or a ferroelectric field-effect transistor memory cell.

8. The memory device of claim 1, wherein each of the memory cells is a resistive random access memory cell, a bridge random access memory cell, a phase change memory cell, or a magnetoresistive random access memory cell.

9. The memory device of claim 1, wherein one of the two memory cells of each memory element is coupled to a word line or a word line in the corresponding word line pair, a bit line in the corresponding bit line pair, and the corresponding common source line, and the other of the two memory cells of each memory element is coupled to the other word line or the other word line in the corresponding word line pair, the other bit line in the corresponding bit line pair, and the corresponding common source line.

10. A calculation method, wherein the calculation method calculates an energy value based on multiple state signals and multiple coefficients, wherein the calculation method uses a memory device, the memory device comprising a memory array, the memory array comprising multiple memory elements, each memory element comprising two memory cells, and wherein the calculation method comprises: Setting the plurality of status signals in the memory array includes: Perform a complementary read operation to individually select one of the two memory cells of each memory element to receive two corresponding status signals; and The plurality of status signals are input to the plurality of selected memory cells of the plurality of memory elements, wherein the selected plurality of memory cells generate a plurality of output currents; and Based on the sum of the multiple output currents, the energy value corresponding to the multiple state signals is calculated.

11. The calculation method according to claim 10, wherein the complementary read operation includes: If a trigger condition is met, the corresponding state signal is toggled.

12. The calculation method according to claim 11, wherein the triggering condition is expressed by the following formula: Where R is a given random value and U is a threshold.

13. The calculation method according to claim 12, wherein U is 0.

5.

14. The calculation method according to claim 10, further comprising: Prior to the step of setting the plurality of state signals, the plurality of coefficients are mapped to the memory array.

15. The calculation method of claim 14, wherein the mapping of the plurality of coefficients is achieved by adjusting the threshold voltage or resistance of the two memory cells of each memory element.

16. The calculation method according to claim 10, further comprising: After calculating the energy value corresponding to the plurality of state signals, the plurality of state signals are updated according to a transition probability of the energy value.

17. The calculation method according to claim 16, wherein the steps of setting the plurality of state signals, calculating the energy value corresponding to the plurality of state signals, and updating the plurality of state signals are repeated until a predetermined completion condition is met, and the calculation method further includes: After the repetition ends, observe the multiple status signals.

18. The calculation method according to claim 10 employs a quantum annealing algorithm using an Euclidean model that does not include external field terms.

19. The calculation method according to claim 10, wherein the plurality of state signals correspond to the spins of lattice points selected from +1 and -1, and the plurality of coefficients are interaction coefficients between lattice points.

20. The calculation method of claim 10, wherein in each of the storage elements, no two storage cells arranged diagonally on the memory array perform a logical "XNOR" operation.

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