Differential resistance change memory chip and control method thereof

Abstract

The application provides a differential resistance change memory chip and a control method thereof. The chip comprises a memory cell array composed of a plurality of 2T2R differential resistance change memory cells, a controller, a read circuit and a write circuit. The controller comprises an algorithm state machine, a selected side decoder, a mask encoder, a mask buffer and a write driver enable decoder. The algorithm state machine is used for setting a resistance state change type and controlling the operation of the selected side decoder, the mask encoder and the write driver enable decoder. The resistance state change type indicates the resistance state change direction of a resistance change device. The selected side decoder is used for indicating the resistance change device on the selected side connected to the read circuit and the write circuit. The mask encoder is used for generating mask information. While considering reliability and reducing the cost caused by the increase of the peripheral circuit area, the resistance change devices distributed on different sides of the plurality of 2T2R differential resistance change memory cells can simultaneously perform the same type of resistance state change, and the resistance state change can be continuously performed, so that the efficiency is high.

Description

Technical Field

[0001] This application relates to the field of resistive variable memory technology, and in particular to a differential resistive variable memory chip and its control method. Background Technology

[0002] A non-volatile RRAM (resistive random access memory) is composed of 2T2R differential resistive variable memory cells. Each 2T2R differential resistive variable memory cell contains two RRAMs (resistive variable devices) with different resistance states: one with higher resistance and the other with lower resistance. When rewriting data, the high-resistance RRAM needs to be rewritten to the low-resistance state, and the low-resistance RRAM needs to be rewritten to the high-resistance state. The operating voltages required to change the two resistance states are different.

[0003] Regarding the two resistance state changes, there are two operating voltage application schemes in related technologies. One scheme forces the use of the same operating voltage, which, while ensuring high voltage application efficiency, deviates from the appropriate operating conditions required by RRAM, leading to memory reliability loss, reduced bit line reuse rate, reduced memory density, and increased peripheral circuit area, rendering it impractical. The other scheme applies corresponding operating voltages to the two different resistance state changes simultaneously, resulting in word lines and bit lines that cannot be shared, leading to even lower memory array density and a larger peripheral circuit area, thus losing its practical value. Therefore, there is a need to provide a technical solution that ensures voltage application efficiency during memory write operations without sacrificing memory reliability and with minimal increase in peripheral circuit area. Summary of the Invention

[0004] This application provides a differential resistive variable memory chip and its control method to ensure the voltage application efficiency of the memory's write operation process without sacrificing memory reliability and with minimal increase in peripheral circuit area. The technical solution of this application is as follows: In a first aspect, embodiments of this application provide a differential resistive switching memory chip, including a memory cell array composed of multiple 2T2R differential resistive switching memory cells, a controller, a read circuit and a write circuit, wherein each 2T2R differential resistive switching memory cell includes two resistive switching devices. The controller includes an algorithm state machine, a selected-side decoder, a mask encoder, a mask buffer, and a write driver enable decoder. The algorithm state machine controls the operation of the selected-side decoder, the mask encoder, and the write driver enable decoder. The algorithm state machine is used to set the current resistance state change type; wherein, the resistance state change type indicates the resistance state change direction of the resistive switching device. The selected-side decoder generates a selection indication signal based on the current resistance state change type output by the algorithm state machine and the data to be written. The selection indication signal is used to indicate the bit lines of the read circuit and the write circuit connected to the first target resistive switching device, so as to ensure that only the resistive switching devices in the 2T2R differential resistive switching memory cell that need to change their resistance state are read during the verification read process, and that the resistive switching devices in the 2T2R differential resistive switching memory cell that need to change their resistance state are applied an operation voltage during the application of the write operation voltage; wherein, the first target resistive switching device is the selected-side resistive switching device in the multiple 2T2R differential resistive switching memory cells corresponding to the current word that needs to change its resistance state. The mask encoder is used to generate mask information based on the current resistance state change type output by the algorithm state machine and the data read from the first target resistive switching device by the read circuit. The mask information is used to indicate the second target resistive switching device in the first target resistive switching device that requires the application of an operating voltage. The mask buffer is used to store the mask information generated by the mask encoder; The write driver enable decoder is used to decode the mask information read by the algorithm state machine control, and generate a write driver enable signal to enable the write circuit.

[0005] In some embodiments, the read circuit includes multiple inductive amplifier units, each of which is connected to a 2T2R differential resistive switching memory cell via a first selector unit. The first selector unit is electrically connected to the selected-side decoder to connect the resistive switching device on the selected side of the 2T2R differential resistive switching memory cell and the corresponding inductive amplifier unit according to the selection indication signal.

[0006] In some embodiments, the write circuit includes multiple write drive units, each of which is connected to one of the 2T2R differential resistive switching memory cells via a second selector unit. The second selector unit is electrically connected to the selected-side decoder to connect the resistive switching device on the selected side of the 2T2R differential resistive switching memory cell and the corresponding write drive unit according to the selection indication signal.

[0007] In some implementations, the read circuit, write circuit, mask encoder, mask buffer, and write drive enable decoder all implement time-division multiplexing of signals during different impedance state change stages.

[0008] In some embodiments, the resistance state change type includes rewriting the resistance state of the resistive switching device from a high resistance state to a low resistance state, and rewriting the resistance state of the resistive switching device from a low resistance state to a high resistance state.

[0009] In some implementations, the algorithm state machine is also used to set the address space for continuous reading and writing of the storage cell array according to the data to be written.

[0010] Secondly, embodiments of this application provide a control method for a differential resistive variable memory chip, the method comprising: Set the current resistance state change type, and establish the operation conditions for verification reading and set the reference current for verification reading based on the current resistance state change type; A verification reading step is performed to determine whether there is a second target resistive switching device in the first target resistive switching device whose resistive state is not the desired resistive state; wherein, the first target resistive switching device is determined by the selection indication signal, and the second target resistive switching device is a resistive switching device in the first target resistive switching device whose resistive state is not the desired resistive state, and the second target resistive switching device is determined by the mask information; When there is a second target resistive switching device in the first target resistive switching device whose resistive state is not the desired resistive state, a write operation voltage is applied to the second target resistive switching device, and the verification read step and subsequent steps are repeated until the resistive state of the second target resistive switching device is the desired resistive state or the number of times the write operation voltage is applied reaches the preset maximum number of times the write operation voltage is applied. Change the current resistance state change type, return to the first step to execute, until the resistance state of the first target resistive switching device corresponding to the changed current resistance state change type is the desired resistance state or the number of times the write operation voltage is applied reaches the preset maximum number of times the write operation voltage is applied, then terminate this process.

[0011] In some implementations, the verification read step is a continuous read operation based on the address space corresponding to the data to be written; and the application of a write operation voltage to the second target resistive switching device is a continuous write operation based on the address space corresponding to the data to be written.

[0012] In some implementations, setting the current resistance state change type includes: The current resistance change type is set by setting the value of the resistance change counter.

[0013] In some implementations, the verification read step includes: The control timing generator generates a read control timing sequence to read the data from the first target resistive switching device; and Applying a write operation voltage to the second target resistive switching device includes: A timing generator is used to generate write control timing, which controls the application of write operation voltage to the second target resistive switching device.

[0014] The technical solution provided in this application has at least the following beneficial effects: While balancing reliability and reducing the overhead caused by increased peripheral circuit area, it enables resistive switching devices distributed on different sides of multiple 2T2R differential resistive switching memory cells to simultaneously perform the same type of resistance state change, and the resistance state change can be performed continuously with high efficiency. At the same time, the reduced power supply operating time of the RRAM memory also effectively reduces write power consumption.

[0015] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application, and do not constitute an undue limitation of this application.

[0017] Figure 1 This is a schematic diagram of the structure of a 2T2R differential resistive variable memory cell according to an embodiment of this application.

[0018] Figure 2 This is a schematic diagram of the structure of some components of a differential resistive variable memory chip according to an embodiment of this application.

[0019] Figure 3 This is an example diagram of an encoding method for a 2T2R differential resistive variable memory cell according to an embodiment of this application.

[0020] Figure 4 This is a schematic diagram of the reference current in an embodiment of this application.

[0021] Figure 5 This is a schematic diagram illustrating the connection between a portion of the read circuit and the memory cell array in an embodiment of this application.

[0022] Figure 6 This is a schematic diagram illustrating the connection between a portion of the write circuit and the memory cell array in an embodiment of this application.

[0023] Figure 7 This is a flowchart of a control method for a differential resistive variable memory chip according to an embodiment of this application.

[0024] Figure 8 This is a block diagram illustrating an electronic device according to an exemplary embodiment. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0026] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0027] like Figure 1 , Figure 2 As shown, this application provides a differential resistive variable memory chip, such as... Figure 2 As shown, the differential resistive variable memory chip includes a memory cell array composed of multiple 2T2R differential resistive variable memory cells (also known as 2T2R differential RRAM cells), a controller, a read circuit, and a write circuit.

[0028] like Figure 1 As shown, each of the 2T2R differential resistive switching memory cells includes two resistive switching devices. In this embodiment, the two resistive switching devices are defined as "left RRAM" and "right RRAM", respectively, and each resistive switching device corresponds to a selector transistor. WL (Word Line) is the word line, connected to the gate of the selector transistor; SL (source line) is the first bit line, connected to the source of the selector transistor; BL (bit line) is the second bit line, connected to the drain of the selector transistor. Figure 1 The meanings of the other signal names in the table are as follows: Table 1:

[0029] The resistance state of a resistive switching device is defined as follows: when the resistance of the resistive switching device is greater than a preset high resistance threshold, the current resistance state is defined as high resistance (HR); when the resistance of the resistive switching device is lower than a preset low resistance threshold, the current resistance state is defined as low resistance (LR). The resistance information of the resistive switching device can be read using a current sensing amplifier; the resistance information is represented by the current flowing through the resistive switching device.

[0030] It should be noted that the data encoding method of the 2T2R differential RRAM cell is as follows: The different resistance states of the two RRAMs in the 2T2R differential RRAM cell are used to represent logic 1 and logic 0, defining one resistance state as logic 1 and the other as logic 0. Figure 3 illustrates one encoding method. In the encoding method shown in Figure 2, when the left RRAM is HR and the right RRAM is LR, it is defined as data 0; conversely, when the left RRAM is LR and the right RRAM is HR, it is defined as data 1. See Table 2 for details.

[0031] Table 2:

[0032] It should be noted that another encoding method is used where, if the left RRAM is LR and the right RRAM is HR, it is defined as data 0; conversely, if the left RRAM is HR and the right RRAM is LR, it is defined as data 1. This application does not limit the specific encoding method used. For the sake of simplicity, the following explanation uses the encoding method shown in Table 2 as an example to illustrate the operation of the 2T2R differential RRAM cell.

[0033] It should be noted that, Figure 2 This only shows a portion of the memory cell array, which contains n word lines (WL), with each word line displaying only one word, and each word being i bits; in practice, each word line can have k words. Figure 2 also illustrates other peripheral circuitry of the memory cell array, such as word line decoders, word line drivers, bit line (BL, SL) decoders, data buffers, timing generators, on-chip power supplies, etc. These peripheral circuitry units are all existing technologies and will not be described in detail here. The controller for the differential resistor variable memory chip according to the embodiments of this application will be further described below.

[0034] The following section introduces the read / write working principle of the resistive switching device in the 2T2R differential resistive switching memory cell of this application embodiment.

[0035] By performing a verification read, it is determined whether the two resistive switching devices in the 2T2R differential resistive switching memory cell have reached the resistance state defined in the preset data encoding scheme. If not, it indicates that the write operation has not been successful. The operation voltage pulse is applied again, and the verification read is repeated to determine the result of the write operation.

[0036] It should be noted that the normal data reading method for a 2T2R differential resistive variable memory cell is differential reading. During differential reading, the controller operates the read circuit, applying a read voltage to the resistive devices (left RRAM and right RRAM) of the addressed word. The current through the left RRAM of bit i is defined as Icell_L[i], and the current through the right RRAM of bit i is defined as Icell_R[i]. The read circuit is responsible for converting the relationship between the magnitudes of the Icell_L[i] and Icell_R[i] currents into logic 0 and logic 1 levels, respectively, to read the data. Taking the encoding method shown in Table 2 as an example, when the resistance of the left RRAM is higher than that of the right RRAM, the current Icell_L[i] is less than the current Icell_R[i], and the data read by the read circuit is 0; when the resistance of the left RRAM is lower than that of the right RRAM, the current Icell_L[i] is greater than the current Icell_R[i], and the data read by the read circuit is 1.

[0037] To ensure the speed and accuracy of current comparison in the read circuit, and considering that Icell_L and Icell_R may change due to degradation of resistive switching devices caused by aging, irradiation, etc., Icell_L and Icell_R should have a larger window, that is, the resistance difference between the two resistive switching devices in the 2T2R differential resistive switching memory cell needs to be large enough; at the same time, during the write operation, to avoid erroneous write operation and overset and overreset when the data to be written is the same as the data stored in the memory cell array, a verification read mechanism is introduced accordingly.

[0038] Unlike differential read mechanisms, during check reads, such as Figure 4 The read circuit compares the current of the left or right RRAM with the reference current (low-resistance reference current or high-resistance reference current) to determine whether the left or right RRAM has reached the target resistance state. When the read current is greater than the reference current, the read circuit outputs a value of 1; when the read current is less than the reference current, the output value is 0.

[0039] When a 1 in the memory cell array is overwritten as a 0, both RRAMs in the 2T2R differential resistive variable memory cell need to change their resistance states. For example, according to the encoding scheme shown in Figure 2, the left RRAM is expected to change from the LR state to the HR state, and the right RRAM is expected to change from the HR state to the LR state. It should be noted that the data 1 here is different from the data 1 in differential reads. A data 1 in differential reads indicates that the data stored in the 2T2R differential resistive variable memory cell is 1. However, for a check read, a data 1 indicates whether the left or right RRAM in the 2T2R differential resistive variable memory cell has reached the target resistance state (also called the desired resistance state).

[0040] When an RRAM in HR state is rewritten to LR state, the reference current is set to the low-resistance reference current corresponding to LR state (denoted as Iref_LR). If the read data is 0, it means that the current resistance value of the RRAM is higher than the resistance threshold of LR state. The RRAM needs to apply the corresponding LR write operation voltage in the subsequent write operation. After applying the LR write operation voltage, the read is checked to see if the read data has become 1, that is, whether the resistance state of the RRAM has changed to LR state. If it has not become 1, the step of checking the read after applying the LR write operation voltage is repeated until the read data becomes 1 or the maximum number of times the LR write operation voltage can be applied is reached by the controller.

[0041] When an RRAM in the LR state is rewritten to the HR state, the reference current is set to the high-resistance reference current corresponding to the HR state (denoted as Iref_HR). A read data of 1 indicates that the current resistance of the RRAM is lower than the resistance threshold of the HR state. The RRAM needs to have an HR write operation voltage applied in subsequent write operations. After applying the HR write operation voltage, a check read is performed to determine if the read data has become 0, i.e., whether the resistance state has changed to the HR state. If it has not become 0, the check read process after applying the HR write operation voltage is repeated until the read data becomes 0 or the maximum number of times the HR write operation voltage can be applied is reached by the controller. This method of determining whether to apply a write operation voltage based on the result of the check read is called a check write.

[0042] Through the above verification write mechanism, after the write operation is completed, the two RRAMs in the 2T2R differential resistor variable memory cell reach the preset resistance range respectively. During differential read, the window between Icell_L and Icell_R is large enough to meet the requirements of read speed and correctness after aging.

[0043] like Figure 2 As shown, the controller (also known as the RRAM controller) includes an algorithm state machine, a selected-side decoder, a mask encoder, a mask buffer, and a write driver enable decoder. The algorithm state machine is used to set the current resistance state change type and continuously read and write the address space of the memory cell array, as well as control the operation of the selected-side decoder, the mask encoder, and the write driver enable decoder. The resistance state change type indicates the direction of resistance state change of the resistive switching device. The algorithm state machine is electrically connected to the selected-side decoder, the mask encoder, and the write driver enable decoder, and all three operate according to the control instructions of the algorithm state machine.

[0044] In this embodiment, the resistance state change type includes rewriting the resistance state of the resistive switching device from a high resistance state (HR) to a low resistance state (LR), and rewriting the resistance state of the resistive switching device from a low resistance state to a high resistance state.

[0045] In other words, the algorithm state machine controls whether the current resistance state change is from high resistance to low resistance or from low resistance to high resistance, and outputs the current resistance state change type to the selected side decoder, the mask encoder, and the write driver enable decoder it controls. As the control center, the algorithm state machine understands the operating state of all other components connected to it to coordinate the transmission of information between them.

[0046] In this embodiment, the resistance state change type is defined as follows: if the current state is LR and it is expected to be rewritten as HR, it is called HR write; if the current state is HR and it is expected to be rewritten as LR, it is called LR write.

[0047] This can be understood as follows: by defining the current resistance state change type, based on the current resistance state change type and the data to be written, multiple left RRAMs and multiple right RRAMs in multiple 2T2R differential resistor variable memory cells corresponding to the current word in the memory cell array can be selected to undergo the same type of resistance state change simultaneously. This enables a technical solution to simultaneously perform one type of resistance state change in multiple 2T2R differential resistor variable memory cells.

[0048] As one possible implementation, the algorithm state machine is also used to establish the operation conditions for verification read, set the reference current for verification read, and establish the operation voltage for write operation based on the current resistance state change type.

[0049] This can be understood as follows: the operating conditions for verification read, the reference current for verification read, and the operating voltage for write operation are different for different types of resistance state changes. Therefore, for the current type of resistance state change, it is necessary to establish the corresponding verification read operating conditions, the corresponding reference current, and the corresponding write operation operating voltage.

[0050] In this embodiment, the algorithm state machine is also used to set the address space for continuous reading and writing of the storage cell array according to the data to be written.

[0051] This can be understood as the algorithm's state machine setting the starting address, and then using address incrementing to perform continuous read or write operations during the reading and writing of memory units.

[0052] Specifically, the selected side decoder is used to generate a selection indication signal based on the current resistance state change type and the data to be written output by the algorithm state machine. The selection indication signal is used to indicate the bit line of the read circuit and the write circuit connected to the first target resistive switching device, so as to ensure that only the resistive switching devices in the 2T2R differential resistive switching memory cell that need to change their resistance state are read during the verification read process, and that the resistive switching devices in the 2T2R differential resistive switching memory cell that need to change their resistance state are applied an operation voltage during the application of the write operation voltage. The first target resistive switching device is the selected side of the multiple 2T2R differential resistive switching memory cells corresponding to the current word, which needs to change its resistive state.

[0053] This can be understood as determining which side of each 2T2R differential resistive switching memory cell should be selected based on the current resistive state change type and the data to be written, i.e., the left-side resistive switching device or the right-side resistive switching device.

[0054] As an example, the selected side decoder decodes and generates a selection indicator signal MC_LEFT[i-1:0] (where i is the word width) indicating the selected side resistive variable device in the 2T2R differential resistive variable memory cell. During a read operation, this selection indicator signal directs the bit line connected to the first target resistive variable device and the read circuit, allowing the first target resistive variable device to be read under read timing control. When a write operation voltage is applied, it directs the bit line connected to the first target resistive variable device and the write circuit, outputting the voltage line for the resistive variable device write voltage, enabling the write operation on the first target resistive variable device under write timing control.

[0055] Read the selected resistive switching device (i.e., the first target resistive switching device) in the 2T2R differential resistive switching memory cell corresponding to the current address word. The current resistive state of the selected resistive switching device in the currently addressed 2T2R differential resistive switching memory cell can be known by reading the data.

[0056] In other words, the reading circuit determines whether the resistance state of the selected first target resistive switching device is consistent with the target resistance state of the current resistance state change type. If they are consistent, the resistive switching device does not need to change its resistance state; otherwise, a write operation voltage needs to be applied to change the resistance state.

[0057] The mask encoder is used to generate mask information based on the current resistance state change type output by the algorithm state machine and the data read from the first target resistive switching device by the read circuit. The mask information is used to indicate the second target resistive switching device in the first target resistive switching device that requires the application of an operating voltage.

[0058] In other words, the mask encoder is used to determine whether the first target resistive switching device needs to undergo a resistance state change based on the current resistance state change type output by the algorithm state machine and the data read from the first target resistive switching device by the read circuit, and generates mask information. The mask information is used to indicate whether the first target resistive switching device needs to be subjected to an operating voltage.

[0059] As an example, the mask encoder decoder identifies whether the first target resistive switching device selected by the selected side decoder output selection indication signal CO_LEFT[i:0] needs to be applied a write operation voltage. The information of whether a write operation voltage needs to be applied is encoded as a mask.

[0060] When performing HR write, according to the encoding scheme shown in Table 2, after decoding by the selected side decoder, the left RRAM in the 2T2R differential resistor variable memory cell of the addressable word (i.e., the current word) in the memory cell array corresponding to the bit to be written with data of 0 is selected, and at the same time, the right RRAM in the 2T2R differential resistor variable memory cell of the addressable word in the memory cell array corresponding to the bit to be written with data of 1 is selected. This is to detect whether the resistance state of the simultaneously selected left RRAM and right RRAM is HR. If the resistance state is not HR, it is marked that the bit needs to be applied with an operating voltage. When performing an LR write, according to the encoding scheme shown in Table 2, after decoding by the selected side decoder, the right RRAM in the 2T2R differential resistor variable memory cell of the addressable word in the memory cell array corresponding to the bit to be written with data of 0 is selected, and at the same time, the left RRAM in the 2T2R differential resistor variable memory cell of the addressable word in the memory cell array corresponding to the bit to be written with data of 1 is selected. This is to detect whether the resistance state of the simultaneously selected left and right RRAMs is LR. If their resistance state is not LR, it is marked that an operating voltage needs to be applied to that bit.

[0061] The mask buffer is used to store the mask information generated by the mask encoder.

[0062] This can be understood as the mask information generated by the mask encoder being written into the mask buffer for caching under the control of the algorithm state machine.

[0063] The write driver enable decoder is used to decode the mask information read by the algorithm state machine control, and generate a write driver enable signal to enable the write circuit.

[0064] As an example, the write driver enable decoder decodes the enable signals of i write driver cells in the write circuit.

[0065] This embodiment can be understood as follows: in order to balance reliability and reduce the overhead caused by the increase in peripheral circuit area, only one type of resistance state change can be performed at a time. However, since this embodiment can identify the same type of resistance state change distributed on different sides (which, from the perspective of encoding, are different 0s and 1s) within multiple 2T2R differential RRAM cells, it does not affect the write speed and can be performed continuously, thus improving the write speed.

[0066] Compared to existing calculation schemes that can only apply operating voltage to one side of the resistive switching device (either the left or right side) in a single resistance state change type, this embodiment can achieve efficient application of operating voltage during write operations of the 2T2R differential resistive switching memory cell while ensuring the reliability of the RRAM memory. This significantly improves write speed when writing random data. Furthermore, the peripheral circuits of the memory cell array can be time-division multiplexed for different resistance state change types and when writing data 0 or 1. This multiple time-division multiplexing further reduces area overhead, effectively improving memory density and the efficient utilization of memory chip area.

[0067] The differential resistive switching memory chip of this application embodiment, while balancing reliability and reducing the overhead caused by the increase in peripheral circuit area, enables resistive switching devices distributed on different sides of multiple 2T2R differential resistive switching memory cells to simultaneously perform the same type of resistive state change, ensuring the write speed of the memory cells, and the resistive state change can be performed continuously, resulting in high efficiency. Simultaneously, the reduced power supply operating time for the RRAM memory also effectively reduces write power consumption. Furthermore, the mask information does not distinguish between the selected side, simplifying the mask and thus reducing the chip area occupied by the mask buffer. In addition, the select transistor in the 2T2R differential resistive switching memory cell is a low-voltage MOS device, which will generate overvoltage on the select transistor during voltage application. Improving the voltage application efficiency can reduce the overvoltage time of the select transistor's gate, thereby slowing down the aging rate of the memory cell array.

[0068] In some embodiments, such as Figure 5 As shown, the read circuit includes multiple sense amplifier units (SA). Each sense amplifier unit is connected to a 2T2R differential resistive variable memory cell through a first selector unit. The first selector unit is electrically connected to the selected-side decoder to connect the resistive variable device on the selected side of the 2T2R differential resistive variable memory cell and the corresponding sense amplifier unit according to the selection indication signal.

[0069] It should be noted that the structure shown in Figure 5 is a part of the read circuit shown in Figure 2, and illustrates the connection relationship between the read circuit and the current addressed word corresponding to the memory cell array. The BL / SL decoder and column selection circuit are not shown here. As an example, the read circuit contains i sense amplifier units, matching the i-bit word width of the memory cell array shown in Figure 2. During verification reads, the resistive switching device on the selected side is connected to the current sense amplifier via a bit line.

[0070] As an example, the sensing amplifier unit is a current sensing amplifier unit, and the first selector unit is a 2-to-1 multiplexer (i.e., Figure 5 (2_to_1_MUX in the middle).

[0071] In this embodiment, a two-way multiplexer is implemented by adding only a selector unit that performs a two-to-one function. With very little additional circuit area overhead, the selected side resistive switching device is connected through an inductive amplifier unit, and the current value of the selected side resistive switching device is read. By comparing the read current value with the corresponding reference current, the above-mentioned verification reading mechanism is realized.

[0072] In some embodiments, such as Figure 6 As shown, the write circuit includes multiple write driver units (WDs). Each write driver unit is connected to one of the 2T2R differential resistive switching memory cells via a second selector unit. The second selector unit is electrically connected to the selected-side decoder to connect the selected-side resistive switching device and the corresponding write driver unit in the 2T2R differential resistive switching memory cell according to the selection indication signal. The column decoder is not shown.

[0073] It should be noted that the structure shown in Figure 6 is a part of the write circuit shown in Figure 2, and illustrates the connection relationship between the write circuit and the current address word corresponding to the memory cell array. The BL / SL decoder and column selection circuit are not shown here. As an example, the write circuit contains i write driver units, and... Figure 2 The word widths of the i-bits in the shown memory cell array are matched. During a write operation, the resistive switching device on the selected side is connected to the voltage line of the write circuit output write voltage via the bit line.

[0074] As an example, the second selector unit is a 2-to-1 multiplexer (i.e., Figure 6 (2_to_1_MUX in the middle).

[0075] In this embodiment, a two-way multiplexer is implemented by adding only a selector unit that performs a two-to-one function. With very small circuit area overhead, the resistive switching device on the selected side is connected through a write drive unit. When the write operation is applied, the resistive switching device on the selected side is connected to the voltage line of the write circuit output write voltage through the bit line to realize the write operation.

[0076] In some implementations, the read circuit, write circuit, mask encoder, mask buffer, and write driver enable decoder all implement time-division multiplexing of signals.

[0077] In other words, the read circuit, write circuit, mask encoder, mask buffer, and write driver enable decoder can all be time-division multiplexed at different impedance state change stages.

[0078] In some implementations, the chip includes a data buffer, and the selected-side decoder reads the data to be written from the data buffer according to the control instructions of the algorithm state machine.

[0079] As an example, in practical implementation, Figure 2 Table 3 shows the functional descriptions of some modules or components of the differential resistive variable memory chip.

[0080] Table 3:

[0081] Figure 2 The relevant controls are shown in Table 4.

[0082] Table 4:

[0083] Based on the above embodiments, Figure 7 This is a flowchart of a write operation control method for a differential resistive variable memory chip according to an embodiment of this application. Figure 7 As shown, the write operation control method of the differential resistor variable memory chip may include steps S701-S706.

[0084] In step S701, the current resistance state change type is set, and the operation conditions for verification reading and the reference current for verification reading are established according to the current resistance state change type.

[0085] This can be understood as follows: before implementing the verification read mechanism, initialization is required. This involves setting the current resistance state change type via an algorithm state machine, such as whether to perform an HR write first or an LR write first. Furthermore, the operational conditions for the verification read and the reference current for the verification read need to be established based on the current resistance state change type.

[0086] It should also be noted that the resistance state change type involved in the control method of this application does not limit the order of HR writing and LR writing. HR writing or LR writing can be subdivided into multiple sub-stages, and each sub-stage can use different timing sequences and different operating voltages.

[0087] As one possible implementation, the current resistance change type can be set by setting the value of the resistance change counter.

[0088] In step S702, a verification reading step is performed to determine whether there is a second target resistive switching device in the first target resistive switching device whose resistive state is not the desired resistive state; wherein, the first target resistive switching device is determined by the selection indication signal, the second target resistive switching device is a resistive switching device in the first target resistive switching device whose resistive state is not the desired resistive state, and the second target resistive switching device is determined by the mask information.

[0089] A selection indication signal is generated by the selected side decoder, so as to instruct the read circuit to connect to the selected side resistive switching device (i.e., the first target resistive switching device) in the 2T2R differential resistive switching memory cell corresponding to the current word.

[0090] According to the control instructions issued by the algorithm state machine, the selected side decoder is controlled to generate a selection indication signal, so as to determine the first target resistive switching device based on the selection indication signal, and read the data of the first target resistive switching device through the read circuit.

[0091] In specific implementation, the verification reading steps include: controlling the timing generator to generate the read control timing, and reading the data of the first target resistive switching device.

[0092] The mask encoder, based on the current resistance state change type output by the algorithm state machine and the data read from the first target resistive switching device by the read circuit, determines whether the resistive switching device on the selected side of the 2T2R differential resistive switching memory cell corresponding to the current word needs to undergo a resistance state change (i.e., determining the second target resistive switching device), generates mask information, and saves it. The data read by the read circuit from the resistive switching device on the selected side of the 2T2R differential resistive switching memory cell corresponding to the current word is the current resistance state.

[0093] This can be understood as controlling the mask encoder to generate mask information based on the control instructions issued by the algorithm state machine, so as to determine the resistive switching device that needs to change its resistive state based on the mask information.

[0094] In step S703, when there is a second target resistive switching device in the first target resistive switching device whose resistive state is not the desired resistive state, a write operation voltage is applied to the second target resistive switching device, and the verification read step and subsequent steps are repeated until the resistive state of the second target resistive switching device is the desired resistive state or the number of times the write operation voltage is applied reaches the preset maximum number of times the write operation voltage is applied.

[0095] A selection indication signal is generated to instruct the write circuit to connect to the first target resistive switching device.

[0096] The write driver enable decoder decodes the mask information to generate a write driver enable signal for enabling the write circuit, and controls the application of an operating voltage pulse to the resistive switching device indicated by the mask information that requires an operating voltage, so as to change the resistance state of the corresponding resistive switching device.

[0097] This can be understood as follows: after determining the resistive switching device whose resistance state needs to be changed, it is necessary to connect the resistive switching device whose resistance state needs to be changed and the writing circuit, and realize the connection between the writing circuit and the first target resistive switching device according to the selection indication signal.

[0098] In specific implementation, when controlling the application of an operating voltage pulse to the second target resistive switching device indicated by the mask information as requiring an operating voltage, the process includes: generating a write control timing sequence through a timing generator, and controlling the bit line and word line corresponding to the current word to apply an operating voltage pulse to the second target resistive switching device indicated by the mask information as requiring an operating voltage.

[0099] This can be understood as performing a verification read to check whether the resistance state change of the resistive switching device was successful, i.e., whether the data was successfully written. If the resistance state change is determined to have failed, the write operation process continues until the resistance state change is successful or the number of voltage applications reaches a preset limit (i.e., the preset maximum number of write operation voltage applications).

[0100] In this embodiment, the verification read step is a continuous read operation implemented according to the address space corresponding to the data to be written; and the application of the write operation voltage to the second target resistive switching device is a continuous write operation implemented according to the address space corresponding to the data to be written.

[0101] In step S704, the current resistance state change type is changed, and the process returns to the first step until the resistance state of the first target resistive switching device corresponding to the changed current resistance state change type is the desired resistance state or the number of times the write operation voltage is applied reaches the preset maximum number of times the write operation voltage is applied, and then the process is terminated.

[0102] This can be understood as follows: after completing the current resistance state change type, such as completing the HR write, it is also necessary to complete the LR write. Therefore, it is necessary to change the current resistance state change type to another resistance state change type and continue the above steps to finally complete the write operation of the two resistance state change types, that is, to complete the verification write mechanism of the two resistance state change types.

[0103] The write operation control method of this application embodiment, while balancing reliability and reducing the overhead caused by the increase in peripheral circuit area, enables resistive switching devices distributed on different sides of multiple 2T2R differential resistive switching memory cells to simultaneously perform the same type of resistive state change, thus ensuring write speed and continuous resistive state change, resulting in high efficiency. Simultaneously, the reduced power supply operating time for the RRAM memory also effectively lowers write power consumption.

[0104] Figure 8 This is a flowchart illustrating a write operation control method for a differential resistive variable memory chip according to a specific example of this application. For example... Figure 8 As shown, the write operation control method of this differential resistive variable memory chip, namely the verification write process, may include the following steps.

[0105] In step S801, the values ​​of the resistance state change counter and the number of voltage applications are initialized. The resistance state change counter indicates the current resistance state change type, and the number of voltage applications indicates the number of times the write operation voltage is currently applied.

[0106] In this embodiment of the application, a resistance state change counter (RS_C) is set and defined as shown in Table 5 below.

[0107] Table 5:

[0108] It should be noted that, in specific implementation, it can be implemented according to either Definition 1 or Definition 2, and no restriction is imposed here. Furthermore, the embodiments of this application do not restrict whether the first resistive state change is an HR write or an LR write, that is, the order of HR write and LR write is not limited.

[0109] It should be noted that the voltage application count parameter is used to record the number of voltage applications. The voltage application count is used by RS_C to indicate the number of times a write operation voltage is applied during the resistance state change phase corresponding to different resistance state change types. During initialization, the voltage application count value is cleared to 0. Each time an operation voltage is applied (referred to as voltage application), this voltage application count parameter is incremented by 1. When a read check is performed, if the voltage application count reaches the maximum (i.e., the upper limit of the voltage application count) and there are still RRAMs that have not been successfully written, then the resistance state change of the current resistance state change type will not continue, and voltage application will cease. Furthermore, when RS_C indicates a new resistance state change type, the voltage application count is cleared to 0; that is, after changing the current resistance state change type, the voltage application count restarts from 0.

[0110] It should also be noted that the embodiments of this application do not limit the first impedance state change to HR write or LR write. Furthermore, the embodiments of this application do not limit the specific impedance state change tracking control method; a configuration table can be used to configure the number of impedance state change types and the sequence of types for each impedance state change. This method can achieve better scalability, and HR and LR impedance state changes can extend to their sub-impedance state change types. The word line and bit line operating voltages that may be required for reading and writing are not detailed in the embodiments of this application, but are summarized as "operating conditions".

[0111] In step S802, the starting address is set.

[0112] In step S803, the value of the counter is changed according to the resistance state to establish the verification read conditions and set the verification read reference current.

[0113] This can be understood as the verification read conditions and verification read reference current being different for HR write and LR write. Therefore, before performing a verification read, the verification read conditions and verification read reference current need to be set according to the current resistance state change type (HR write or LR write).

[0114] As an example, when the current resistance state change type is HR write, the operation condition for HR verification read is established, and the reference current is set to the high resistance state reference current; when the current resistance state change type is LR write, the operation condition for LR verification read is established, and the reference current is set to the low resistance state reference current.

[0115] In step S804, the data to be written is read.

[0116] One possible implementation is to read cached data to be written from the data cache.

[0117] In step S805, the selected-side decoder is controlled to generate an i-bit selection indication signal MC_LEFT[i-1:0] for the current word, which connects the bit line of the selected-side resistive converter and the read circuit.

[0118] In this embodiment, the selected-side decoder is controlled by an algorithm state machine to generate an i-bit selection indication signal MC_LEFT[i-1:0] for the current word, which connects the bit line of the selected-side resistive converter and the read circuit.

[0119] In step S806, the control generates a read control timing sequence to read the data of the selected side resistive switching device in the 2T2R differential resistive switching memory cell of the addressed word in the memory cell array.

[0120] As an example, when the current resistance state changes to HR for writing, the selected side decoder generates a selection indication signal MC_LEFT[i-1:0]. According to the encoding scheme shown in Table 2, the left RRAM corresponding to the same bit in the currently addressed memory cell array corresponding to the bit of the currently written word that is 0 is selected, and the right RRAM corresponding to the same bit in the currently addressed memory cell array corresponding to the bit of the currently written word that is 1 is selected. All resistive switching devices in the current word whose resistance state is expected to change to HR are read and subsequently encoded into mask information by the mask encoder. In other words, all resistive switching devices in the current word whose resistance state is expected to change to HR are read and subsequently encoded into mask information by the mask encoder.

[0121] When the current resistance state changes to LR for writing, the selected side decoder generates a selection indication signal MC_LEFT[i-1:0]. According to the encoding scheme shown in Table 2, the RRAM to the right of the same bit in the currently addressed memory cell array corresponding to the bit of the currently written word that is 0 is selected, and the RRAM to the left of the same bit in the currently addressed memory cell array corresponding to the bit of the currently written word that is 1 is selected. That is, all resistive devices in the current word whose resistance state is expected to change to LR are read and subsequently encoded into mask information by the mask encoder. The read circuit, mask encoder, and mask buffer of the memory cell array can all be time-division multiplexed at different resistance state change stages.

[0122] In step S807, the mask encoder is controlled to generate mask information and write the mask information into the mask buffer.

[0123] This can be understood as follows: when a resistive switching device in a 2T2R differential resistive switching memory cell is detected by a verification read and its resistance state needs to change, it is marked as true. In this embodiment, the mask information does not record whether the resistive switching device whose resistance state needs to change is located on the left or right side of the 2T2R differential resistive switching memory cell. Mask information for different resistance state change stages can reuse the mask and mask buffer. This method can reduce the memory capacity required by the mask buffer and significantly reduce the circuit area of ​​the mask buffer while maintaining the same write burst capability.

[0124] It should be noted that the speed at which external data is written to the on-chip data buffer is typically much higher than the write speed of non-volatile memories such as RRAM. In technical solutions using data buffers, the buffers are not originally intended for specific control methods, and their chip area usage does not conflict with the chip area reduction achieved by mask buffers. Furthermore, the capacity of the data buffer can differ from that of the mask buffer. In technical solutions that use a data interface bus to replace the data buffer, the external source needs to synchronously provide the data to be written via the data interface.

[0125] In step S808, it is determined whether it is the end address. If not, the address is incremented and the process returns to step S804.

[0126] If the end address has not been reached, the process continues to address the next address, retrieves the data to be written, and repeats the verification and read process.

[0127] In step S809, if it is the end address, continue to determine if there is an address that needs to change the resistance state or the value of the voltage increase number parameter to reach the maximum voltage increase number; if it is determined that there is no address that needs to change the resistance state or reach the maximum voltage increase number, then proceed to step S818.

[0128] This can be understood as follows: when the verification read reaches the end address and no resistive switching device is found whose resistance state needs to be changed, it means that there is no resistive switching device whose resistance state needs to be changed in the resistance state change stage currently indicated by RS_C. Therefore, no write operation will be triggered. At this time, the process will proceed to step S820, where RS_C is incremented to indicate a new resistance state change stage or to indicate the end of the entire verification write process.

[0129] No resistance state change was found, including the following two situations: When the first verification read is performed, it is found that the resistance state of the resistive switching device is the same as the expected resistance state, and no write operation is required; When the verification read-write cycle is repeated, all resistive switching devices that need to change their resistance state in the resistance state change stage currently indicated by RS_C have been successfully written.

[0130] In step S810, if it is determined that there is an address that needs to change the resistance state or the maximum number of pressurization cycles has not been reached, the starting address is set.

[0131] In step S811, the on-chip power supply is controlled to establish the operating voltage for the write operation.

[0132] In step S812, the data to be written is read.

[0133] In this embodiment, the data to be written is read before the mask information is decoded.

[0134] Before the mask information is sent to the write driver enable decoder for decoding, the data to be written needs to be read.

[0135] The selected side decoder generates a selection indication signal CO_LEFT[i-1:0], connecting the resistive switching device whose resistance state is expected to be changed to the voltage line of the write voltage output by the write circuit. In this way, within a single continuous write operation, both the left and right resistive switching devices whose resistance state is expected to change can be subjected to operating voltage, improving the efficiency of voltage application. Compared with existing techniques that apply voltage only to one side at a time, this application's solution does not experience efficiency degradation when writing random data, making it more advantageous. Furthermore, since reading the data to be written is a typical SRAM volatile memory read access, which is very short compared to the voltage application time and can be ignored, the improved voltage application efficiency significantly reduces write time and increases write speed.

[0136] In addition, when selecting transistors in the 2T2R differential resistive variable memory cell, low-voltage MOS devices are used to further reduce costs and ensure compatibility with CMOS processes. When applying voltage, overvoltage will be generated on the selection transistor. Improving the voltage application efficiency can reduce the overvoltage time of the selection transistor's gate, thereby slowing down the aging speed of the memory cell array and thus ensuring the reliability of the memory cell array to a certain extent.

[0137] In step S813, the selected-side decoder is controlled to generate an i-bit selection indication signal MC_LEFT[i-1:0] for the current word, connecting the bit line and write circuit of the selected-side resistive converter.

[0138] It should be noted that since the mask buffer does not store information about which side of the 2T2R differential resistor variable memory cell the operating voltage is applied to, but only stores information about whether the operating voltage needs to be applied, the data to be written needs to be read again before applying the voltage to restore the information about which side of the 2T2R differential resistor variable memory cell the operating voltage is applied to, and the selection signal needs to be regenerated by the selected side decoder.

[0139] In step S814, the mask information stored in the mask buffer is read, the write driver enable decoder is controlled to decode the mask information, and a write driver enable signal is generated to enable the corresponding write driver unit.

[0140] The mask information is read and sent to the write driver enable decoder. After decoding, the write drive unit (WD) shown in Figure 6 is enabled, and a preset write operation voltage pulse is applied under the control of the timing generator. Prior to this, the resistive switching device whose resistance state is expected to be changed has been connected to the write voltage signal output by the write circuit.

[0141] It should be noted that during decoding, the selected signal, regenerated by the selected-side decoder from the data to be written, is read using this control method to restore the selected-side information. This ensures that only the resistive switching device expected to undergo a resistance state change is applied with an operating voltage. Therefore, the left and right resistive switching devices of different 2T2R differential resistive switching memory cells in the current address word can be applied with operating voltages simultaneously and independently, without dependency. The selection of the left or right side depends solely on whether the data to be written is 0 or 1, the preset 0 / 1 data encoding scheme, and the current resistance state change type. The write circuit, mask buffer, and write driver enable decoder of the memory cell array can all be time-division multiplexed at different resistance state change stages. Through the "2_to_1_MUX" two-way multiplexer and selection signal in Figure 6, when writing 0 or 1 data at the same resistance state change type stage, the write circuit, mask buffer, and write driver enable decoder of the memory cell array can all be time-division multiplexed. Because the left and right resistive switching devices of different 2T2R differential resistive switching memory cells in the current addressing word can be operated independently and simultaneously, this method offers significant efficiency and speed advantages when writing random data compared to techniques that can only change the resistance state of the left or right resistive switching devices at the same time. The peripheral circuitry of the memory cell array can be time-division multiplexed, further reducing area overhead and effectively improving memory density and the efficient utilization of memory chip area.

[0142] In step S815, the timing generator is controlled to apply operating voltage pulses to the addressed word lines and bit lines.

[0143] In step S816, it is determined whether it is the end address. If not, the address is incremented and the process proceeds to step S812.

[0144] In step S817, if it is the end address, the pressurization count parameter is incremented by 1, and the process proceeds to step S802.

[0145] In step S818, the value of the resistance change counter is incremented by 1, and the number of pressurization cycles parameter is cleared to 0.

[0146] In step S819, it is determined whether the value of the resistance change counter is greater than 2. If not, proceed to step S802.

[0147] In this embodiment, according to the definition of the resistance state change counter, when the value of the resistance state change counter is equal to 2, the process proceeds to step S802 to perform a verification write process for another type of resistance state change. When the value of the resistance state change counter is greater than 2, it indicates that both resistance state change types (HR write and LR write) have been completed, and the entire verification write process ends.

[0148] The control method of this application embodiment, while balancing reliability and reducing the overhead caused by the increase in peripheral circuit area, enables resistive switching devices distributed on different sides of multiple 2T2R differential resistive switching memory cells to simultaneously perform the same type of resistive state change, and the resistive state change can be performed continuously with high efficiency. Simultaneously, the power supply operating time for the RRAM memory is reduced, effectively lowering write power consumption. Moreover, since the mask information does not distinguish between the selected side, the mask is simpler under the same write burst capability, thus reducing the chip area occupied by the mask buffer. Furthermore, the selection transistor in the 2T2R differential resistive switching memory cell is a low-voltage MOS device, which will generate overvoltage on the selection transistor during voltage application. Improving the voltage application efficiency can reduce the overvoltage time of the selection transistor's gate, thereby slowing down the aging rate of the memory cell array. Additionally, the read circuit, write circuit, mask encoder, mask buffer, and write drive enable decoder can all be time-division multiplexed at different resistive state change stages, further reducing memory area overhead and effectively improving memory density and the efficient utilization of memory chip area.

[0149] It should also be noted that the exemplary embodiments mentioned in this invention describe methods or systems based on a series of steps or apparatus. However, this invention is not limited to the order of the steps described above; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0150] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only.

[0151] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A differential resistive variable memory chip, characterized in that, The system includes a memory cell array consisting of multiple 2T2R differential resistive switching memory cells, a controller, a read circuit, and a write circuit. Each of the 2T2R differential resistive switching memory cells includes two resistive switching devices. The controller includes an algorithm state machine, a selected-side decoder, a mask encoder, a mask buffer, and a write driver enable decoder. The algorithm state machine controls the operation of the selected-side decoder, the mask encoder, and the write driver enable decoder. The algorithm state machine is used to set the current resistance state change type; wherein, the resistance state change type indicates the resistance state change direction of the resistive switching device. The selected-side decoder generates a selection indication signal based on the current resistance state change type output by the algorithm state machine and the data to be written. The selection indication signal is used to indicate the bit lines of the read circuit and the write circuit connected to the first target resistive switching device, so as to ensure that only the resistive switching devices in the 2T2R differential resistive switching memory cell that need to change their resistance state are read during the verification read process, and that the resistive switching devices in the 2T2R differential resistive switching memory cell that need to change their resistance state are applied an operation voltage during the application of the write operation voltage; wherein, the first target resistive switching device is the selected-side resistive switching device in the multiple 2T2R differential resistive switching memory cells corresponding to the current word that needs to change its resistance state. The mask encoder is used to generate mask information based on the current resistance state change type output by the algorithm state machine and the data read from the first target resistive switching device by the read circuit. The mask information is used to indicate the second target resistive switching device in the first target resistive switching device that requires the application of an operating voltage. The mask buffer is used to store the mask information generated by the mask encoder; The write driver enable decoder is used to decode the mask information read by the algorithm state machine control, and generate a write driver enable signal to enable the write circuit.

2. The chip according to claim 1, characterized in that, The read circuit includes multiple inductive amplifier units. Each inductive amplifier unit is connected to a 2T2R differential resistive variable memory cell through a first selector unit. The first selector unit is electrically connected to the selected-side decoder to connect the resistive variable device on the selected side of the 2T2R differential resistive variable memory cell and the corresponding inductive amplifier unit according to the selection indication signal.

3. The chip according to claim 1, characterized in that, The write circuit includes multiple write drive units. Each write drive unit is connected to a 2T2R differential resistive switching memory cell through a second selector unit. The second selector unit is electrically connected to the selected-side decoder to connect the resistive switching device on the selected side of the 2T2R differential resistive switching memory cell and the corresponding write drive unit according to the selection indication signal.

4. The chip according to claim 1, characterized in that, During different impedance state change stages, the read circuit, write circuit, mask encoder, mask buffer, and write drive enable decoder all realize time-division multiplexing of signals.

5. The chip according to claim 1, characterized in that, The resistance state change types include changing the resistance state of the resistive switching device from a high resistance state to a low resistance state, and changing the resistance state of the resistive switching device from a low resistance state to a high resistance state.

6. The chip according to claim 5, characterized in that, The algorithm state machine is also used to set the address space for continuous reading and writing of the storage cell array according to the data to be written.

7. The control method for a differential resistive variable memory chip as described in any one of claims 1 to 6, characterized in that, The method includes: Set the current resistance state change type, and establish the operation conditions for verification reading and set the reference current for verification reading based on the current resistance state change type; A verification reading step is performed to determine whether there is a second target resistive switching device in the first target resistive switching device whose resistive state is not the desired resistive state; wherein, the first target resistive switching device is determined by the selection indication signal, and the second target resistive switching device is a resistive switching device in the first target resistive switching device whose resistive state is not the desired resistive state, and the second target resistive switching device is determined by the mask information; When there is a second target resistive switching device in the first target resistive switching device whose resistive state is not the desired resistive state, a write operation voltage is applied to the second target resistive switching device, and the verification read step and subsequent steps are repeated until the resistive state of the second target resistive switching device is the desired resistive state or the number of times the write operation voltage is applied reaches the preset maximum number of times the write operation voltage is applied. Change the current resistance state change type, return to the first step to execute, until the resistance state of the first target resistive switching device corresponding to the changed current resistance state change type is the desired resistance state or the number of times the write operation voltage is applied reaches the preset maximum number of times the write operation voltage is applied, then terminate this process.

8. The method according to claim 7, characterized in that, The verification read step is a continuous read operation implemented according to the address space corresponding to the data to be written; and the application of the write operation voltage to the second target resistive switching device is a continuous write operation implemented according to the address space corresponding to the data to be written.

9. The method according to claim 7, characterized in that, The setting of the current resistance state change type includes: The current resistance change type is set by setting the value of the resistance change counter.

10. The method according to claim 7, characterized in that, The verification read step includes: The control timing generator generates a read control timing sequence to read the data from the first target resistive switching device; and Applying a write operation voltage to the second target resistive switching device includes: A timing generator is used to generate write control timing, which controls the application of write operation voltage to the second target resistive switching device.

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