A memory structure and its implementation method for realizing full range low swing

Abstract

The application provides a memory structure and a method for realizing full-range low swing, wherein the memory structure comprises a match line, a memory output circuit structure and a plurality of content addressable memory units; the content addressable memory unit is used for reading and writing bits, inputting and outputting bits, and transmitting results to the match line; the content addressable memory unit comprises a static random memory and a search module; the memory output circuit structure is used for judging whether the results of the match line of the content addressable memory unit match or not, and outputting the judgment results; the memory output circuit structure is coupled with the sub-match line of each content addressable memory unit through the match line. The application controls the voltage of the match line through the memory unit and the memory output circuit structure, controls the voltage of the match line in a small amplitude range, reduces the swing of the voltage of the match line, and thus reduces the dynamic power consumption of the memory.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a memory structure and implementation method for achieving full-range low swing. Background Technology

[0002] Content-addressable memory (CAM) is a special type of memory. Each CAM cell contains embedded comparison logic; data written to CAM is compared with every piece of data stored within it, and the result returns the addresses of all internal data that match the port data. CAM cells are constructed by adding transistors to a standard static random access memory (SRAM) cell structure to perform the matching function.

[0003] Traditional content-addressable memory (CDMA) matching line structures paired with conventional sensitive amplifiers generate significant power consumption during operation. This is due to the constant full-swing voltage fluctuations between ground and power supply levels caused by word matching and mismatch. Therefore, lower power consumption technologies are urgently needed. Summary of the Invention

[0004] To address the above problems, this invention provides a memory structure and implementation method for achieving low swing across the entire range.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows:

[0006] A memory structure that achieves full-range low swing includes: a matching line, a memory output circuit structure, and several content-addressable memory cells;

[0007] The content-addressable memory unit is used to read and write bits, input and output bits, and transmit the results to the matching line. The content-addressable memory unit includes a static random access memory (SRAM) and a search module. The SRAM includes four N-type transistors, two P-type transistors, two bit lines, and one word line. The two N-type transistors and two P-type transistors form two inverters, with the input of one inverter connected to the output of the other. The two inverters are interconnected to form a latch structure to store bits. The word line is connected between two external N-type transistors, and the two external N-type transistors are respectively connected to the two bit lines to read and write bits. The search module includes four N-type transistors, two search lines, one sub-matching line, and one low-matching line. The two upper N-type transistors are respectively connected to the two search lines, the sub-matching line is connected between the two upper N-type transistors, the two lower N-type transistors are connected to the SRAM to perform the search function, and the low-matching line is connected between the two lower N-type transistors.

[0008] The memory output circuit structure is used to determine whether the result of the matching line of the content-addressable memory cell matches and outputs the determination result; the memory output circuit structure is coupled to the sub-matching line of each content-addressable memory cell through the matching line.

[0009] Furthermore, the memory output circuit structure controls the matching line flip voltage within a small range through a control circuit, thereby achieving low-amplitude flipping of the matching line and outputting the matching judgment result.

[0010] Furthermore, the memory output circuit structure includes transistors P0, P1, P2, P3, N2, N3, and three inverters INV; the low matching line and the PRE 0 signal are used as the input of an OR gate, and the output of the OR gate is connected to the gate of transistor P0, with the drain of transistor P0 connected to the matching line; the gate of transistor P1 is connected to the output of the lower inverter INV, and its drain is connected to the input of the lower inverter INV, i.e., node Y; the gate of transistor P2 is connected to node Y, and its drain is connected to node X; the gate of transistor P3 is connected to YPRE, and its drain is connected to node Y; node Y and the EN signal are used as the input of the output circuit module, and the output is to OUTPUT; the matching line and the PRE 1 signal are used as the input of the two lower inverters INV, and their output is node X; the gate of transistor N2 is connected to DIS, and its drain is connected to the matching line; the gate of transistor N3 is connected to node X, its source is connected to the matching line, and its drain is connected to node Y.

[0011] A storage device circuit includes several memory structures that achieve full-range low swing, wherein the content-addressable memory cells in each memory structure are arrayed to store multiple bytes, and each matching line and output is in row format.

[0012] A control method for achieving a memory structure with full-range low swing, based on a memory structure that achieves full-range low swing, includes the following steps:

[0013] During the non-search matching phase, first, the DIS signal is set to a high level to turn on transistor N2 and fully discharge the matching line; the YPRE signal is set to a low level to turn on transistor P3 and charge node Y; the PRE1 signal is set to a high level to reduce the output node X level and turn off transistor N3 to isolate node Y from the matching line; then, the PRE0 signal is set to a high level to turn on transistor P0 and charge the matching line.

[0014] During the matching phase, if a match is found, the matching line is at a high level. Since the matching line level has not reached the common output CMOS gate enable voltage, node X is at a low level and node Y is at a high level. If there is no match, the sub-matching line discharges to the low matching line. When the low matching line is charged to the OR gate enable voltage, transistor P0 is turned off, causing the matching line to stop charging. The matching line is at a low level, which is input to the common output CMOS gate. Therefore, node X is at a high level, which turns on transistor N3, causing node Y to discharge and be at a low level. During the output phase, the EN signal is set to a high level. If node Y is at a high level, the output signal OUT is 1. If node Y is at a low level, the output signal OUT is 0.

[0015] The beneficial effects of this invention are as follows:

[0016] This invention controls the matching line voltage through the memory cell and memory output circuit structure, keeping the matching line voltage within a small range and reducing the voltage swing, thereby reducing the dynamic power consumption of the memory. The memory output circuit structure connects to the matching line of the content-addressable memory cell. The control circuit keeps the matching line switching voltage within a small range, achieving low-swing switching of the matching line, and thus outputs the matching judgment result. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the content-addressable memory cell structure in an embodiment of the present invention;

[0018] Figure 2 This is a schematic diagram of a memory circuit structure that achieves low swing across the entire range of the matching line in an embodiment of the present invention;

[0019] Figure 3 This is a simulation waveform diagram of the memory circuit in an embodiment of the present invention;

[0020] Figure 4 This is a schematic diagram of a storage device in an embodiment of the present invention;

[0021] Figure 5 The above is a simulation waveform diagram of the storage device in an embodiment of the present invention. Detailed Implementation

[0022] The present invention will be further illustrated below with reference to the accompanying drawings and specific embodiments. It should be understood that the following specific embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention.

[0023] like Figure 1 As shown in the figure, the content-addressable memory cell structure a in this embodiment includes a static random access memory (SRAM) b and a search module c. The content-addressable memory cell is used to read and write bits, including 0s and 1s, and uses its structure to input and output bits, and transmits the results to the matching line.

[0024] The static random access memory (SRAM) b comprises four N-type transistors and two P-type transistors, two bit lines (BL1, BL2), and one word line (WL), enabling storage and read / write operations. The source of the upper P-type transistor is connected to VDD, and the source of the lower N-type transistor is connected to GND. Their gates are connected as inputs, and their drains are connected as outputs, forming an inverter. The source of the external N-type transistor on the left is connected to the output of the inverter, its gate is connected to the word line, and its drain is connected to bit line 1. Similarly, mirroring this structure yields a symmetrical structure, where the drain of the external N-type transistor on the right is connected to bit line 2. The input of the left inverter is connected to the output of the right inverter, and the input of the right inverter is connected to the output of the left inverter. The two inverters are interconnected to form a latch structure for bit storage. The word line connects between the two external N-type transistors, which are then connected to the two bit lines to perform bit read / write operations. When performing a write operation, the word line is set to 1, one bit line value is set to the write value, and the other bit line value is its opposite value, so that the value can be written to two connected inverters to achieve storage; when performing a read operation, the word line is set to 1, and the stored value is read by comparing the differential voltage between the two bit lines.

[0025] The search module c includes four N-type transistors, two search lines (SL1, SL2), one matching line (ML), and one low-matching line (MLL), enabling search and matching operations. Figure 1 Taking the two N-type transistors on the left as an example, the drain of the upper N-type transistor is connected to the matching line, and it is connected in series with the lower N-type transistor. The source of the lower N-type transistor is connected to the low matching line. The gate of the upper N-type transistor is connected to the search line SL2. The gate of the lower N-type transistor is connected to the source of the external N-type transistor on the left side of the static memory b. Similarly, by mirroring and flipping them... Figure 2 A symmetrical structure is shown on the right side, where the gate of the upper N-type transistor is connected to search line SL1, and the gate of the lower N-type transistor is connected to the source of the externally connected N-type transistor on the right side of the static memory b. The two upper N-type transistors are connected to the two search lines respectively, and a matching line is connected between the two upper N-type transistors. The two lower N-type transistors are connected to the static random access memory to realize the search function, and a low matching line is connected between the two lower N-type transistors. During the search operation, the matching line is pre-charged, and the value to be searched and its opposite value are added to the two search lines (SL1, SL2). During the matching operation, if the search keyword is the same as the data stored in the static random access memory b, it indicates a match, the path from the matching line to the low matching line is turned off, and the matching line value remains unchanged; if the search keyword is different from the data stored in the static random access memory b, it indicates a mismatch, the path from the matching line to the low matching line is turned on, and the matching line is discharged to the low matching line.

[0026] like Figure 2As shown, this specification provides a memory circuit structure for achieving low swing across the entire range, including a memory output circuit structure d and memory sub-units 1 to n, wherein the memory sub-units are... Figure 1 Structure a. In the memory output circuit structure d, the INV structure is the inverter structure in the static memory b. MLL and PRE0 are used as OR gate inputs, and the OR gate output is connected to the gate of transistor P0. The drain of transistor P0 is connected to the matching line. The gate of transistor P1 is connected to the lower INV output, and the drain is connected to the lower INV input, i.e., node Y. The gate of transistor P2 is connected to node Y, and the drain is connected to node X. The gate of transistor P3 is connected to YPRE, and the drain is connected to node Y. Node Y and EN are used as inputs to the output circuit module, and the output is to OUTPUT. The matching line and PRE1 are used as inputs to the two lower INVs, and their output is node X. The gate of transistor N2 is connected to DIS, and the drain is connected to the matching line. The gate of transistor N3 is connected to node X, the source is connected to the matching line, and the drain is connected to node Y. The memory output circuit structure is used to determine whether the matching line of the content-addressable memory cell matches and output the judgment result. It is connected to the matching line of the content-addressable memory cell. The control circuit controls the switching voltage of the matching line within a small range to achieve low swing switching of the matching line and output the matching judgment result. Specifically, in this example, the low matching line (MLL) and the PRE0 signal are used as OR gate inputs to control transistor P0. The switching on and off of transistor P0 controls the charging of the matching line (ML). The matching line (ML) is coupled to the sub-matching lines of multiple memory cells (1 to n). The DIS signal controls the switching on and off of transistor N2, which controls the discharging of the matching line (ML). The matching line signal and the PRE1 signal jointly control the common-output CMOS gate to control node X. Node X controls the switching on and off of transistor N3, which controls the isolation between node Y and the matching line. The YPRE signal controls the switching on and off of transistor P3, which controls the charging of node Y. Node Y controls the switching on and off of transistor P2, which controls the charging of node X. Transistor P1 and an inverter form a latch circuit to latch node Y. The node Y signal and the EN signal jointly control the output circuit, outputting the matching result as OUT.

[0027] like Figure 3 The image shown is a simulation waveform diagram of the memory structure. Figure 2 The working process of the memory circuit structure shown will be coordinated with Figure 3The waveform diagram will be described in detail below. During the non-matching search phase, the DIS signal is first set high to turn on transistor N2 and fully discharge the matching line. The YPRE signal is set low to turn on transistor P3 and charge node Y. The PRE1 signal is set high to reduce the output node X level and turn off transistor N3 to isolate node Y from the matching line. Then, the PRE0 signal is set high to turn on transistor P0 and charge the matching line. During the matching search phase, if a match is found, the matching line is at a high level. Since the matching line level has not reached the common output CMOS gate enable voltage, node X is at a low level and node Y is at a high level. If a match is not found, the sub-matching line discharges to the low matching line. When the low matching line is charged to the OR gate enable voltage, transistor P0 is turned off to disconnect the charging of the matching line. The matching line is at a low level and inputs to the common output CMOS gate, so node X is at a high level, turning on transistor N3 and causing node Y to discharge to a low level. During the output phase, the EN signal is set high. If node Y is at a high level, the output signal OUT is 1; if node Y is at a low level, the output signal OUT is 0. Therefore, the memory circuit structure allows the matching line voltage to fluctuate within a small range, achieving low swing across the entire range of the matching line and reducing the dynamic power consumption of the memory.

[0028] like Figure 4 As shown, this specification provides a storage device circuit in an embodiment. Content-addressable memory unit ( Figure 1 The structure shown exists in array form, storing multiple bytes. The SA module is the memory circuit structure described above that implements full-range low swing. The matching lines and outputs exist in row form, with output signals OUT1 to OUT2. n Output matching lines ML1 to ML respectively n As a result, each column in the array shares a single bit line.

[0029] like Figure 5 The diagram shown is a simulation waveform diagram simulating the aforementioned storage device. When the EN signal is high, matching is enabled. If the string to be searched is identical only to the string stored in the second row of the array, while the strings stored in the remaining rows are not identical to the searched string, then OUT1 to OUT2... n Only OUT2 outputs are high, while the rest are low.

[0030] It should be noted that the above content merely illustrates the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. For those skilled in the art, various improvements and modifications can be made without departing from the principle of the present invention, and all such improvements and modifications fall within the scope of protection of the claims of the present invention.

Claims

1. A memory structure that achieves low swing across the entire range, characterized in that, include: Matching lines, memory output circuit structure, and several content-addressable memory units; The content-addressable memory unit is used to read and write bits, input and output bits, and transmit the results to the matching line. The content-addressable memory unit includes a static random access memory (SRAM) and a search module. The SRAM includes four N-type transistors, two P-type transistors, two bit lines, and one word line. The two N-type transistors and two P-type transistors form two inverters, with the input of one inverter connected to the output of the other. The two inverters are interconnected to form a latch structure to store bits. The word line is connected between two external N-type transistors, and the two external N-type transistors are respectively connected to the two bit lines to read and write bits. The search module includes four N-type transistors, two search lines, one sub-matching line, and one low-matching line. The two upper N-type transistors are respectively connected to the two search lines, the sub-matching line is connected between the two upper N-type transistors, the two lower N-type transistors are connected to the SRAM to perform the search function, and the low-matching line is connected between the two lower N-type transistors. The memory output circuit structure is used to determine whether the matching line of the content-addressable memory cell matches, and outputs the determination result. The memory output circuit structure is coupled to the sub-matching line of the content-addressable memory cell via a matching line; the memory output circuit structure includes transistors P0, P1, P2, P3, N2, and N3, three inverters INV, and an OR gate; the low matching line is used as the input of the OR gate with the PRE0 signal, and the output of the OR gate is connected to the gate of transistor P0. The drain of transistor P0 is connected to the matching line, and the source is connected to the power supply; the gate of transistor P1 is connected to the output of the lower inverter INV, the drain is connected to the input of the lower inverter INV (i.e., node Y), and the source is connected to the power supply; Transistor P2 has its gate connected to node Y, its drain connected to node X, and its source connected to the power supply; transistor P3 has its gate connected to YPRE, its drain connected to node Y, and its source connected to the power supply; node Y and the EN signal serve as the input to the output circuit module, and the output is to OUTPUT; the matching line and the PRE1 signal serve as the input to the two inverters INV below, and their output is to node X; transistor N2 has its gate connected to DIS, its drain connected to the matching line, and its source connected to the matching line; transistor N3 has its gate connected to node X, its source connected to the matching line, and its drain connected to node Y.

2. The memory structure for achieving full-range low swing as described in claim 1, characterized in that, The memory output circuit structure controls the matching line flip voltage within a small range through the control circuit, thereby achieving low-amplitude flipping of the matching line and outputting the matching judgment result.

3. A storage device circuit, characterized in that, It includes several memory structures that achieve full-range low swing as described in any one of claims 1-2, wherein the content-addressable memory cells in each memory structure are distributed in an array to store multiple bytes, and each matching line and output is in row form.

4. A control method for achieving a memory structure with low swing across the entire range, characterized in that, The implementation of the memory structure for achieving full-range low swing as described in any one of claims 1-2 includes the following steps: During the non-search matching phase, first, the DIS signal is set to a high level to turn on transistor N2 and fully discharge the matching line; the YPRE signal is set to a low level to turn on transistor P3 and charge node Y; the PRE1 signal is set to a high level to reduce the output node X level and turn off transistor N3 to isolate node Y from the matching line; then, the PRE0 signal is set to a high level to turn on transistor P0 and charge the matching line. During the matching phase, if a match is found, the matching line is at a high level. Since the matching line level has not reached the common output CMOS gate enable voltage, node X is at a low level and node Y is at a high level. If there is no match, the sub-matching line discharges to the low matching line. When the low matching line is charged to the OR gate enable voltage, transistor P0 is turned off, causing the matching line to stop charging. The matching line is at a low level, which is input to the common output CMOS gate. Therefore, node X is at a high level, which turns on transistor N3, causing node Y to discharge and be at a low level. During the output phase, the EN signal is set to a high level. If node Y is at a high level, the output signal OUT is 1. If node Y is at a low level, the output signal OUT is 0.

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