Memory testing method and testing device, electronic equipment and readable storage medium

Abstract

This disclosure relates to the field of memory testing technology, and more particularly to a memory testing method and apparatus, electronic device, and computer-readable storage medium. The memory testing method includes: sending an instruction signal to the memory, the instruction signal including a randomly generated write instruction or read instruction; detecting the specific type of the instruction signal, and randomly inserting a valid CAS instruction that guarantees the execution of the instruction signal before the instruction signal, and randomly generating and inserting redundant CAS instructions and / or invalid commands unrelated to the instruction signal; causing the memory to execute the instruction signal, the inserted valid CAS instructions, the redundant CAS instructions, and / or the invalid commands, and testing the operation of the memory. This memory testing method can randomly insert different CAS instructions and invalid commands, thereby comprehensively simulating all situations that the memory may encounter during actual use.

Description

Technical Field

[0001] This disclosure relates to the field of memory testing technology, and in particular to a memory testing method and testing apparatus, electronic device and readable storage medium. Background Technology

[0002] In the field of memory testing, to ensure the accuracy of test results, it is necessary to insert as many different CAS instructions as possible. However, the usage scenarios and timing requirements of CAS instructions must meet the protocol specifications of the memory. Furthermore, there are dependencies between different CAS instructions; therefore, each CAS instruction must also meet the protocol specifications to avoid errors that could affect subsequent operations.

[0003] However, current memory testing methods used in this field cannot meet the requirement of inserting different CAS instructions as much as possible in order to meet protocol specifications. This makes it impossible for existing memory testing methods to simulate all the situations that memory may encounter in actual use, and the operation is relatively complicated.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a testing method, testing apparatus, electronic device, and readable storage medium for memory. This memory testing method can simulate as comprehensively as possible all situations that the memory may encounter during actual use.

[0006] This disclosure provides a method for testing a memory, including:

[0007] Send instruction signals to the memory, the instruction signals including randomly generated write or read instructions;

[0008] The specific type of the instruction signal is detected, and a valid CAS instruction that ensures the operation of the instruction signal is randomly inserted before the instruction signal. Redundant CAS instructions and / or invalid commands that are unrelated to the instruction signal are randomly generated and inserted.

[0009] The memory is made to execute the instruction signal, the inserted valid CAS instruction, the redundant CAS instruction and / or the invalid command, and the operation of the memory is tested.

[0010] In one exemplary embodiment of this disclosure, the step of randomly inserting a valid CAS instruction that guarantees the operation of the instruction signal before the instruction signal, and randomly generating and inserting redundant CAS instructions and / or invalid commands unrelated to the instruction signal, includes:

[0011] Detect the type of the previously mentioned valid CAS instruction and determine whether the execution of the current instruction signal can be guaranteed;

[0012] If so, then detect the time interval between the current instruction signal and the previous valid CAS instruction;

[0013] Determine whether the sum of the time interval and the time of the invalid command to be inserted is greater than the duration of the previous valid CAS instruction. During the duration of the duration, the write instruction or the read instruction can be executed.

[0014] If the sum of the times is greater than the duration, then it is determined whether the time interval is greater than the duration. If so, then a valid CAS instruction to ensure the operation of the instruction signal is inserted before the current instruction signal, and redundant CAS instructions and / or invalid commands are randomly inserted between the inserted valid CAS instruction and the current instruction signal.

[0015] In one exemplary embodiment of this disclosure, the method further includes: if the time interval is equal to the duration, then during the remaining duration, the current instruction signal is executed; or, a valid CAS instruction that guarantees the operation of the current instruction signal is inserted, and during the duration of the inserted valid CAS instruction, the redundant CAS instruction and / or the invalid command are inserted before the current instruction signal is executed.

[0016] In one exemplary embodiment of this disclosure, the method further includes: if the time interval is less than the maintenance time, then the current instruction signal is executed directly during the remaining maintenance time; or, during the remaining maintenance time, the redundant CAS instruction and / or the invalid command are inserted first, and then the current instruction signal is executed; or, the valid CAS instruction that ensures the operation of the current instruction signal is inserted, and the redundant CAS instruction and / or the invalid command are inserted first during the maintenance time of the inserted valid CAS instruction, and then the current instruction signal is executed.

[0017] In one exemplary embodiment of this disclosure, the method further includes: if the sum of the times equals the duration, inserting the invalid command and executing the current instruction signal during the remaining duration; or, after inserting the invalid command, inserting the valid CAS instruction that guarantees the operation of the current instruction signal, and after inserting the redundant CAS instruction during the duration of the inserted valid CAS instruction, executing the current instruction signal.

[0018] In one exemplary embodiment of this disclosure, the method further includes: if the sum of the times is less than the duration, inserting the invalid command, and first inserting the redundant CAS instruction during the remaining duration, and then executing the current instruction signal; or, after inserting the invalid command, inserting the valid CAS instruction that ensures the operation of the current instruction signal, and inserting the redundant CAS instruction during the duration of the inserted valid CAS instruction and executing the current instruction signal.

[0019] In one exemplary embodiment of this disclosure, the duration is the maximum duration of the previous valid CAS instruction, or the minimum duration of the previous valid CAS instruction, or the average duration of all valid CAS instructions.

[0020] In one exemplary embodiment of this disclosure, after the valid CAS instruction inserted during the maintenance time of the previously stated valid CAS instruction and before the current instruction signal, the total number of redundant CAS instructions and / or invalid commands inserted does not exceed 7.

[0021] In one exemplary embodiment of this disclosure, the testing method further includes:

[0022] When a valid CAS instruction that guarantees the operation of the instruction signal is randomly inserted before the instruction signal, and redundant CAS instructions and / or invalid commands that are unrelated to the instruction signal are randomly generated and inserted, the number of the randomly inserted valid CAS instructions, the number of the randomly generated and inserted irrelevant redundant CAS instructions and invalid commands is counted.

[0023] After the memory has completed the execution of the instruction signal, the inserted valid CAS instruction, the redundant CAS instruction, and / or the invalid command within the current clock cycle, the count of the valid CAS instruction, the redundant CAS instruction, and the invalid command within the current clock cycle will be reset to zero.

[0024] In one exemplary embodiment of this disclosure, the type of detecting the aforementioned valid CAS instruction includes:

[0025] When the type of the previously detected valid CAS instruction is CAS_FS instruction, the CAS_FS instruction is retained;

[0026] When the type of the previously detected valid CAS instruction is any CAS instruction other than the CAS_FS instruction, the other CAS instructions are ignored.

[0027] In one exemplary embodiment of this disclosure, the number of randomly generated and inserted redundant CAS instructions is multiple, and the redundant CAS instructions have multiple types.

[0028] In one exemplary embodiment of this disclosure, the redundant CAS command signal includes one or more of the following: CAS_WRX command, CAS_WRSB command, and CAS_DC command;

[0029] Specifically, the CAS_WRX instruction is used to randomly write data, the CAS_WRSB instruction is used to repeatedly write high-byte data, and the CAS_DC instruction is used to copy and store the data from the first burst.

[0030] In one exemplary embodiment of this disclosure, the write instruction includes: a memory write instruction and a register write instruction;

[0031] The read instructions include: memory read instructions and register read instructions.

[0032] Another aspect of this disclosure provides a memory testing apparatus, comprising:

[0033] An instruction signal generator is connected to the memory, and the instruction signal generator is used to send instruction signals to the memory;

[0034] A detector, connected to the command signal generator, is used to detect the specific type of the command signal;

[0035] A random signal generator is connected to the detector, and the random signal generator is used to randomly insert a valid CAS instruction that ensures the operation of the instruction signal before the instruction signal, and to randomly generate and insert redundant CAS instructions and / or invalid commands that are unrelated to the instruction signal.

[0036] A tester, connected to the memory, is used to test the memory's operating status;

[0037] The instruction signal includes a randomly generated write instruction or read instruction.

[0038] In one exemplary embodiment of this disclosure, the random signal generator includes:

[0039] A detection component is used to detect the type of the previously mentioned valid CAS instruction and to detect the time interval between the current instruction signal and the previously mentioned valid CAS instruction.

[0040] The judgment component is used to determine whether the previous valid CAS instruction can guarantee the execution of the current instruction signal, and to determine whether the sum of the time interval and the time of the invalid command to be inserted is greater than the duration of the previous valid CAS instruction, and when the sum of the times is greater than the duration, to determine whether the time interval is greater than the duration.

[0041] A signal generating component is configured to randomly insert a valid CAS instruction that guarantees the operation of the instruction signal before the current instruction signal when the time interval is greater than the duration, and to randomly insert the redundant CAS instruction and / or the invalid command between the inserted valid CAS instruction and the current instruction signal.

[0042] In one exemplary embodiment of this disclosure, the testing apparatus further includes:

[0043] A counter is used to count the number of randomly inserted valid CAS commands, randomly generated and inserted irrelevant redundant CAS commands, and invalid commands.

[0044] Another aspect of this disclosure provides an electronic device, comprising:

[0045] Processor; and

[0046] Memory for storing the executable instructions of the processor;

[0047] The processor is configured to execute the memory testing method described in any one of the preceding descriptions by executing the executable instructions.

[0048] Another aspect of this disclosure provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the testing method for the memory described in any one of the preceding claims.

[0049] The technical solution provided in this disclosure can achieve the following beneficial effects:

[0050] This disclosure provides a method for testing a memory, which can randomly generate write or read instructions, thereby increasing the randomness of the testing method and expanding the coverage of test scenarios to detect the memory's operation in various scenarios.

[0051] Furthermore, the testing method for this memory can detect the specific type of the instruction signal, randomly insert a valid CAS instruction to ensure the operation of the instruction signal before the instruction signal, and can randomly generate and insert redundant CAS instructions and / or invalid commands unrelated to the instruction signal.

[0052] Therefore, the testing method can ensure that all inserted CAS commands comply with the requirements of the protocol specification, so that no errors occur during the testing process that would affect subsequent testing and operation.

[0053] Furthermore, randomly generating and inserting CAS instructions and invalid commands can further enhance the randomness of this test method, enabling it to simulate all possible situations that the memory might encounter during actual use as comprehensively as possible during the test.

[0054] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0055] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0056] Figure 1 A flowchart illustrating a testing method for a memory according to an exemplary embodiment of the present disclosure is shown;

[0057] Figure 2 An exemplary embodiment according to this disclosure is shown. Figure 1 A partial flowchart of step S20;

[0058] Figure 3 Another exemplary embodiment according to this disclosure is shown. Figure 1 A partial flowchart of step S20;

[0059] Figure 4 An exemplary embodiment according to this disclosure is shown. Figure 1 A partial flowchart of step S20;

[0060] Figure 5 An exemplary embodiment according to this disclosure is shown. Figure 1 A partial flowchart of step S20;

[0061] Figure 6 A flowchart illustrating a testing method for a memory according to another exemplary embodiment of the present disclosure is shown;

[0062] Figure 7 An exemplary embodiment according to this disclosure is shown. Figure 2 Flowchart of step S201

[0063] Figure 8 A schematic diagram of the module structure of a test apparatus for a memory according to an exemplary embodiment of the present disclosure is shown;

[0064] Figure 9 A schematic diagram of the module structure of an electronic device according to an exemplary embodiment of the present disclosure is shown;

[0065] Figure 10 A schematic diagram of a computer-readable medium according to an exemplary embodiment of the present disclosure is shown.

[0066] Explanation of reference numerals in the attached figures:

[0067] 1. Memory;

[0068] 2. Memory testing device; 21. Instruction signal generator; 22. Detector; 23. Random signal generator; 24. Tester; 25. Counter; 231. Detection component; 232. Judgment component; 233. Signal generation component; 2321. Calculation element; 2322. Acquisition element; 2323. Judgment element;

[0069] 3. Electronic devices; 31. Processor; 32. Memory; 33. Bus; 34. Display unit; 35. I / O interface; 36. Network adapter; 37. External device; 321. Random access memory unit; 322. Cache memory unit; 323. Read-only memory unit; 324. Program / utility; 325. Program module;

[0070] 4. Computer programs. Detailed Implementation

[0071] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0072] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion meaning and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0073] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details described, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, materials, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0074] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, or in one or more software-hardened modules, or in different network and / or processor devices and / or microcontroller devices.

[0075] With the increasing demands and scenarios for the use of electronic devices (such as mobile phones, computers, tablets, televisions, and smartwatches), and the growing requirements for stability during use, the performance and stability of memory, an indispensable component of electronic devices, also need continuous improvement.

[0076] In this field, currently used memories can include: Static Random-Access Memory (SRAM) and Dynamic Random-Access Memory (DRAM). DRAM can include: Rambus Dynamic Random-Access Memory (RDRAM) and Double Data Rate Synchronous Dynamic Random-Access Memory (DDR SDRAM), etc.

[0077] To ensure good performance and stability of the memory during subsequent use, comprehensive testing and verification of its performance and stability are necessary before use. This requires simulating all possible scenarios that the memory might encounter during subsequent use during the testing process.

[0078] However, after careful study of existing memory testing methods, the applicant of this disclosure found that existing memory testing methods cannot achieve the requirement of randomly inserting different CAS instructions as much as possible. This means that existing memory testing methods cannot simulate all possible situations that memory may encounter during the testing process, resulting in low scenario coverage and complex operation when testing memory using existing memory testing methods.

[0079] In order to solve the above-mentioned technical problems, the inventor of this disclosure, after careful consideration and a great deal of creative work, invented a new testing method for memory that can expand the coverage of testing scenarios, thereby enabling the testing process to simulate as comprehensively as possible all the situations that memory may encounter in actual use.

[0080] In one embodiment of this disclosure, such as Figure 1 As shown, the testing methods for memory may include:

[0081] Step S10: Send an instruction signal to the memory. The instruction signal includes a randomly generated write instruction or read instruction.

[0082] Step S20: Detect the specific type of the instruction signal, and randomly insert a valid CAS instruction that ensures the operation of the instruction signal before the instruction signal, and randomly generate and insert redundant CAS instructions and / or invalid commands that are unrelated to the instruction signal.

[0083] Step S30: Activate the memory execution instruction signal, insert valid CAS instructions, redundant CAS instructions, and / or invalid commands, and test the memory's operation.

[0084] The following section uses LPDDR5 memory as an example to explain in detail the testing methods for the aforementioned memory:

[0085] In step S10, an instruction signal transmitter can be used to send an instruction signal to the memory. This instruction signal can include a write instruction or a read instruction. Specifically, the write instruction can include a memory write instruction (wr) and a register write instruction (mwr); the read instruction signal can include a memory read instruction (rd) and a register read instruction (mrr).

[0086] The instruction signal sent to the memory can be a single instruction signal or an instruction string consisting of multiple instruction signals. For example, a single write or read instruction can be sent to the memory, which can be sampled at the first sampling time; or an instruction string can be sent to the memory, which may include multiple write and / or read instructions as well as other instructions, and the instruction string conforms to a first-in-first-out (FIFO) queue. For example, the instruction string can be wr, rd, wr, rd, mrr. In this case, the first instruction in the instruction string is wr. When the memory runs, wr is executed first, rd is executed only after wr is completed, and so on. After rd is completed, the second wr is executed, the second rd is executed, and finally the mrr instruction is executed to end the entire process.

[0087] In this embodiment, the instruction signal can be generated randomly. That is, this disclosure does not require pre-setting the type of instruction signal to be inserted. The instruction signal transmitter can randomly select the instruction signal to be inserted from various types of instruction signals, thereby increasing the randomness of the test method of the memory and expanding the test scenario coverage to detect the operation of the memory in various scenarios.

[0088] In step S20 above, the specific type of the instruction signal can be detected first to determine whether the random instruction signal sent to the memory is a write instruction, a read instruction, or another instruction signal. When the instruction signal sent to the memory by the instruction signal transmitter is an instruction string composed of multiple instruction signals, the specific type of all instructions in the instruction string can be detected simultaneously, or the specific type of each instruction in the instruction string can be detected at different times in a time-division manner.

[0089] In this embodiment, after detecting the specific type of the instruction signal, a valid CAS instruction that guarantees the execution of the instruction signal can be randomly inserted before the instruction signal. Since the memory executes instructions according to a first-in, first-out (FIFO) queue, in the FIFO queue, the next instruction signal can only start execution after the previous instruction signal has finished executing, and the queue terminates after the previous instruction signal finishes executing. Therefore, inserting a valid CAS instruction before the instruction signal to guarantee its execution is to ensure the execution of the next instruction signal adjacent to that CAS instruction. For example, when the instruction string is wr, rd, wr, rd, nrr, a valid CAS instruction that guarantees its execution can be randomly inserted before the first wr instruction. After obtaining the corresponding valid CAS instruction, the execution of the next wr instruction adjacent to it (i.e., the first wr instruction) can be guaranteed; and since the queue terminates after the first wr instruction finishes executing, the valid CAS instruction randomly inserted before the rd instruction is to guarantee the execution of the rd instruction following that valid CAS instruction.

[0090] This disclosure utilizes a first-in-first-out (FIFO) queue to send command signals, allowing for advance knowledge of the execution order of preceding and following command signals during testing. This enables the random insertion of valid CAS commands. Furthermore, since the command signals in this disclosure are randomly generated, and valid CAS commands are also randomly generated and inserted, the accuracy and randomness of the test are enhanced.

[0091] In one embodiment of this disclosure, valid CAS instructions may include: CAS_WR instruction, CAS_FS instruction, and CAS_RD instruction. However, this is not limited to these; valid CAS instructions may also include: CAS_OFF instruction, etc., all of which are within the scope of this disclosure. Specifically, CAS_WR can be used to synchronize the write clock so that the next adjacent WR or MWR instruction can be executed. The CAS_RD instruction can be used to synchronize the read clock so that the next adjacent RD or MRR instruction can be executed. The CAS_FS instruction can be used to synchronize the previous write clock or read clock.

[0092] Therefore, when the detected current instruction signal is a write instruction, a CAS_WR or CAS_FS instruction can be randomly inserted before the write instruction to ensure its proper execution. Similarly, when the detected current instruction signal is a read instruction, a CAS_RD or CAS_FS instruction can be randomly inserted before the read instruction to ensure its proper execution. It should be noted that when inserting a CAS_FS instruction before a write or read instruction, the previous valid CAS instruction must still be within its duration.

[0093] In this embodiment, each valid CAS instruction described above has a duration. If the duration of the immediately preceding CAS_WR instruction has not yet expired, then the current wr instruction does not need to synchronize the write clock, and therefore a new CAS_WR instruction does not need to be inserted before the current wr instruction. If the duration of the immediately preceding CAS_WR instruction expires, then the current weite instruction must use a CAS_WR instruction to synchronize the write clock before execution to ensure that the current wr instruction can run.

[0094] Similarly, if the duration of the immediately preceding CAS_RD instruction has not yet expired, then the current rd instruction does not need to be preceded by a clock synchronization instruction, and therefore a new CAS_RD instruction does not need to be inserted before the current rd instruction. If the duration of the immediately preceding CAS_RD instruction has expired, then the current rd instruction must be preceded by a CAS_RD instruction to synchronize the clock, in order to ensure that the current rd instruction can run.

[0095] If the previous instruction signal is an rd instruction and the current instruction signal is a wr instruction, then a CAS_WR instruction must be inserted before the current wr instruction. Conversely, if the previous instruction signal is a wr instruction and the current instruction signal is an rd instruction, then a CAS_RD instruction must be inserted before the current rd instruction.

[0096] It should be noted that, since the instruction signals of this disclosure meet the requirements of a first-in-first-out queue, the aforementioned previous instruction signal can be understood as an instruction signal that has been completed and retired, while the current instruction signal can be understood as an instruction signal that will start running after the previous instruction signal adjacent to it has been completed.

[0097] If the current instruction signal is a WR instruction, and a CAS_FS instruction was executed before the current instruction signal to synchronize the write clock, then a CAS_WR instruction does not need to be inserted before the current WR instruction. Furthermore, if subsequent instruction signals are all WR instructions under these circumstances, then during the duration of the CAS_FS instruction, a CAS_WR instruction does not need to be inserted before any subsequent WR instruction signal.

[0098] If the current instruction signal is an rd instruction, and a CAS_FS instruction was executed before the current instruction signal to synchronize the read clock, then a CAS_RD instruction does not need to be inserted before the current rd instruction. Furthermore, if all subsequent instruction signals are rd instructions under these circumstances, then during the duration of the CAS_FS instruction, no CAS_RD instruction needs to be inserted before any subsequent wr instruction signal.

[0099] The CAD_OFF instruction described above can be used to terminate the current clock synchronization state. This can be understood as follows: if the duration of the preceding CAS_WR instruction or the CAS_FS instruction synchronizing the write clock has not yet expired, a CAD_OFF instruction can be inserted to terminate the write clock synchronization state. In this case, a new CAS_WR instruction must be inserted before the current WR instruction to resynchronize the write clock and ensure the current WR instruction executes. Similarly, if the duration of the preceding CAS_RD instruction or the CAS_FS instruction synchronizing the read clock has not yet expired, a CAD_OFF instruction can be inserted to terminate the read clock synchronization state. In this case, a new CAS_RD instruction must be inserted before the current rd instruction to resynchronize the read clock and ensure the current rd instruction executes.

[0100] Furthermore, if a power outage occurs before the current instruction signal is executed, the clock synchronization state will immediately end upon power failure. In this case, to resume execution of the current instruction signal after power is restored, a valid CAS instruction must be randomly inserted before the current instruction signal to ensure its execution. For example, if the current instruction signal is a WR instruction, and a power outage occurs, a CAS_WR instruction must be inserted before the WR instruction after power is restored to synchronize the write clock; similarly, if the current instruction signal is an RD instruction, and a power outage occurs, a CAS_RD instruction must be inserted before the RD instruction after power is restored to synchronize the read clock.

[0101] In this embodiment, redundant CAS instructions unrelated to the instruction signal can also be randomly generated and inserted. These redundant CAS instructions can be inserted before or after the instruction signal. By randomly generating and inserting redundant CAS instructions, the randomness of instruction insertion can be further enhanced. This allows the testing method to simulate as many situations as possible that the memory might encounter during actual operation, ensuring that the tested memory exhibits high stability in real-world use.

[0102] In one embodiment of this disclosure, the number of randomly generated and inserted redundant CAS instructions can be multiple. That is, it can be understood that multiple redundant CAS instructions can be inserted before the instruction signal, or multiple redundant CAS instructions can be inserted after the instruction signal, or at least one redundant CAS instruction can be inserted both before and after the specified signal.

[0103] The aforementioned redundant CAS instructions have various types. For example, redundant CAS instruction signals can include one or more of the following: CAS_WRX, CAS_WRSB, and CAS_DC. Specifically, the CAS_WRX instruction can be used to write random data; the CAS_WRSB instruction can be used to repeatedly write the high-byte data, and when the CAS_WRSB instruction is 1, the high-byte [15:8] are all 1, and when the CAS_WRSB instruction is 0, the high-byte [15:8] are all 0; the CAS_DC instruction can be used to copy and store the data from the first burst. However, this is not the only limitation; redundant CAS instructions can also include other CAS instructions.

[0104] In one embodiment of this disclosure, such as Figure 2 As shown, the above-mentioned random insertion of valid CAS instructions before the instruction signal to ensure the execution of the instruction signal, and random generation and insertion of redundant CAS instructions and / or invalid commands unrelated to the instruction signal, may include:

[0105] Step S201: Detect the type of the previous valid CAS instruction and determine whether the execution of the current instruction signal can be guaranteed;

[0106] Step S202: If yes, then detect the time interval between the current instruction signal and the previous valid CAS instruction;

[0107] Step S203: Determine whether the sum of the time interval and the time of the invalid command to be inserted is greater than the duration of the previous valid CAS instruction. If the duration is within the duration, the write instruction or read instruction can be executed.

[0108] Step S204: If the total time is greater than the duration, determine whether the time interval is greater than the duration. If so, insert a valid CAS instruction before the current instruction signal to ensure the operation of the instruction signal, and randomly insert redundant CAS instructions and / or invalid commands between the inserted valid CAS instruction and the current instruction signal.

[0109] The following examples will be used to explain in detail the steps S201 to S204 above:

[0110] When the current instruction signal is wr, the type of the previous valid CAS instruction can be detected. If the type of the previous valid CAS instruction is CAS_WR, it can be determined that the previous valid CAS instruction can guarantee that the current instruction signal wr can be executed. At this time, the time interval between the wr instruction and the detected CAS_WR instruction can be detected.

[0111] It can calculate the time interval between the wr instruction and the detected CAS_WR instruction, plus the total time of any invalid commands to be inserted before the wr instruction; or it can calculate the time interval plus the total time of any invalid commands and / or redundant CAS instructions to be inserted before the wr instruction. It can also obtain the duration of the CAS_WR instruction and determine whether the sum of the above times is greater than the duration of the CAS_WR instruction.

[0112] If the sum of the above times is greater than the duration of the detected CAS_WR instruction, it means that when the wr instruction is about to run, the duration of the CAS_WR instruction may end, and the write clock may be in an unsynchronized state at this time.

[0113] At this point, to further determine the synchronization status of the write clock when the wr instruction is about to run, it can be checked whether the aforementioned time interval is greater than the duration of the CAS_WR instruction. If the aforementioned time interval is greater than the duration of the CAS_WR instruction, it indicates that the write clock is definitely in an unsynchronized state when the wr instruction is about to run. Therefore, to ensure the normal operation of the current wr instruction, a new CAS_WR instruction needs to be randomly inserted before this wr instruction to resynchronize the write clock. Furthermore, redundant CAS instructions and / or invalid commands can be randomly inserted between the inserted valid CAS instruction and the wr instruction.

[0114] Similarly, when the current instruction signal is rd, the type of the previous valid CAS instruction can be detected. If the type of the previous valid CAS instruction is CAS_RD, it can be determined that the previous valid CAS instruction can guarantee that the current instruction signal rd can be executed. At this time, the time interval between the rd instruction and the detected CAS_RD instruction can be detected.

[0115] It can calculate the time interval between the rd instruction and the detected CAS_RD instruction, plus the total time of any invalid commands to be inserted before the rd instruction; or it can calculate the time interval plus the total time of any invalid commands and / or redundant CAS instructions to be inserted before the rd instruction. It can obtain the duration of the CAS_RD instruction and determine whether the sum of the above times is greater than the duration of the CAS_RD instruction.

[0116] If the sum of the above times is greater than the duration of the detected CAS_RD instruction, it means that when the rd instruction is about to run, the duration of the CAS_Rd instruction may disappear, and the read clock may be in an unsynchronized state at this time.

[0117] At this point, to further determine the synchronization status of the write clock when the rd instruction is about to run, it can be checked whether the aforementioned time interval is greater than the duration of the CAS_RD instruction. If the aforementioned time interval is greater than the duration of the CAS_RD instruction, it indicates that the read clock will definitely be in an unsynchronized state when the rd instruction is about to run. Therefore, to ensure the normal operation of the current rd instruction, a new CAS_RD instruction needs to be randomly inserted before this rd instruction to resynchronize the read clock. Furthermore, redundant CAS instructions and / or invalid commands can be randomly inserted between the inserted valid CAS instruction and the current rd instruction.

[0118] Therefore, the testing method provided in this embodiment can expand the scenarios of redundant CAS instruction insertion, thereby further testing the stability of the memory operation when redundant CAS instructions are inserted.

[0119] In addition, in this embodiment, if the type of the previous valid CAS instruction cannot guarantee the execution of the current instruction signal, then a valid CAS instruction that can guarantee the operation of the instruction signal needs to be inserted before the instruction signal so that the instruction signal can operate normally.

[0120] In one embodiment of this disclosure, if the time interval between the current instruction signal and the previous valid CAS instruction is equal to the duration of the previous valid CAS instruction, the current instruction signal can be executed within the remaining duration of the previous valid CAS instruction. Alternatively, a valid CAS instruction that ensures the execution of the current instruction signal can be inserted before the current instruction signal, and redundant CAS instructions and / or invalid commands can be inserted before the duration of the inserted valid CAS instruction before the current instruction signal is executed. Thus, this disclosure can further expand the testing scenarios for memory through the above two methods of executing instruction signals.

[0121] For example: if the current instruction signal is wr and the previous valid CAS instruction is CAS_WR, and the time interval between the wr instruction and the CAS_WR instruction is equal to the duration of the CAS_WR instruction, the write clock can be considered to be synchronized. Therefore, the current wr instruction can be executed directly within the remaining duration of the CAS_WR instruction; or the CAS_FS instruction can be inserted before the current wr instruction, and within the duration of the CAS_FS instruction, one or more redundant CAS instructions and / or invalid commands from the CAS_WRX, CAS_WRSB, and CAS_DC instructions can be inserted before the current wr instruction is executed.

[0122] It should be noted that in the above embodiments, redundant CAS instructions and / or invalid commands are inserted only once, that is, redundant CAS instructions and / or invalid commands are inserted after valid CAS instructions are inserted.

[0123] However, in this embodiment, redundant CAS instructions and / or invalid commands can be inserted multiple times. That is, a redundant CAS instruction and / or invalid command can be inserted once before a valid CAS instruction is inserted, and then another redundant CAS instruction and / or invalid command can be inserted after a valid CAS instruction is inserted. For example, when the time interval between the wr instruction and the CAS_WR instruction is equal to the duration of the CAS_WR instruction, one or more redundant CAS instructions and / or invalid commands from CAS_WRX, CAS_WRSB, and CAS_DC instructions can be inserted first, followed by the CAS_FS instruction, and then another one or more redundant CAS instructions and / or invalid commands from CAS_WRX, CAS_WRSB, and CAS_DC instructions can be inserted after CAS_FS, and finally the wr instruction is executed. It should be noted that when calculating the time interval, since the time of the instruction signal is determined in advance, even if the time when the current instruction signal needs to be executed has not yet arrived, the interval between the current instruction signal and the previous valid CAS instruction can be known. Therefore, redundant CAS instructions and / or invalid commands can be inserted first, as long as the inserted CAS_FS instruction can effectively synchronize the write clock or read clock.

[0124] Similarly, if the current instruction signal is rd and the previous valid CAS instruction is CAS_RD, and the time interval between the rd instruction and the CAS_RD instruction is equal to the duration of the CAS_RD instruction, the read clock can be considered to be synchronized. Therefore, the current rd instruction can be executed directly within the remaining duration of the CAS_RD instruction; or the CAS_FS instruction can be inserted before the current rd instruction, and within the duration of the CAS_FS instruction, one or more redundant CAS instructions and / or invalid commands from the CAS_WRX, CAS_WRSB, and CAS_DC instructions can be inserted before the current rd instruction is executed.

[0125] Furthermore, in this embodiment, when the time interval between the rd instruction and the CAS_RD instruction is equal to the duration of the CAS_RD instruction, one or more redundant CAS instructions and / or invalid commands from the CAS_WRX instruction, CAS_WRSB instruction, and CAS_DC instruction can be inserted first, followed by the CAS_FS instruction, and then one or more redundant CAS instructions and / or invalid commands from the CAS_WRX instruction, CAS_WRSB instruction, and CAS_DC instruction can be inserted again after the CAS_FS instruction, and finally the rd instruction is executed.

[0126] In one embodiment of this disclosure, if the time interval between the current instruction signal and the previously valid CAS instruction is less than the duration of the previously valid CAS instruction, the current instruction signal can be executed directly within the remaining duration; or, within the remaining duration, redundant CAS instructions and / or invalid commands can be inserted first, and then the current instruction signal can be executed; or, a valid CAS instruction that guarantees the execution of the current instruction signal can be inserted, and redundant CAS instructions and / or invalid commands can be inserted first within the duration of the inserted valid CAS instruction before the current instruction signal is executed. Thus, this disclosure, through the above three different methods of executing instruction signals, can further expand the testing scenarios for memory.

[0127] For example: If the current instruction signal is wr and the previous valid CAS instruction is CAS_WR, and the time interval between the wr instruction and the CAS_WR instruction is less than the duration of the CAS_WR instruction, the write clock can be considered to be still synchronized. Therefore, the current wr instruction can be executed directly within the remaining duration of the CAS_WR instruction. Alternatively, within the remaining duration of the CAS_WR instruction, one or more redundant CAS instructions and / or invalid commands from CAS_WRX, CAS_WRSB, and CAS_DC can be inserted before executing the wr instruction. Or, a CAS_FS instruction can be inserted before the current wr instruction, and within the duration of the CAS_FS instruction, one or more redundant CAS instructions and / or invalid commands from CAS_WRX, CAS_WRSB, and CAS_DC can be inserted before executing the current wr instruction.

[0128] Similarly, if the current instruction signal is rd and the previous valid CAS instruction is CAS_RD, and the time interval between the rd instruction and the CAS_RD instruction is less than the duration of the CAS_RD instruction, the read clock can be considered to be synchronized. Therefore, the current rd instruction can be executed directly within the remaining duration of the CAS_RD instruction. Alternatively, within the remaining duration of the CAS_RD instruction, one or more redundant CAS instructions and / or invalid commands from CAS_WRX, CAS_WRSB, and CAS_DC can be inserted before executing the rd instruction. Or, a CAS_FS instruction can be inserted before the current rd instruction, and within the duration of the CAS_FS instruction, one or more redundant CAS instructions and / or invalid commands from CAS_WRX, CAS_WRSB, and CAS_DC can be inserted before executing the current rd instruction.

[0129] Similarly, in this embodiment, redundant CAS instructions and / or invalid commands can be inserted multiple times. For example, when the time interval between the wr instruction and the CAS_WR instruction is less than the duration of the CAS_WR instruction, one or more redundant CAS instructions and / or invalid commands from the CAS_WRX, CAS_WRSB, and CAS_DC instructions can be inserted first, followed by the CAS_FS instruction, and then one or more redundant CAS instructions and / or invalid commands from the CAS_WRX, CAS_WRSB, and CAS_DC instructions can be inserted again after the CAS_FS instruction, and finally the wr instruction is executed.

[0130] In one embodiment of this disclosure, if the sum of the time interval and the time of the invalid command to be inserted equals the duration, an invalid command can be inserted, and the current instruction signal can be executed within the remaining duration. Alternatively, a valid CAS instruction that guarantees the execution of the current instruction signal can be inserted after the invalid command is inserted, and a redundant CAS instruction can be inserted within the duration of the inserted valid CAS instruction before the current instruction signal is executed. Thus, this disclosure divides the execution of the instruction signal when the sum of the times equals the duration into the above two different methods, thereby further expanding the test scenarios for memory.

[0131] For example: if the current instruction signal is the WR instruction, the previous valid CAS instruction is the CAS_WR instruction, and the sum of the time interval and the time of the invalid command to be inserted equals the sustain time, it can be assumed that the CAS_WR instruction is still sustaining while the current WR instruction is about to run, and the write clock is in a synchronized state. In this case, the invalid command can be inserted before the instruction signal and the instruction signal can be executed normally; alternatively, after inserting the invalid command, a CAS_FS instruction can be inserted, along with one or more redundant CAS instructions from CAS_WRX, CAS_WRSB, and CAS_DC, before executing the current WR instruction.

[0132] In this embodiment, invalid commands can be inserted multiple times. For example, an invalid command can be inserted first, followed by a CAS_FS instruction, and then one or more redundant CAS instructions from CAS_WRX, CAS_WRSB, and CAS_DC. After the redundant CAS instructions are inserted, an invalid command is inserted again, and finally the WR instruction is executed.

[0133] Similarly, if the current instruction signal is the rd instruction, the previous valid CAS instruction is the CAS_RD instruction, and the sum of the time interval and the time of the invalid command to be inserted equals the sustain time, it can be assumed that the CAS_RD instruction is still sustaining while the current rd instruction is about to run, and the read clock is in a synchronized state. In this case, the invalid command can be inserted before the instruction signal and the instruction signal can be executed normally; alternatively, after inserting the invalid command, a CAS_FS instruction can be inserted, along with one or more redundant CAS instructions from CAS_WRX, CAS_WRSB, and CAS_DC, before executing the current rd instruction.

[0134] Furthermore, it is possible to first insert an invalid command, then insert a CAS_FS instruction, and then insert one or more redundant CAS instructions from CAS_WRX, CAS_WRSB, and CAS_DC instructions. After inserting the redundant CAS instructions, an invalid command is inserted again, and finally the current rd instruction is executed.

[0135] In one embodiment of this disclosure, if the sum of the time interval and the time of the invalid command to be inserted is less than the maintenance time, an invalid command can be inserted. A redundant instruction can be inserted first within the remaining maintenance time, and then the current instruction signal can be executed. Alternatively, a valid CAS instruction that guarantees the execution of the current instruction signal can be inserted after the invalid command is inserted, and a redundant CAS instruction can be inserted within the maintenance time of the inserted valid CAS instruction before the current instruction signal is executed. Thus, this disclosure divides the execution of the instruction signal when the sum of the times is less than the maintenance time into the above two different methods, thereby covering more test scenarios for the memory.

[0136] For example: if the current instruction signal is the wr instruction, the previous valid CAS instruction is the CAS_WR instruction, and the sum of the time interval and the time of the invalid command to be inserted is less than the sustain time, it can be assumed that when the current wr instruction is about to run, the CAS_WR instruction is still sustaining and can still have extra sustain time. At this time, the write clock is in a synchronized state. In this case, the invalid command can be inserted before the instruction signal, and since there is still extra sustain time, the CAS_FS instruction can be inserted within the remaining sustain time, along with one or more redundant CAS instructions from CAS_WRX, CAS_WRSB, and CAS_DC, and the instruction signal can be executed normally; or, after inserting the invalid command, the CAS_FS instruction can be inserted, along with one or more redundant CAS instructions from CAS_WRX, CAS_WRSB, and CAS_DC, before executing the current wr instruction.

[0137] Similarly, if the current instruction signal is the rd instruction, the previous valid CAS instruction is the CAS_RD instruction, and the sum of the time interval and the time of the invalid command to be inserted is less than the sustain time, it can be assumed that when the current rd instruction is about to run, the CAS_RD instruction is still sustaining and can still have extra sustain time. At this time, the write clock is in a synchronized state. In this case, the invalid command can be inserted before the rd instruction, and since there is still extra sustain time, the CAS_FS instruction can be inserted within the remaining sustain time, along with one or more redundant CAS instructions from CAS_WRX, CAS_WRSB, and CAS_DC, and the rd instruction can be executed normally; or, the CAS_FS instruction can be inserted after the invalid command, along with one or more redundant CAS instructions from CAS_WRX, CAS_WRSB, and CAS_DC, before executing the current rd instruction.

[0138] Furthermore, in this embodiment, invalid commands can be inserted multiple times, which is also within the scope of protection of this disclosure.

[0139] In one embodiment of this disclosure, after the valid CAS instruction inserted during the duration of the previously mentioned valid CAS instruction and before the current instruction signal, the total number of redundant instructions and / or invalid commands inserted does not exceed seven, to prevent invalid commands from failing to execute and causing memory malfunctions. In this embodiment, the valid CAS instruction inserted during the duration of the previously mentioned valid CAS instruction can be a CAS_FS instruction.

[0140] In one embodiment of this disclosure, the aforementioned duration may be the maximum duration of the previous valid CAS instruction, the minimum duration of the previous valid CAS instruction, or the average duration of all valid CAS instructions.

[0141] In another embodiment of this disclosure, if the total time exceeds the duration, it is no longer necessary to determine whether the time interval exceeds the duration. That is: Figure 3As shown, the above S20 may include: step S201, detecting the previous valid CAS instruction and determining whether the execution of the current instruction signal can be guaranteed; step S202, if so, detecting the time interval between the current instruction signal and the previous instruction signal; step S203, determining whether the sum of the time interval and the time of the invalid command to be inserted is greater than the maximum duration of the previous valid CAS instruction, and within the maximum duration, the write instruction or read instruction can be executed; step S204, if the sum of the times is greater than the maximum duration, randomly inserting a valid CAS instruction to guarantee the operation of the instruction signal before the current instruction signal, and if the sum of the times is less than the maximum duration, randomly inserting a redundant CAS instruction unrelated to the instruction signal between the current instruction signal's time and the end time of the maximum duration, and after the maximum duration ends, randomly inserting a valid CAS instruction to guarantee the operation of the next instruction signal based on the next instruction signal.

[0142] In another embodiment of this disclosure, such as Figure 4 As shown, the above S20 may include: step S201, calculating the maximum duration of all valid CAS instructions; step S202, detecting the time interval between the current instruction signal and the previous instruction signal; step S203, determining whether the sum of the time interval and the time of the invalid command to be inserted is greater than the maximum duration of each valid CAS instruction; step S204, if the sum of the times is greater than the maximum duration of all valid CAS instructions, then randomly inserting a valid CAS instruction that guarantees the operation of the instruction signal before the current instruction signal; if the sum of the times is less than the maximum duration of all valid CAS instructions, then randomly inserting a redundant CAS instruction unrelated to the instruction signal between the current instruction signal's time and the end time of the maximum duration, and after the maximum duration ends, randomly inserting a valid CAS instruction that guarantees the operation of the next instruction signal based on the next instruction signal.

[0143] In one embodiment of this disclosure, such as Figure 5As shown, the above S20 may include: step S201, calculating the minimum duration of each valid CAS instruction; step S202, detecting the time interval between the current instruction signal and the previous instruction signal; step S203, determining whether the sum of the time interval and the time of the invalid command to be inserted is greater than the minimum duration of each valid CAS instruction, within the minimum duration, the write instruction or read instruction can be executed; step S204, if the sum of the times is greater than the minimum duration of all valid CAS instructions, then randomly insert a valid CAS instruction to ensure the operation of the instruction signal before the current instruction signal; if the sum of the times is less than the minimum duration of all valid CAS instructions, then randomly insert redundant CAS instructions unrelated to the instruction signal between the current instruction signal and the end time of the minimum duration, and after the minimum duration ends, randomly insert a valid CAS instruction to ensure the operation of the next instruction signal based on the next instruction signal.

[0144] In one embodiment of this disclosure, such as Figure 6 As shown, the test method may further include:

[0145] Step S40: When randomly inserting a valid CAS instruction that ensures the operation of the instruction signal before the instruction signal, and randomly generating and inserting redundant CAS instructions and / or invalid commands that are unrelated to the instruction signal, the number of randomly inserted valid CAS instructions, randomly generated and inserted irrelevant redundant CAS instructions and invalid commands is counted.

[0146] Step S50: After the memory has completed the execution of the instruction signals, inserted valid CAS instructions, redundant CAS instructions and / or invalid commands in the current clock cycle, the count of valid CAS instructions, redundant CAS instructions and invalid commands in the current clock cycle will be cleared to zero.

[0147] In this embodiment, a counter can be used to count the number of randomly inserted valid CAS commands, randomly generated and inserted irrelevant redundant CAS commands, and invalid commands. However, it is not limited to this; other components can also be used to count their numbers, all of which are within the protection scope of this disclosure.

[0148] In one embodiment of this disclosure, such as Figure 7 As shown, the types of CAS commands that can detect the previous valid command may include:

[0149] Step S2011: When the type of the previously detected valid CAS instruction is CAS_FS instruction, retain the CAS_FS instruction.

[0150] Step S2012: When the type of the detected previous valid CAS instruction is a CAS instruction other than the CAS_FS instruction, ignore the other CAS instructions.

[0151] In this embodiment, since it is impossible to insert other valid CAS instructions between the CAS_FS instruction and its adjacent next instruction signal while the CAS_FS instruction is still in its hold time, the deficiency of not being able to insert other valid CAS instructions between the CAS_FS instruction and its adjacent next instruction signal can be compensated by retaining the CAS_FS instruction when the previous valid CAS instruction is detected to be of the type CAS_FS instruction.

[0152] like Figure 8 As shown, this disclosure also provides a memory testing apparatus 2, which is capable of employing the testing method for the memory 1 described above. This memory testing apparatus 2 can comprehensively simulate all possible scenarios that the memory 1 might encounter during actual use during the testing process.

[0153] The memory testing apparatus 2 provided in this disclosure may include: an instruction signal generator 21, a detector 22, a random signal generator 23, and a tester 24.

[0154] The instruction signal generator 21 can be connected to the memory 1 to send instruction signals to the memory 1. The instruction signal generator 21 can be a processor 31 or a host computer for testing, etc., and this disclosure does not limit its use; it can be selected according to the specific testing environment, all of which are within the scope of protection of this disclosure. Furthermore, the instruction signals issued by the instruction signal generator 21 can include randomly generated write or read instructions.

[0155] The detector 22 can be connected to the command signal generator 21 to detect the specific type of the command signal, and can send the specific type information of the detected command signal to the random signal generator 23.

[0156] The random signal generator 23 can be connected to the detector 22 to receive information about the specific type of the command signal detected by the detector 22. Furthermore, the random signal generator 23 can be used to randomly insert valid CAS instructions that ensure the operation of the command signal before the command signal, and can also randomly generate and insert redundant CAS instructions and / or invalid commands unrelated to the command signal.

[0157] Tester 24 can be connected to memory 1 to test the operation of memory 1.

[0158] The random signal generator 23 provided in this disclosure may further include: a detection component 231, a judgment component 232, and a signal generation component 233.

[0159] In one embodiment of this disclosure, the detection component 231 can be used to detect the type of the previous valid CAS instruction and to detect the time interval between the current instruction signal and the previous instruction signal.

[0160] The judgment component 232 can be used to determine whether the previous valid CAS instruction can guarantee the execution of the current instruction signal, and to determine whether the sum of the time interval and the time of the invalid command to be inserted is greater than the maximum duration of the previous valid CAS instruction, and to determine whether the time interval is greater than the duration when the sum of the times is greater than the duration.

[0161] The signal generation component 233 can be used to randomly insert a valid CAS instruction that ensures the operation of the instruction signal before the current instruction signal when the time interval is greater than the duration, and can also be used to randomly insert redundant CAS instructions and / or invalid commands between the inserted valid CAS instruction and the current instruction signal.

[0162] In this embodiment, when the detection component 231 detects that the type of the previous valid CAS instruction is CAS_FS, it can retain the CAS_FS instruction; furthermore, when the detected previous valid CAS instruction is of a type other than CAS_FS, the detection component 231 can ignore the remaining CAS instructions. In this way, the detector 22 can overcome the deficiency of not being able to insert other valid CAS instructions between the CAS_FS instruction and its adjacent next instruction signal.

[0163] In this embodiment, the determination component 232 may further include: a calculation element 2321, an acquisition element 2322, and a determination element 2323. The calculation element 2321 can be used to calculate the time interval and the sum of the times of the invalid command to be inserted; the acquisition element 2322 can be used to obtain the duration of the previous valid CAS instruction; and the determination element 2323 can be used to compare the sum of the times with the duration of the previous valid CAS instruction to determine whether the sum of the times is greater than the duration of the previous valid CAS instruction.

[0164] In another embodiment of this disclosure, the detection component 231 can be used to calculate the maximum duration of each valid CAS command and detect the time interval between the current command signal and the previous command signal.

[0165] The judgment component 232 can be used to determine whether the sum of the time interval and the time of the invalid command to be inserted is greater than the maximum duration of each valid CAS instruction.

[0166] The signal generation component 233 can be used to randomly insert a valid CAS instruction that ensures the operation of the instruction signal before the current instruction signal when the total time is greater than the maximum duration; and to randomly insert a redundant CAS instruction unrelated to the instruction signal between the current instruction signal's current time and the end time of the maximum duration when the total time is less than the maximum duration, and to randomly insert a valid CAS instruction that ensures the operation of the next instruction signal based on the next instruction signal after the maximum duration ends.

[0167] In yet another embodiment of this disclosure, the detection component 231 can be used to calculate the minimum duration of each valid CAS instruction and detect the time interval between the current instruction signal and the previous instruction signal.

[0168] The judgment component 232 can be used to determine whether the sum of the time interval and the time of the invalid command to be inserted is greater than the minimum maintenance time of each valid CAS instruction.

[0169] The signal generation component 233 can be used to randomly insert a valid CAS instruction that guarantees the operation of the instruction signal before the current instruction signal when the sum of the times is greater than the minimum duration; and when the sum of the times is less than the minimum duration, it can randomly insert a redundant CAS instruction that is unrelated to the instruction signal between the current instruction signal and the end of the minimum duration, and after the minimum duration ends, randomly insert a valid CAS instruction that guarantees the operation of the next instruction signal based on the next instruction signal.

[0170] In one embodiment of this disclosure, the signal generation component 233 in the above embodiments can also be used to generate and insert invalid commands. Furthermore, after a valid CAS command is inserted during the duration of the previous valid CAS command and before the current command signal, the total number of redundant CAS commands and / or invalid commands inserted by the signal generation component 233 does not exceed seven.

[0171] In one embodiment of this disclosure, the memory testing apparatus 2 may further include a counter 25. The counter 25 can be used to count the number of randomly inserted valid CAS instructions, randomly generated and inserted irrelevant redundant CAS instructions, and invalid commands.

[0172] It should be noted that since the memory testing apparatus 2 described in this section can apply the testing method of memory 1 described above, the specific methods used in the memory testing apparatus 2 and their resulting technical effects will not be elaborated here. Please refer to the detailed description of the testing method for memory 1 above. Furthermore, the types of various instruction signals, the types of valid CAS instructions, and the types of redundant CAS instructions will not be repeated here; again, please refer to the detailed description of the testing method for memory 1 above.

[0173] Another aspect of this disclosure provides an electronic device 3. Those skilled in the art will understand that various aspects of the invention can be implemented as systems, methods, or program products. Therefore, various aspects of the invention can be embodied in the following forms: entirely hardware embodiments, entirely software embodiments (including firmware, microcode, etc.), or embodiments combining hardware and software aspects, collectively referred to herein as “circuit,” “module,” or “system.”

[0174] The following reference Figure 9 To describe an electronic device 3 according to such an embodiment of the present invention. Figure 9 The electronic device 3 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0175] like Figure 9 As shown, electronic device 3 is represented in the form of a general-purpose computing device. The components of electronic device 3 may include, but are not limited to: at least one processor 31, at least one memory 32, a bus 33 connecting different system components, and a display unit 34.

[0176] The memory 32 stores program code that can be executed by the processor 31, causing the processor 31 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processor 31 may be configured to perform, via executing executable instructions, such as Figure 1 Steps S10 to S30 shown or Figure 6 Steps S10 to S50 are shown in the diagram.

[0177] The memory 32 can be used to store executable instructions of the processor 31. It may include readable media in the form of volatile memory cells, such as random access memory (RAM) 321 and / or cache memory 322, and may further include read-only memory (ROM) 323.

[0178] The memory 32 may also include a program / utility 324 having a set (at least one) of program modules 325, including but not limited to: an operating system, one or more application programs, other program modules 325 and program data, and each or some combination of these examples may include an implementation of a network environment.

[0179] Bus 33 can represent one or more of several types of bus structures, including a memory bus or memory controller, peripheral bus, graphics acceleration port, processing unit, or a local bus using any of the various bus structures.

[0180] Electronic device 3 can also communicate with one or more external devices 37 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 3, and / or with any device that enables electronic device 3 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 35. Furthermore, electronic device 3 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 36. As shown, network adapter 36 communicates with other modules of electronic device 3 via bus 33. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with electronic device 3, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0181] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0182] Another aspect of this disclosure, such as Figure 10 As shown, a computer-readable storage medium is also provided, on which a computer program 4 capable of implementing the methods described above in this specification is stored. In some possible embodiments, various aspects of the present invention can also be implemented as a computer program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps of the various exemplary embodiments of the present invention described in the "Exemplary Methods" section above.

[0183] refer to Figure 10 As shown, a program product for implementing the above-described memory testing method according to an embodiment of the present invention is described. This product may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0184] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0185] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0186] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0187] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0188] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0189] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, touch terminal, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0190] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method of testing a memory, characterized by, include: Send instruction signals to the memory, the instruction signals including randomly generated write or read instructions; The specific type of the instruction signal is detected, and a valid CAS instruction that ensures the operation of the instruction signal is randomly inserted before the instruction signal. Redundant CAS instructions and / or invalid commands that are unrelated to the instruction signal are randomly generated and inserted. The memory is made to execute the instruction signal, the inserted valid CAS instruction, the redundant CAS instruction and / or the invalid command, and the operation of the memory is tested; The step of randomly inserting a valid CAS instruction to ensure the operation of the instruction signal before the instruction signal, and randomly generating and inserting redundant CAS instructions and / or invalid commands unrelated to the instruction signal, includes: Detect the type of the previously mentioned valid CAS instruction and determine whether the execution of the current instruction signal can be guaranteed; If so, then detect the time interval between the current instruction signal and the previous valid CAS instruction; Determine whether the sum of the time interval and the time of the invalid command to be inserted is greater than the duration of the previous valid CAS instruction. During the duration of the duration, the write instruction or the read instruction can be executed. If the sum of the times is greater than the duration, then it is determined whether the time interval is greater than the duration. If so, then a valid CAS instruction to ensure the operation of the instruction signal is inserted before the current instruction signal, and redundant CAS instructions and / or invalid commands are randomly inserted between the inserted valid CAS instruction and the current instruction signal.

2. The memory testing method according to claim 1, wherein Also includes: If the time interval is equal to the duration, then the current instruction signal is executed during the remaining duration; or, a valid CAS instruction to ensure the execution of the current instruction signal is inserted, and the redundant CAS instruction and / or the invalid command are inserted before the current instruction signal is executed during the duration of the inserted valid CAS instruction.

3. The method of testing memory of claim 1, wherein, Also includes: If the time interval is less than the duration, the current instruction signal is executed directly during the remaining duration; or, during the remaining duration, the redundant CAS instruction and / or the invalid command are inserted first, and then the current instruction signal is executed; or, a valid CAS instruction that ensures the operation of the current instruction signal is inserted, and the redundant CAS instruction and / or the invalid command are inserted first during the duration of the inserted valid CAS instruction, and then the current instruction signal is executed.

4. The testing method for the memory according to claim 1, characterized in that, Also includes: If the sum of the times equals the duration, then the invalid command is inserted, and the current instruction signal is executed during the remaining duration; or, after inserting the invalid command, a valid CAS instruction that ensures the execution of the current instruction signal is inserted, and the redundant CAS instruction is inserted during the duration of the inserted valid CAS instruction before the current instruction signal is executed.

5. The testing method for the memory according to claim 1, characterized in that, Also includes: If the sum of the times is less than the duration, then the invalid command is inserted, and the redundant CAS instruction is inserted first during the remaining duration, and then the current instruction signal is executed. Alternatively, after inserting the invalid command, the valid CAS instruction that ensures the operation of the current instruction signal is inserted, and the redundant CAS instruction is inserted during the duration of the inserted valid CAS instruction and the current instruction signal is executed.

6. The testing method for the memory according to claims 1-5, characterized in that, The duration is either the maximum duration of the previous valid CAS instruction, or the minimum duration of the previous valid CAS instruction, or the average duration of all valid CAS instructions.

7. The testing method for the memory according to claims 2-5, characterized in that, After the valid CAS instruction inserted during the maintenance time of the previously mentioned valid CAS instruction, and before the current instruction signal, the total number of redundant CAS instructions and / or invalid commands inserted shall not exceed 7.

8. The testing method for the memory according to claim 1, characterized in that, The testing method also includes: When a valid CAS instruction that guarantees the operation of the instruction signal is randomly inserted before the instruction signal, and redundant CAS instructions and / or invalid commands that are unrelated to the instruction signal are randomly generated and inserted, the number of the randomly inserted valid CAS instructions, the number of the randomly generated and inserted irrelevant redundant CAS instructions and invalid commands is counted. After the memory has completed the execution of the instruction signal, the inserted valid CAS instruction, the redundant CAS instruction, and / or the invalid command within the current clock cycle, the count of the valid CAS instruction, the redundant CAS instruction, and the invalid command within the current clock cycle will be reset to zero.

9. The testing method for the memory according to claim 4, characterized in that, The types of valid CAS commands mentioned above include: When the type of the previously detected valid CAS instruction is CAS_FS instruction, the CAS_FS instruction is retained; When the type of the previously detected valid CAS instruction is any CAS instruction other than the CAS_FS instruction, the other CAS instructions are ignored.

10. The testing method for the memory according to claim 1, characterized in that, The number of randomly generated and inserted redundant CAS instructions is multiple, and the redundant CAS instructions have various types.

11. The testing method for the memory according to claim 1 or 10, characterized in that, The redundant CAS command signals include one or more of the following: CAS_WRX command, CAS_WRSB command, and CAS_DC command; Specifically, the CAS_WRX instruction is used to randomly write data, the CAS_WRSB instruction is used to repeatedly write high-byte data, and the CAS_DC instruction is used to copy and store the data from the first burst.

12. The testing method for the memory according to claim 1, characterized in that, The write instructions include: memory write instructions and register write instructions; The read instructions include: memory read instructions and register read instructions.

13. A testing apparatus for a memory, characterized in that, include: An instruction signal generator is connected to the memory, and the instruction signal generator is used to send instruction signals to the memory; A detector, connected to the command signal generator, is used to detect the specific type of the command signal; A random signal generator is connected to the detector, and the random signal generator is used to randomly insert a valid CAS instruction that ensures the operation of the instruction signal before the instruction signal, and to randomly generate and insert redundant CAS instructions and / or invalid commands that are unrelated to the instruction signal. A tester, connected to the memory, is used to test the memory's operating status; The instruction signal includes a randomly generated write instruction or read instruction; The random signal generator includes: A detection component is used to detect the type of the previously mentioned valid CAS instruction and to detect the time interval between the current instruction signal and the previously mentioned valid CAS instruction. The judgment component is used to determine whether the previous valid CAS instruction can guarantee the execution of the current instruction signal, and to determine whether the sum of the time interval and the time of the invalid command to be inserted is greater than the duration of the previous valid CAS instruction, and when the sum of the times is greater than the duration, to determine whether the time interval is greater than the duration. A signal generating component is configured to randomly insert a valid CAS instruction that guarantees the operation of the instruction signal before the current instruction signal when the time interval is greater than the duration, and to randomly insert the redundant CAS instruction and / or the invalid command between the inserted valid CAS instruction and the current instruction signal.

14. The testing apparatus for the memory according to claim 13, characterized in that, The testing apparatus also includes: A counter is used to count the number of randomly inserted valid CAS commands, randomly generated and inserted irrelevant redundant CAS commands, and invalid commands.

15. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the memory testing method of any one of claims 1-12 by executing the executable instructions.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the memory testing method according to any one of claims 1-12.

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