Flip quantum chip, substrate of quantum chip, and method for manufacturing substrate

Abstract

The application discloses a flip quantum chip, a substrate of the quantum chip and a substrate manufacturing method. The method comprises the following steps: providing a wafer formed with superconducting metal, the wafer having a central region and a peripheral edge region; performing first photoetching on the central region by non-contact exposure with an exposure field covering the central region; performing first etching on the exposed superconducting metal to form a first circuit structure and a positioning mark; performing second photoetching on the edge region by contact exposure with an exposure field covering the wafer through photoetching alignment of the positioning mark; and performing second etching on the exposed superconducting metal to form a second circuit structure at least partially connected with the first circuit structure. In this way, the application can improve the exposure yield when large-area exposure is performed.

Description

Technical Field

[0001] This invention relates to the field of quantum chip manufacturing technology, and in particular to a flip-chip quantum chip, a quantum chip substrate, and a substrate manufacturing method. Background Technology

[0002] Currently, to improve chip integration density, most quantum chips are packaged using flip-chip technology. Since quantum chips include circuit structures such as Josephson junctions, resonators, capacitors, inductors, and transmission lines, and many large-area circuit structures, such as resonators and transmission lines, are placed on the flip-chip substrate, the substrate size is becoming increasingly larger, typically exceeding 33*33mm.

[0003] In chip manufacturing, one crucial process is photolithography. Photolithography employs exposure techniques including contact and non-contact exposure, with non-contact exposure further divided into proximity exposure and projection exposure. Because the field of view for non-contact exposure is limited to within 22*22mm, while contact exposure supports an exposure area diameter of up to 150mm, current processes generally utilize contact exposure to manufacture large-area substrates.

[0004] However, in contact exposure, the photoresist comes into contact with the photomask during exposure, and the photoresist can easily contaminate the photomask, resulting in a low exposure yield when exposing large areas. Summary of the Invention

[0005] The purpose of this invention is to provide a flip-chip quantum chip, a substrate for the quantum chip, and a method for manufacturing the substrate, so as to solve the problem of low exposure yield in the prior art when large-area exposure is performed, and to improve the exposure yield when large-area exposure is performed.

[0006] To address the aforementioned technical problems, this invention provides a method for manufacturing a substrate for a flip-chip quantum chip, comprising:

[0007] A wafer with a superconducting metal formed thereon is provided, the wafer having a central region and a peripheral edge region;

[0008] The first photolithography is performed in the central region using a non-contact exposure method that covers the central region with an exposure field of view.

[0009] The exposed superconducting metal is etched for the first time to form the first circuit structure and alignment marks;

[0010] Photolithographic alignment is performed using the alignment marks, and a second photolithography is performed on the edge region using contact exposure with an exposure field covering the wafer.

[0011] The exposed superconducting metal is etched a second time to form a second circuit structure that is at least partially connected to the first circuit structure.

[0012] Preferably, the second photolithography is also performed within a preset distance range between the central region and the edge region, so that the first circuit structure and the second circuit structure overlap at the connection point.

[0013] Preferably, both the first etching and the second etching are ICP etching.

[0014] Preferably, the etching gas used in the ICP etching is chlorine or boron trichloride.

[0015] Preferably, the superconducting metal is made of aluminum or niobium.

[0016] Preferably, when the superconducting metal is made of aluminum, the substrate manufacturing method further includes the following steps before the first photolithography:

[0017] Multiple titanium nitride pads are formed on the superconducting metal at intervals.

[0018] To solve the above-mentioned technical problems, the present invention provides a substrate for a quantum chip, wherein the substrate is obtained according to any of the aforementioned substrate manufacturing methods for quantum chips.

[0019] To address the aforementioned technical problems, the present invention provides a flip-chip quantum chip, comprising a first chip and a second chip flip-chip connected to the first chip. The first chip uses the aforementioned substrate, and a plurality of support pillars for supporting the second chip are disposed on the superconducting metal.

[0020] Preferably, the support column is an indium column.

[0021] Preferably, when a titanium nitride pad is formed on the superconducting metal, the indium pillar is placed on the titanium nitride pad.

[0022] Unlike existing technologies, the substrate manufacturing method for quantum chips provided by this invention combines non-contact exposure and contact exposure. First, non-contact exposure is used to form a partial circuit structure in the central region of the wafer, and then contact exposure is used to form another partial circuit structure in the edge region of the wafer. The two circuit structures are interconnected. In non-contact exposure, there is no photoresist contamination problem, and the exposure yield is very high. In contact exposure, the exposure area is reduced, and even if the photoresist in the central region contaminates the photoresist, it does not affect the exposure yield of the edge region. This can improve the exposure yield when exposing large areas. Furthermore, in contact exposure, if the edge region of the photoresist is not contaminated by photoresist, there is no need to clean it, thus reducing the cleaning frequency of the photoresist and indirectly improving work efficiency.

[0023] The quantum chip substrate and flip-chip provided by this invention belong to the same inventive concept and have the same technical effects as the aforementioned substrate manufacturing method for quantum chips, and will not be described again here. Attached Figure Description

[0024] Figure 1 This is a schematic flowchart of a substrate manufacturing method for quantum chips provided in an embodiment of the present invention.

[0025] Figure 2 This is a schematic diagram of a wafer.

[0026] Figure 3 This is a schematic diagram of a wafer after the first photolithography.

[0027] Figure 4 This is a schematic diagram of the wafer after the first etching.

[0028] Figure 5 This is a schematic diagram of the wafer after the second photolithography process.

[0029] Figure 6 This is a schematic diagram of the wafer after the second etching.

[0030] Figure 7 This is a schematic diagram showing the overlap of the lithography ranges of the first and second photolithography processes.

[0031] Figure 8 This is a side view schematic diagram of a flip-chip quantum chip provided in an embodiment of the present invention. Detailed Implementation

[0032] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0033] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0035] Please refer to Figure 1 This invention provides a method for fabricating a substrate for quantum chips. The substrate fabrication method includes the following steps:

[0036] S1: Provides a wafer with superconducting metal formed on it, the wafer having a central region and an outer edge region.

[0037] The wafer material can be silicon, sapphire, etc. Superconducting metals can be formed on the wafer using processes such as deposition or coating. The wafer shape can be circular, square, etc. The wafer surface is divided into two regions: a central region located at the center of the wafer, and an edge region surrounding the central region. The shape of the central region can be set according to actual needs; it can be a regular shape such as circular or square, or an irregular shape.

[0038] For example, such as Figure 2 The image shown is a schematic diagram of a wafer, in which... Figure 2 a is a schematic diagram of the wafer from an oblique angle. Figure 2 b is a top view of the wafer. Wafer 1 is circular, and superconducting metal 2 is formed on wafer 1. The surface of wafer 1 has a central region A1 and an edge region A2. The central region A1 is located at the center of wafer 1, and the edge region A2 surrounds and circumvents the central region A1. The central region A1 is square. The dashed box in the figure represents the boundary between the central region A1 and the edge region A2. It should be noted that the dashed box is only used to indicate the range of the central region A1 and does not represent any entity.

[0039] S2: The first photolithography is performed in the central area using non-contact exposure with the exposure field covering the central area.

[0040] Non-contact exposure can be either proximity exposure or projection exposure. Compared to the entire wafer, non-contact exposure only requires exposure of the central area, reducing the exposure area relative to the entire wafer. The exposure field of view of most non-contact exposure equipment can meet the requirements.

[0041] The first photolithography process is as follows: a photoresist layer is formed on the superconducting metal, a photomask is used to perform non-contact exposure on the photoresist layer in the central area, and the exposed photoresist layer is developed, thereby transferring the mask pattern and alignment pattern on the photomask onto the photoresist layer.

[0042] For example, such as Figure 3 The image shown is a schematic diagram of the wafer after the first photolithography step. Figure 3 a is a schematic diagram of the wafer at an oblique angle after the first photolithography. Figure 3 b is a top view of the wafer after the first photolithography. A first photoresist layer 11 is formed on wafer 1, and a mask pattern 111 and an alignment pattern 112 are formed in the corresponding area of ​​the central region of wafer 1.

[0043] S3: Perform the first etching on the exposed superconducting metal to form the first circuit structure and alignment marks.

[0044] In this process, the mask pattern and alignment pattern obtained from the first photolithography expose the superconducting metal in the central region, which can then be etched to form a first circuit structure corresponding to the mask pattern and an alignment mark corresponding to the alignment pattern.

[0045] For example, such as Figure 4 The image shown is a schematic diagram of the wafer after the first metal etching. Figure 4 a is a schematic diagram of the wafer after the first metal etching at an oblique angle. Figure 4 b is a top view of the wafer after the first metal etching. After the superconducting metal 2 in the central region is etched, a first circuit structure 21 corresponding to the mask pattern 111 and an alignment mark 22 corresponding to the alignment pattern 112 are formed.

[0046] S4: Photolithography alignment is performed using alignment marks, and a second photolithography is performed in the edge area using contact exposure with the exposure field covering the wafer.

[0047] Among them, contact lithography has a large exposure area, which can cover the entire wafer and can perform photolithography on any position on the wafer.

[0048] The second photolithography process involves: forming a photoresist layer on the wafer; photolithographic alignment using alignment marks; contact exposure of the photoresist layer at the edge region using a photomask; and developing the exposed photoresist layer to transfer the mask pattern from the photomask onto the photoresist layer. The difference between the second and first photolithography processes is that the photomask comes into contact with the photoresist, posing a risk of photoresist contamination.

[0049] For example, such as Figure 5 The image shown is a schematic diagram of the wafer after the second photolithography process. Figure 5 a is a schematic diagram of the wafer at an oblique angle after the second photolithography. Figure 5 b is a top view of the wafer after the second photolithography. A second photoresist layer 12 is formed on wafer 1, and a mask pattern 121 is formed in the area corresponding to the edge region of wafer 1 on the second photoresist layer 12.

[0050] S5: Perform a second etching on the exposed superconducting metal to form a second circuit structure that is at least partially connected to the first circuit structure.

[0051] In this process, since the mask pattern obtained by the second photolithography exposes the superconducting metal in the edge region, the exposed superconducting metal can be etched to form a second circuit structure corresponding to the mask pattern. Furthermore, since photolithographic alignment was performed during the second photolithography, the second circuit structure is at least partially connected to the first circuit structure, and the two become an integral circuit structure.

[0052] For example, such as Figure 6 The image shown is a schematic diagram of the wafer after the second metal etching. Figure 6 a is a schematic diagram of the wafer after the second metal etching, viewed from an oblique angle. Figure 6 b is a top view of the wafer after the second metal etching. After the superconducting metal 2 in the edge region is etched, a second circuit structure 23 corresponding to the mask pattern 121 is formed, thereby obtaining the substrate.

[0053] In some embodiments of this application, to avoid errors in photolithographic alignment during the second photolithography, which could cause a break in the connection between the first and second circuit structures, the second photolithography is performed within a preset distance range near the edge region of the central region, so that the first and second circuit structures overlap at the connection point. That is, the second photolithography is performed not only in the edge region but also slightly deeper into the central region, so that a portion of the first circuit structure is exposed after the second photolithography. For example... Figure 7 The diagram shows the overlap of the lithographic areas of the first and second photolithography processes. The mask pattern 111 and alignment pattern 112 of the first photolithography are located in the central region, with the mask pattern 111 extending to the boundary of the central region. The mask pattern 121 of the second photolithography is located in the edge region, but a small portion of the mask pattern 121 extends across the boundary of the edge region into the central region. The mask pattern 111 at the boundary of the central region and the mask pattern 121 at the boundary of the edge region partially overlap; the shaded area in the diagram represents the overlapping region. This allows the first circuit structure 21 located at the boundary of the central region and the second circuit structure 23 located near the boundary of the edge region to overlap at the connection point after the second etching. In a practical application, the overlap length of the first circuit structure 21 and the second circuit structure 23 is 1µm.

[0054] In some embodiments of this application, both the first and second etching are ICP etching, and the etching gas used for ICP etching can be chlorine or boron trichloride.

[0055] In some embodiments of this application, the superconducting metal is made of aluminum or niobium. Furthermore, if the superconducting metal is made of aluminum, the substrate fabrication method prior to the first photolithography step further includes forming a plurality of spaced-apart titanium nitride pads on the superconducting metal.

[0056] The formation process of titanium nitride pads is as follows: a titanium nitride layer is deposited on a superconducting metal; a photoresist layer is formed on the titanium nitride layer; the photoresist layer is exposed using contact etching; after development, the exposed titanium nitride layer is etched using refractive ink (RIE); and after removing the photoresist layer, multiple titanium nitride pads are obtained. The etching precision requirements for the titanium nitride layer are relatively low. Even if there is some incomplete etching of titanium nitride, it will not affect the subsequent etching of the superconducting metal, because the residual titanium nitride can be etched away during the first and second etching processes.

[0057] For example, such as Figure 2 As shown, multiple titanium nitride pads 3 are formed on the surface of the superconducting metal 2 on wafer 1.

[0058] In the above manner, the substrate manufacturing method for quantum chips provided by the embodiments of the present invention combines non-contact exposure and contact exposure. First, non-contact exposure is used to form a partial circuit structure in the central region of the wafer, and then contact exposure is used to form another part of the circuit structure in the edge region of the wafer. The two parts of the circuit structure are interconnected. In non-contact exposure, there is no problem of photoresist contamination, and the exposure yield is very high. In contact exposure, the exposure area is reduced. Even if the photoresist in the central region contaminates the photoresist, it does not affect the exposure yield of the edge region, thereby improving the exposure yield when exposing large areas. Furthermore, in contact exposure, if the edge region of the photoresist is not contaminated by photoresist, there is no need to clean it, thus reducing the cleaning frequency of the photoresist and indirectly improving work efficiency.

[0059] Although contact exposure has the problem of photoresist contamination of the photomask, the substrate manufacturing method of this embodiment allows the photomask to be used without cleaning if the edge area is not contaminated by photoresist. Therefore, the cleaning frequency of the photomask can be reduced, indirectly improving work efficiency.

[0060] This invention also provides a substrate for a quantum chip, which is obtained according to the substrate manufacturing method for a quantum chip described in the foregoing embodiments. For example... Figure 6 The image shows a substrate obtained by the substrate manufacturing method for quantum chips described in the foregoing embodiment.

[0061] Please refer to Figure 8This invention provides a flip-chip quantum chip. The flip-chip quantum chip includes a first chip 10 and a second chip 20 flip-chip connected to the first chip 10. The first chip 10 uses the substrate described in the previous embodiment, and a plurality of support pillars 4 for supporting the second chip 20 are disposed on the superconducting metal 2.

[0062] In some embodiments of this application, the support pillar 4 is an indium pillar. Because indium has low adhesion to aluminum but high adhesion to niobium, when a titanium nitride pad is formed on the superconducting metal 2, the indium pillar is placed on the titanium nitride pad 3. If the superconducting metal is niobium, a titanium nitride pad is not required, and the indium pillar is placed directly on the superconducting metal 2. Figure 8 As shown in the figure, the superconducting metal 2 is aluminum, and a titanium nitride pad 3 is formed on the surface of the superconducting metal 2. One end of the indium pillar is connected to the titanium nitride pad 3, and the other end is connected to the second chip 20.

[0063] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0064] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for manufacturing a substrate for quantum chips, characterized in that, include: A wafer with a superconducting metal formed thereon is provided, the wafer having a central region and a peripheral edge region; The first photolithography is performed in the central region using a non-contact exposure method that covers the central region with an exposure field of view. The exposed superconducting metal is etched for the first time to form the first circuit structure and alignment marks; Photolithographic alignment is performed using the alignment marks, and a second photolithography is performed on the edge region using contact exposure with an exposure field covering the wafer. The exposed superconducting metal is etched a second time to form a second circuit structure that is at least partially connected to the first circuit structure.

2. The substrate manufacturing method according to claim 1, characterized in that, The second photolithography is also performed within a preset distance range between the central region and the edge region, so that the first circuit structure and the second circuit structure overlap at the connection point.

3. The substrate manufacturing method according to claim 1, characterized in that, Both the first and second etching processes are ICP etching processes.

4. The substrate manufacturing method according to claim 3, characterized in that, The etching gas used in the ICP etching is chlorine or boron trichloride.

5. The substrate manufacturing method according to any one of claims 1 to 4, characterized in that, The superconducting metal is made of aluminum or niobium.

6. The substrate manufacturing method according to claim 5, characterized in that, When the superconducting metal is made of aluminum, the substrate manufacturing method prior to the first photolithography step further includes: Multiple titanium nitride pads are formed on the superconducting metal at intervals.

7. A substrate for a quantum chip, characterized in that, The substrate is obtained by the substrate manufacturing method for quantum chips according to any one of claims 1 to 6.

8. A flip-chip quantum chip, characterized in that, It includes a first chip and a second chip flip-chip connected to the first chip. The first chip uses the substrate described in claim 7, and the superconducting metal is provided with a plurality of support pillars for supporting the second chip.

9. The flip-chip quantum chip according to claim 8, characterized in that, The support column is an indium column.

10. The flip-chip quantum chip according to claim 9, characterized in that, When a titanium nitride pad is formed on the superconducting metal, the indium pillar is placed on the titanium nitride pad.

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