Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure comprises: providing a substrate, the substrate comprising a layer to be etched, and a first dielectric layer formed on the layer to be etched; forming a first trench through the first dielectric layer, the first trench extending along a second direction; forming a partition layer in the first trench, the material of the partition layer having an etching selectivity ratio with the material of the first dielectric layer; forming a second trench extending along a first direction in the first dielectric layer, in the first direction, the second trench is located on both sides of the partition layer, and the second trench exposes the sidewall of the partition layer, the first direction being perpendicular to the second direction; removing the layer to be etched at the bottom of the second trench with the partition layer as a mask, forming a third trench in the layer to be etched, in the first direction, adjacent third trenches are isolated by the layer to be etched below the partition layer; removing the partition layer, and forming a target structure in the third trench. The present application is advantageous to guarantee the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] With the gradual development of semiconductor process technology, semiconductor process nodes are continuously decreasing in size, following Moore's Law. To adapt to the shrinking process nodes and the increasing integration of semiconductor devices, the critical dimensions of metal-oxide-semiconductor (MOS) devices are also shrinking, and the spacing of interconnect structures is also decreasing to even smaller dimensions. Correspondingly, the manufacturing process of semiconductor devices is also constantly being improved to meet people's requirements for device performance.

[0003] Currently, in the fabrication of interconnect structures for MOS devices, a cut technique is typically used to sever the strip-shaped interconnect structure. The severed interconnect structure corresponds to different transistors, which can improve the transistor integration density. Furthermore, when multiple interconnect structures are arranged in a row along the extension direction, the cut technique can precisely reduce the spacing (Cut CD) between the disconnected interconnect structures after cutting. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a method for forming a semiconductor structure, thereby ensuring the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a layer to be etched, a first dielectric layer formed on the layer to be etched; forming a first trench penetrating the first dielectric layer, the first trench extending along a second direction; forming an isolation layer in the first trench, the material of the isolation layer having an etching selectivity ratio with the material of the first dielectric layer; forming a second trench in the first dielectric layer extending along the first direction, the second trench being located on both sides of the isolation layer in the first direction, and the second trench exposing the sidewalls of the isolation layer, the first direction being perpendicular to the second direction; using the isolation layer as a mask, removing the layer to be etched at the bottom of the second trench, forming a third trench in the layer to be etched, adjacent third trenches being isolated from each other by a layer to be etched below the isolation layer in the first direction; removing the isolation layer, and forming a target structure in the third trench.

[0006] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0007] In the forming method provided by this embodiment of the invention, a first trench penetrating the first dielectric layer is formed, and a partition layer is formed in the first trench. The material of the partition layer has an etching selectivity ratio with the material of the first dielectric layer. A second trench extending along a second direction is formed in the first dielectric layer. In the second direction, the second trench is located on both sides of the partition layer and exposes the sidewall of the partition layer. Using the partition layer as a mask, the layer to be etched at the bottom of the second trench is removed, and a third trench is formed in the layer to be etched. In the second direction, adjacent third trenches are isolated by the layer to be etched below the partition layer. By forming the first trench first and then forming the partition layer in the first trench, the forming steps of multiple partition layers do not interfere with each other, thus ensuring the first... When the trench dimension along the first direction is small, multiple isolation layers can be obtained at once. This not only simplifies the process steps and improves the process efficiency, but also improves the process feasibility of the formation method when the first trench is formed in multiple stages. In addition, the material of the isolation layer has an etching selectivity ratio with the material of the first dielectric layer. Therefore, in the step of forming the second trench extending along the second direction in the first dielectric layer, it is beneficial to reduce the damage to the isolation layer, thereby achieving a better isolation effect of the isolation layer on the second trench. Correspondingly, in the step of removing the layer to be etched at the bottom of the second trench using the isolation layer as a mask, the third trench also has a good isolation effect. Thus, the isolation effect between the target structures formed in the third trench is better, which helps to ensure the performance of the semiconductor structure. Attached Figure Description

[0008] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0009] Figures 4 to 18 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0010] The performance of semiconductor structures needs to be guaranteed. This paper analyzes the reasons for this performance guarantee by examining a semiconductor structure formation method.

[0011] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] refer to Figure 1 Provides base 11.

[0013] refer to Figures 1 to 3 Multiple partition layers 21 are formed on the substrate.

[0014] The step of forming one of the partition layers 21 includes: referencing Figure 1 A partition material layer 20 is formed on the substrate 11; Reference Figure 2 The partition material layer 20 is graphically represented to form the partition layer 21.

[0015] refer to Figure 3 The steps of forming the partition material layer 20 and graphically representing the partition material layer 20 are repeated to form a plurality of partition layers 21.

[0016] Forming multiple isolation layers 21 requires multiple cycles of forming isolation material layers 20 and patterning isolation material layers 20. The process steps are relatively complicated and the process efficiency is low. Moreover, in the later step of forming the isolation layer 21, the etching process of the isolation material layer 20 can easily damage or even remove the previously formed isolation layer 21, affecting the effect of the subsequent isolation layer 20 on the patterning of the substrate 10. This affects the isolation effect of the structure that needs to be isolated formed in the subsequent substrate 11, and thus makes it difficult to guarantee the performance of the semiconductor structure.

[0017] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a layer to be etched, a first dielectric layer formed on the layer to be etched; forming a first trench penetrating the first dielectric layer, the first trench extending along a second direction; forming an isolation layer in the first trench, the material of the isolation layer having an etching selectivity ratio with the material of the first dielectric layer; forming a second trench in the first dielectric layer extending along the first direction, the second trench being located on both sides of the isolation layer in the first direction, and the second trench exposing the sidewalls of the isolation layer, the first direction being perpendicular to the second direction; using the isolation layer as a mask, removing the layer to be etched at the bottom of the second trench, forming a third trench in the layer to be etched, adjacent third trenches being isolated from each other by a layer to be etched below the isolation layer in the first direction; removing the isolation layer, and forming a target structure in the third trench.

[0018] This invention, through the formation of a first trench followed by the formation of a barrier layer within that trench, ensures that the formation steps of multiple barrier layers do not interfere with each other. This allows for the simultaneous formation of multiple barrier layers while maintaining a relatively small dimension of the first trench along the first direction. This simplifies the process, improves efficiency, and enhances the feasibility of the formation method when the first trench is formed in multiple stages. Furthermore, the material of the barrier layer has an etching selectivity ratio with the material of the first dielectric layer. This reduces damage to the barrier layer during the formation of the second trench extending along the second direction within the first dielectric layer, resulting in a better barrier effect. Correspondingly, using the barrier layer as a mask, the layer to be etched at the bottom of the second trench is removed. During the formation of the third trench within this etched layer, the third trenches also exhibit good barrier effects. This results in a better barrier effect between the target structures formed in the third trenches, thereby contributing to the performance of the semiconductor structure.

[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0020] Figures 4 to 18 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0021] Reference Figure 4 and Figure 5 , Figure 4 This is a top view of the gate structure and the source / drain doped layers. Figure 5 for Figure 4 A cross-sectional view based on the AA direction is provided, the substrate 100 includes a layer 120 to be etched, and a first dielectric layer 300 is formed on the layer 120 to be etched.

[0022] Substrate 100 provides the basis for the process operation of semiconductor structure formation.

[0023] In this embodiment, the semiconductor structure includes an SRAM device.

[0024] In SRAM devices, multiple interconnect structures need to be formed to bring out the electrical properties of the transistor structure. The interconnect structure includes source-drain interconnect plugs. The source-drain interconnect plugs usually extend in the same direction, and the spacing between adjacent source-drain interconnect plugs extending in the same direction is small. Therefore, by using the cut technique of pre-embedded partition layer to separate adjacent source-drain interconnect plugs, the formation method of the present invention is particularly suitable.

[0025] It should be noted that this embodiment uses an SRAM device as an example for illustration. The embodiments of the present invention are not limited to SRAM devices and can also be applied to other semiconductor structures.

[0026] In this embodiment, the substrate 100 includes a plurality of components along a first direction (e.g., Figure 4 The transistor cell region 100c (shown in the X direction) is arranged in a substrate 110, and the substrate 100 further includes a substrate 110 and a transistor structure located on the substrate 110 of the transistor cell region 100c. The transistor structure includes a gate structure 140 extending along a first direction and source / drain doped layers 130 located on both sides of the gate structure 140.

[0027] Transistor cell region 100c is used to form transistor structure.

[0028] In this embodiment, the substrate 110 is made of silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0029] The gate structure 140 is used to control the opening or closing of the channel of the transistor structure.

[0030] The source / drain doped layer 130 is used as the source or drain region of the transistor structure. Specifically, the doping type of the source / drain doped region 130 is the same as the channel conductivity type of the corresponding transistor structure.

[0031] In this embodiment, the target structure formed subsequently is electrically connected to the source / drain doped layer 130, thereby bringing out the electrical properties of the source / drain doped layer 130.

[0032] Correspondingly, the layer to be etched 120 is the second dielectric layer 121 covering the transistor structure.

[0033] The etchable layer 120 is used to provide an operating platform for the subsequent formation of the third trench through etching. In this embodiment, the etchable layer 120 is the second dielectric layer 121. The etchable layer 120 is also used to achieve mutual isolation between the source and drain interconnect plugs.

[0034] In this embodiment, the material of the layer 120 to be etched includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0035] In this embodiment, a first dielectric layer 300 is formed on the etchable layer 120. The first dielectric layer 300 is used to provide an operating platform for the subsequent etching to form a first trench and then filling the first trench to form a partition layer.

[0036] In other embodiments, an etch stop layer may be formed between the layer to be etched and the first dielectric layer, serving as an etch stop point for subsequent etching of the first dielectric layer. The material of the etch stop layer includes aluminum oxide or aluminum nitride.

[0037] In this embodiment, the material of the first dielectric layer 300 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. As an example, the material of the first dielectric layer 300 is silicon oxide.

[0038] In this embodiment, a hard mask layer 200 is also formed between the etchable layer 120 and the first dielectric layer 300.

[0039] The hard mask layer 200 is used as an etching mask when transferring the pattern to the etchable layer 120. After the hard mask layer 200 is patterned, the pattern is transferred downward through the patterned hard mask layer 200. The hard mask layer 200 helps to further improve the stability of the patterning process and the accuracy of pattern transfer.

[0040] In this embodiment, the material of the hard mask layer 200 includes tungsten, titanium nitride, tantalum nitride, tantalum, or tungsten carbide.

[0041] Hard mask layers formed from tungsten, titanium nitride, tantalum nitride, tantalum, or tungsten carbide have high hardness, which helps to ensure the stability and accuracy of pattern transfer.

[0042] Reference Figure 6 and Figure 7 A first trench 310 is formed that penetrates the first dielectric layer 300, and the first trench 310 is along the second direction (e.g., Figure 4 (Extended in the Y direction as shown)

[0043] In this embodiment, one or more first grooves 310 are spaced apart in a first direction.

[0044] The first groove 310 is used to provide space for the subsequent formation of the partition layer.

[0045] In this embodiment, by first forming the first trench 310 and then forming the partition layer in the first trench 310, the formation steps of multiple partition layers do not interfere with each other. This allows multiple partition layers to be obtained at once while ensuring that the size of the first trench 310 along the first direction is small. This not only simplifies the process steps and improves the process efficiency, but also improves the process feasibility of the formation method when the first trench 310 is formed in multiple stages. Correspondingly, it also helps to improve the integrity of the partition layer formed in the first trench 310 in the subsequent stages.

[0046] In this embodiment, taking the formation of multiple first grooves 310 as an example, the multiple first grooves 310 are arranged at intervals in the first direction and extend along the second direction, so that multiple second grooves can be formed subsequently by the partition layer along the first direction.

[0047] Specifically, in this embodiment, forming a first trench 310 penetrating the first dielectric layer 300 includes: performing one or more patterning processes in the first dielectric layer 300 to form the first trench 310 in the first dielectric layer 300.

[0048] When the patterning process is performed multiple times, the first trench 310 is formed in different regions of the first dielectric layer 300.

[0049] By performing multiple patterning processes, multiple photomasks are used to form multiple first grooves 310, that is, the pattern of multiple first grooves 310 is split into multiple layouts and set in multiple photomasks, thereby meeting the requirement that the width of the first grooves 310 is small.

[0050] The patterning process includes: forming a first mask layer (not shown) covering the first dielectric layer 300; patterning the first mask layer to form a first opening (not shown) exposing the first dielectric layer 300, the first opening extending along a second direction; etching the first dielectric layer 300 along the first opening to form a first trench 310; and removing the first mask layer after forming the first trench 310.

[0051] The first mask layer is used as an etching mask to form the first opening. For example, the material of the first mask layer includes photoresist.

[0052] In this embodiment, a dry etching process is used to etch the first dielectric layer 300 to form one or more first trenches 310 that are spaced apart in a first direction and penetrate the first dielectric layer 300.

[0053] Dry etching is anisotropic, so by selecting dry etching, the etching becomes more directional, which is beneficial to improving the opening size accuracy of the first trench 310.

[0054] Therefore, as Figure 7 As shown, taking the formation of two first trenches 310 as an example, the patterning process is repeated twice to form the first trenches 310 in different regions of the first dielectric layer 300.

[0055] It should be noted that when multiple patterning processes are performed, the multiple patterning processes are used to form the first trench 310 in different regions of the first dielectric layer 300. Therefore, the impact on the already formed first trench 310 is small during the repeated patterning process.

[0056] In this embodiment, the width of the first groove 310 along the first direction is relatively small, making it difficult to form multiple patterns of the first groove 310 in the same photomask. Therefore, in this embodiment, multiple first grooves 310 are formed through multiple patterning processes.

[0057] In this embodiment, in the step of forming the first trench 310 that penetrates the first dielectric layer 300, the first trench 310 is located at the boundary of adjacent transistor cell regions 100c and above the second dielectric layer 121 between adjacent source and drain doped layers 130.

[0058] The first trench 310 is located at the boundary of adjacent transistor cell regions 100c and above the second dielectric layer 121 between adjacent source / drain doped layers 130. Correspondingly, the subsequently formed partition layer is located at the boundary of adjacent transistor cell regions 100c and above the second dielectric layer 121 between adjacent source / drain doped layers 130. Thus, when the pattern is transferred to the second dielectric layer 121 using the partition layer as a mask, a third trench located in adjacent transistor cell regions 100c and isolated from each other can be formed. At the same time, the third trench can expose the source / drain doped layer 130, and the target structure subsequently formed in the third trench can contact the source / drain doped layer 130.

[0059] Reference Figure 8 and Figure 9 An isolation layer 410 is formed in the first trench 310. The material of the isolation layer 410 has an etching selectivity ratio with the material of the first dielectric layer 300. The material of the isolation layer 410 is a metal, a metal compound, or a combination thereof.

[0060] The partition layer 410 is used to divide the second trench located on both sides of the partition layer 410 when a second trench extending in the first direction is subsequently formed in the first medium layer 300.

[0061] In this embodiment, the material of the isolation layer 410 has an etching selectivity ratio with the material of the first dielectric layer 300. Therefore, in the subsequent step of forming a second trench extending in the second direction in the first dielectric layer 300, it is beneficial to reduce damage to the isolation layer 410, thereby achieving a better isolation effect of the isolation layer 410 on the second trench. Correspondingly, in the subsequent step of using the isolation layer 410 as a mask to remove the bottom layer 120 of the second trench and forming a third trench in the layer 120 to be etched, the third trenches also have a good isolation effect. Thus, the isolation effect between the target structures formed in the third trenches is better, which is beneficial to ensuring the performance of the semiconductor structure.

[0062] It should be noted that the etching selectivity ratio of the materials of the first dielectric layer 300 to the partition layer 410 should not be too small. If the etching selectivity ratio of the materials of the first dielectric layer 300 to the partition layer 410 is too small, the partition layer 410 may be easily damaged during the subsequent step of forming the second trench extending in the second direction in the first dielectric layer 300, making it difficult to achieve a good isolation effect of the partition layer 410 on the second trench and affecting the performance of the semiconductor structure. Therefore, in this embodiment, the etching selectivity ratio of the materials of the first dielectric layer 300 to the partition layer 410 is greater than or equal to 3:1.

[0063] In this embodiment, the material of the partition layer 410 satisfies the following: the etching process of the hard mask layer 200 has an etching selectivity ratio for the hard mask layer 200 and the partition layer 410. Therefore, in the subsequent step of using the partition layer 410 as a mask to remove the hard mask layer 200 at the bottom of the second trench and forming the fourth trench in the hard mask layer 200, it is beneficial to reduce the damage to the partition layer 410. This is beneficial to achieve better pattern transfer from the partition layer 410 to the hard mask layer 200, and correspondingly achieves a better isolation effect of the hard mask layer 200 at the bottom of the partition layer 410 on the fourth trench.

[0064] It should be noted that the material of the isolation layer 410 satisfies the following condition: the etching selectivity ratio of the hard mask layer 200 to the isolation layer 410 in the etching process of the hard mask layer 200 should not be too small. If the etching selectivity ratio of the hard mask layer 200 to the isolation layer 410 in the etching process of the hard mask layer 200 is too small, then in the subsequent step of removing the hard mask layer 200 at the bottom of the second trench using the isolation layer 410 as a mask to form the fourth trench in the hard mask layer 200, the isolation layer 410 is easily damaged, affecting the pattern transfer from the isolation layer 410 to the hard mask layer 200. This makes it difficult to achieve a good isolation effect of the hard mask layer 200 at the bottom of the isolation layer 410 on the second trench, affecting the performance of the semiconductor structure. Therefore, in this embodiment, the etching selectivity ratio of the material of the hard mask layer 200 to the material of the isolation layer 410 is greater than or equal to 3:1.

[0065] In this embodiment, the material of the partition layer 410 also satisfies the following condition: the partition layer 410 and the hard mask layer 200 can be removed in the same wet etching process.

[0066] In this embodiment, the material of the partition layer 410 includes tungsten, titanium nitride, tantalum nitride, tantalum, or tungsten carbide. As an example, the material of the partition layer 410 is tungsten.

[0067] In this embodiment, the first dielectric layer 300 is made of silicon oxide, and the isolation layer 410 is made of tungsten, titanium nitride, tantalum nitride, tantalum, or tungsten carbide. Silicon oxide has a high etching selectivity with tungsten, titanium nitride, tantalum nitride, tantalum, or tungsten carbide. Therefore, in the subsequent step of forming the second trench extending along the second direction in the first dielectric layer 300, damage to the isolation layer 410 is reduced, thereby improving the isolation effect of the isolation layer 410 on the second trench. In this embodiment, the hard mask layer 200 is made of tungsten, titanium nitride, tantalum nitride, tantalum, or tungsten carbide. In the dry etching process, materials selected from tungsten, titanium nitride, tantalum nitride, tantalum, or tungsten carbide are all compatible with tungsten, titanium nitride, tantalum nitride, tantalum, or tungsten carbide. The presence of tantalum nitride, tantalum, or tungsten carbide provides a high etching selectivity. This allows for better pattern transfer from the partition layer 410 to the hard mask layer 200 at the bottom of the second trench, and in the subsequent step of forming the fourth trench within the hard mask layer 200, using the partition layer 410 as a mask. This reduces damage to the partition layer 410, resulting in better pattern transfer from the partition layer 410 to the hard mask layer 200, and consequently, a better isolation effect of the hard mask layer 200 at the bottom of the partition layer 410 on the fourth trench. Furthermore, in the wet etching process, tungsten, titanium nitride, tantalum nitride, tantalum, or tungsten carbide can all be removed along with the tungsten. This allows for the removal of the partition layer 410 and the hard mask layer 200 in the same step, improving process efficiency.

[0068] Specifically, in this embodiment, the step of forming the partition layer 410 includes: referencing Figure 8 This forms a partition material layer 400 covering the top of the first dielectric layer 300, and the bottom and sidewalls of the first trench 310; Reference Figure 9 The partition material layer 400 is flattened, the partition material layer 400 above the top of the first medium layer 300 is removed, and the partition material layer 400 located in the first groove 310 is retained as the partition layer 410.

[0069] In this embodiment, a chemical vapor deposition process is used to form the barrier material layer 400.

[0070] It should be noted that, in order to better deposit the partition material layer 400, an adhesive material is deposited on the sidewalls and bottom of the first trench 310 before depositing the partition material layer 400, which helps the partition material layer 400 to better adhere to the first trench 310.

[0071] Chemical vapor deposition (CVD) has good deposition effect, high gap filling ability, can form high-quality partition material layer 400, and can reduce the voids in partition material layer 400.

[0072] In this embodiment, a chemical mechanical polishing process is used to planarize the partition material layer 400.

[0073] Reference Figures 10 to 12A second groove 320 is formed in the first dielectric layer 300 extending along a first direction. In the first direction, the second groove 320 is located on both sides of the partition layer 410 and exposes the sidewall of the partition layer 410. The first direction is perpendicular to the second direction.

[0074] The second trench 320 is used for subsequent pattern transfer to the layer 120 to be etched.

[0075] In this embodiment, by first forming an isolation layer 410 and then forming a second trench 320 extending in the first direction in the first dielectric layer 300, a plurality of spaced second trenches 310 are obtained through the isolation layer 410. Compared with the scheme of first forming a connected trench and then dividing the trench into a plurality of second trenches by forming an isolation layer, this scheme is advantageous in that the spacing between adjacent second trenches 320 along the first direction is smaller, thereby improving the integration of the semiconductor structure.

[0076] In this embodiment, a dry etching process is used to etch the first dielectric layer 300 to form a second trench 320 extending along a first direction in the first dielectric layer 300.

[0077] Dry etching is anisotropic, so by selecting dry etching, the etching is more directional and can achieve a fairly accurate pattern transformation, which is beneficial to improving the opening size accuracy of the second trench 320.

[0078] Specifically, the step of forming a second trench 320 extending in a first direction in the first dielectric layer 300 includes: referencing Figure 10 This forms a second mask layer 500 covering the first dielectric layer 300 and the isolation layer 410.

[0079] The second mask layer 500 is used as an etching mask for subsequent etching of the first dielectric layer 300. For example, the material of the second mask layer 500 includes a planarization material.

[0080] refer to Figure 11 The second mask layer 500 is patterned to form a second opening 520 across the partition layer 410, the second opening 520 exposing a portion of the top of the partition layer 410.

[0081] The second opening 520 is used as a mask opening for forming the second trench 320. The second opening 520 exposes part of the top of the partition layer 410. When the first dielectric layer 300 is etched along the second opening 520, the partition layer 410 can divide the second trench 320 located on both sides of the partition layer 410.

[0082] Specifically, the step of patterning the second mask layer 500 includes: forming a patterned photoresist on the second mask layer 500; and patterning the second mask layer 500 using the patterned photoresist as a mask.

[0083] refer to Figure 12 The first dielectric layer 300 is etched along the second opening 520 to form the second trench 320.

[0084] In this embodiment, the partition layer 410 and the first dielectric layer 300 have an etching selectivity ratio, so that in the step of etching the first dielectric layer 300 along the second opening 520 to form the second trench 320, the first dielectric layer 300 can be etched while the partition layer 410 is retained, so that the partition layer 410 can divide the second trench 320 located on both sides of the partition layer 410.

[0085] refer to Figure 13 After forming the second trench 320 extending in the first direction in the first dielectric layer 300, before removing the etchable layer 120 at the bottom of the second trench 320 using the partition layer 410 as a mask, the method further includes: removing the hard mask layer 200 at the bottom of the second trench 320 using the partition layer 410 as a mask, forming a fourth trench 210 in the hard mask layer 200, wherein adjacent fourth trenches 210 are isolated from each other in the first direction by the hard mask layer 200 below the partition layer 410.

[0086] The fourth trench 210 is used for subsequent pattern transfer to the layer 120 to be etched.

[0087] In this embodiment, by forming a fourth trench 210 in the hard mask layer 200 and then transferring the pattern through the fourth trench 210, the hard mask layer 200 is used to improve the stability of the patterning process and the accuracy of the pattern transfer.

[0088] In this embodiment, a dry etching process is used to remove the hard mask layer 200 at the bottom of the second trench 320, and a fourth trench 210 is formed in the hard mask layer 200.

[0089] Dry etching is anisotropic, so by selecting dry etching, the etching is more directional and can achieve a fairly accurate pattern transformation, which is beneficial to improving the opening size accuracy of the fourth trench 210.

[0090] refer to Figure 14 In this embodiment, after the second trench 320 is formed and before the third trench is formed, the method further includes: removing the second mask layer 510 to prepare for the subsequent removal of the first dielectric layer 300.

[0091] Specifically, in this embodiment, after the fourth trench 210 is formed and before the third trench is formed, the second mask layer 510 is removed, thereby reducing the height difference of the etching mask protruding from the etchable layer 120, so that the etching consistency of the third trench is better.

[0092] In this embodiment, after removing the second mask layer 510 and before forming the third trench, the first dielectric layer 300 is removed to prepare for the subsequent etching of the layer to be etched 120 to form the third trench.

[0093] refer to Figure 15 Using the partition layer 410 as a mask, the bottom of the second trench 320 is removed from the etchable layer 120, and a third trench 150 is formed in the etchable layer 120. In the first direction, adjacent third trenches 150 are isolated by the etchable layer 120 below the partition layer 410.

[0094] The third trench 150 is used to provide spatial location for the subsequent formation of the target structure.

[0095] In this embodiment, a dry etching process is used to remove the etchable layer 120 at the bottom of the second trench 320, and a third trench 150 is formed in the etchable layer 120.

[0096] Dry etching is anisotropic, so by selecting dry etching, the etching is more directional and can achieve a fairly accurate pattern transformation, which is beneficial to improving the opening size accuracy of the third trench 150.

[0097] Specifically, in this embodiment, in the step of removing the etchable layer 120 at the bottom of the second trench 320 using the partition layer 410 as a mask, the etchable layer 120 at the bottom of the fourth trench 210 is removed to form the third trench 150.

[0098] Using the fourth trench 210 in the hard mask layer 200 for pattern transfer is beneficial to improving the stability of the patterning process and the accuracy of pattern transfer.

[0099] In this embodiment, in the step of using the partition layer 410 as a mask to remove the bottom layer 120 of the second trench 320 and forming the third trench 150 in the layer 120 to be etched, the third trench 150 penetrates the second dielectric layer 130 above the source / drain doped layer 130 and exposes the top of the source / drain doped layer 130.

[0100] The third trench 150 penetrates the second dielectric layer 130 above the source / drain doped layer 130, exposing the top of the source / drain doped layer 130, so that the target structure formed subsequently is in contact with the source / drain doped layer 130.

[0101] refer to Figure 16 Remove the partition layer 410.

[0102] The partition layer 410 is removed to prepare for the subsequent formation of the target structure in the third trench 150, thus avoiding the impact of the presence of the partition layer 410 on the process of forming the target structure.

[0103] In this embodiment, a wet etching process is used to remove the partition layer 410.

[0104] Wet etching has the characteristics of isotropic etching, which is beneficial to remove the barrier layer 410 cleanly. Moreover, wet etching has a relatively low cost and simple operation steps, and can achieve a large etching selectivity, which is beneficial to reduce the damage to the layer 120 to be etched and the source / drain doped layer 130 during the removal of the barrier layer 410.

[0105] In this embodiment, after the third trench 150 is formed and before the target structure is formed, the process further includes: removing the hard mask layer 200.

[0106] The hard mask layer 200 is removed to prepare for the subsequent formation of the target structure in the third trench 150, thus avoiding the influence of the presence of the hard mask layer 200 on the process of forming the target structure.

[0107] In this embodiment, a wet etching process is used to remove the hard mask layer 200.

[0108] Wet etching has the characteristics of isotropic etching, which is beneficial to remove the hard mask layer 200 cleanly. Moreover, wet etching has a relatively low cost and simple operation steps, and can achieve a large etching selectivity, which is beneficial to reduce the damage to the layer 120 to be etched and the source / drain doped layer 130 during the removal of the hard mask layer 200.

[0109] In this embodiment, the partition layer 410 and the hard mask layer 200 are removed in the same step, thereby simplifying the process flow, saving process costs, and improving process efficiency.

[0110] In this embodiment, the material of the partition layer 410 is tungsten, and the material of the hard mask layer 200 includes tungsten, titanium nitride, tantalum nitride, tantalum or tungsten carbide. Tungsten and tungsten, titanium nitride, tantalum nitride, tantalum or tungsten carbide can be removed simultaneously by a wet etching process, so that the partition layer 410 and the hard mask layer 200 can be removed in the same step.

[0111] In this embodiment, in the step of removing the barrier layer 410 using a wet etching process, the etching solution of the wet etching process includes one or more of the following: APM solution, SPM solution, DIW solution, DPM solution, tannic acid solution, hexadecyl (alkyl) solution, trimethylamine solution, or p-xylenesulfonic acid solution.

[0112] Among them, APM solution is composed of a certain proportion of NH4OH solution and H2O2 solution, SPM solution is composed of a certain proportion of H2SO4 solution and H2O2 solution, DIW solution is deionized water, and DPM solution is dipropylene glycol methyl ether metal cleaner. All of the above solutions can remove tungsten, titanium nitride, tantalum nitride, tantalum or tungsten carbide at the same time.

[0113] Reference Figure 17 and Figure 18 , Figure 18 for Figure 17 The top view shows that after removing the partition layer 410, the target structure 160 is formed in the third trench 150.

[0114] In this embodiment, in the first direction, adjacent third trenches 150 are isolated by the etchable layer 120 below the partition layer 410. Correspondingly, in the first direction, adjacent target structures 160 are isolated by the etchable layer 120 below the partition layer 410.

[0115] In this embodiment, in the step of forming the target structure 160 in the third trench 150, the target structure 160 is a source-drain interconnect plug.

[0116] Source-drain interconnect plugs are used to bring out the electrical properties of the source-drain doped layer 130.

[0117] In this embodiment, the process for forming the source-drain interconnect plug includes chemical vapor deposition or physical vapor deposition.

[0118] In this embodiment, the source-drain interconnect plug is made of tungsten. In other embodiments, the source-drain interconnect plug may also be made of cobalt or ruthenium.

[0119] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a layer to be etched, on which a first dielectric layer is formed; A first trench is formed that penetrates the first dielectric layer, and the first trench extends along a second direction; An isolation layer is formed in the first trench, wherein the material of the isolation layer has an etching selectivity ratio with the material of the first dielectric layer, and the etching selectivity ratio of the material of the first dielectric layer to the material of the isolation layer is greater than or equal to 3:

1. A second trench is formed in the first dielectric layer extending along a first direction. In the first direction, the second trench is located on both sides of the partition layer and exposes the sidewall of the partition layer. The first direction is perpendicular to the second direction. Using the partition layer as a mask, the etchable layer at the bottom of the second trench is removed, and a third trench is formed in the etchable layer. In the first direction, adjacent third trenches are isolated from each other by the etchable layer below the partition layer. Remove the partition layer and form the target structure in the third trench.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the partition layer is a metal, a metal compound, or a combination thereof.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the partition layer includes tungsten, titanium nitride, tantalum nitride, tantalum, or tungsten carbide.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, a hard mask layer is also formed between the layer to be etched and the first dielectric layer, and the material of the hard mask layer is a metal, a metal compound, or a combination thereof; In the step of forming a partition layer in the first trench, the material of the partition layer satisfies the condition that the etching process of the hard mask layer has an etching selectivity ratio for the hard mask layer and the partition layer.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, Using the partition layer as a mask, removing the layer to be etched at the bottom of the second trench includes: using the partition layer as a mask, removing the hard mask layer at the bottom of the second trench, forming a fourth trench in the hard mask layer, and in the first direction, adjacent fourth trenches are isolated from each other by a hard mask layer below the partition layer; Remove the layer to be etched at the bottom of the fourth trench to form the third trench; After the third trench is formed but before the target structure is formed, the process further includes removing the hard mask layer.

6. The method for forming a semiconductor structure as described in claim 4, characterized in that, The etching process of the hard mask layer has an etching selectivity ratio of 3:1 for the hard mask layer and the isolation layer.

7. The method for forming a semiconductor structure as described in claim 4, characterized in that, The material of the hard mask layer includes tungsten, titanium nitride, tantalum nitride, tantalum, or tungsten carbide.

8. The method for forming a semiconductor structure as described in claim 4, characterized in that, In the same step, the partition layer is removed, and the hard mask layer is also removed.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The partition layer is removed using a wet etching process.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The etching solution used in the wet etching process includes one or more of the following: APM solution, SPM solution, DIW solution, DPM solution, tannic acid solution, hexadecyl (alkyl) solution, trimethylamine solution, or p-xylenesulfonic acid solution.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, Forming a first trench penetrating the first dielectric layer includes: performing one or more patterning processes in the first dielectric layer to form the first trench in the first dielectric layer.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, When the patterning process is performed multiple times, first trenches are formed in different regions of the first dielectric layer.

14. The method for forming a semiconductor structure as described in claim 12, characterized in that, The patterning process includes: forming a first mask layer covering the first dielectric layer; The first mask layer is patterned to form a first opening that exposes the first dielectric layer, and the first opening extends along the second direction; The first dielectric layer is etched along the first opening to form the first trench; After the first trench is formed, the first mask layer is removed.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a second trench extending along the first direction in the first dielectric layer includes: forming a second mask layer covering the first dielectric layer and the partition layer; The second mask layer is patterned to form a second opening across the partition layer, the second opening exposing a portion of the top of the partition layer; The first dielectric layer is etched along the second opening to form the second trench.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, Before forming the third trench, the process further includes: removing the second mask layer and removing the first dielectric layer.

17. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing a substrate, the substrate includes a plurality of transistor cell regions arranged along the first direction, the substrate also includes a substrate and a transistor structure located on the substrate of the transistor cell regions, the transistor structure includes a gate structure extending along the first direction and source / drain doped layers located on both sides of the gate structure, and the layer to be etched is a second dielectric layer covering the transistor structure. In the step of forming one or more first trenches spaced apart in a first direction through the first dielectric layer, the first trenches are located at the boundary of adjacent transistor cell regions and above the second dielectric layer between adjacent source and drain doped layers. In the step of removing the etchable layer at the bottom of the second trench using the isolation layer as a mask, and forming a third trench in the etchable layer, the third trench penetrates the second dielectric layer above the source / drain doped layer and exposes the top of the source / drain doped layer. In the step of forming the target structure in the third trench, the target structure is a source-drain interconnect plug.

18. The method for forming a semiconductor structure as described in claim 1 or 17, characterized in that, The semiconductor structure includes an SRAM device.

Images