High-efficiency heterojunction solar cell, preparation method thereof and photovoltaic module

Abstract

The application discloses a kind of high-efficiency heterojunction solar cell and its preparation method, photovoltaic module, belong to heterojunction battery technical field, including silicon base, its front and back are provided with intrinsic amorphous silicon layer, doped layer, transparent conductive film layer and metal electrode;Transparent conductive film layer includes first film area and second film area, the carrier concentration of first film area is less than the carrier concentration of second film area, the transmittance of first film area is greater than the transmittance of second film area, and the work function of first film area is different from the work function of second film area.Set first film area and second film area on transparent conductive film, and control the carrier concentration, transmittance and work function of second film area and first film area, while reducing the contact resistance of transparent conductive film and metal, without affecting the nature of transparent conductive film in light area, so as to improve the fill factor of cell, to improve the purpose of cell conversion efficiency.

Description

Technical Field

[0001] This invention relates to the field of heterojunction solar cell technology, and more specifically, to a high-efficiency heterojunction solar cell and its preparation method, as well as a photovoltaic module. Background Technology

[0002] With the rapid development of the photovoltaic industry, the conversion efficiency of heterojunction cells has gradually improved. However, in terms of manufacturing cost, it still does not have an advantage compared to other technologies such as PERC and TOPCon. This is mainly due to the high cost of metallization. The reason is that the structure and principle of heterojunction cells determine that they can usually only use low-temperature silver paste, which is expensive.

[0003] To reduce metallization costs, current main approaches include using low-silver-content pastes or copper electroplating. Low-silver-content pastes use other inexpensive metals to replace some of the silver without affecting conductivity. However, current testing shows that low-silver-content pastes do not perform as well as pure silver pastes in terms of contact resistance. Especially with further reductions in silver content, both bulk resistance and contact resistance decrease, affecting contact performance and resulting in a low fill factor in battery performance. Copper electroplating uses chemical electroplating to form copper electrodes on the battery surface. Because the formed copper electrodes have low bulk resistance, low contact resistance, and high aspect ratio, their fill performance is also improved. Furthermore, copper is much cheaper than silver, making it one of the main technologies for future cost reduction. However, copper electroplating involves masking, and the electrode performance is closely related to the effectiveness of the mask. The proportions of chemical solutions and additives also significantly affect performance. Currently, the development costs of masks and additives remain high, and the process yield is low, involving chemical discharge, all of which restrict its mass production and widespread adoption.

[0004] In existing technologies, much research focuses on the gradual replacement of pure silver paste with low-silver paste. However, since the contact resistance of the metal electrode formed by low-silver paste is slightly higher than that of pure silver paste, the battery fill factor decreases, which in turn leads to a slight decrease in battery efficiency. Although this reduces costs, it also results in some loss of efficiency. Therefore, other methods are needed to reduce contact resistance and improve conductivity.

[0005] For example, the invention patent CN103985778B discloses a heterojunction solar cell with a selective emitter and its fabrication method. The cell performance is improved by adding a selective emitter. However, this is achieved by placing multiple heavily doped P-type amorphous silicon monomers at the contact area between the front transparent conductive film layer and the lightly doped P-type amorphous silicon layer, each corresponding to a grid line of the front silver gate and located directly below the corresponding grid line, thus forming a selective contact. The heavily doped region is achieved through a mask, which presents several problems. First, the mask material increases cost. Second, it adds a PECVD coating process, and the high cost of PECVD equipment further increases costs. Third, there is the issue of mask precision; if the mask and substrate do not adhere well, there will be issues with metallization around the substrate. Since the metallization spacing is very small, the metallization around the substrate may cover this area, essentially rendering the mask ineffective. If a good fit is required, the mask needs to be ultra-thin, which significantly increases the cost. Summary of the Invention

[0006] To overcome the problems of existing heterojunction solar cells, which can only use low-temperature silver paste and have higher metallization costs compared to other technologies such as PERC and TOPCon, and whose efficiency is reduced by using low-silver-content pastes, this invention provides a high-efficiency heterojunction solar cell and its fabrication method. It compensates for contact losses from the perspective of a transparent conductive film and reduces the metallization contact resistance without affecting the transmittance of the transparent conductive film, thereby improving cell efficiency. The specific technical solution is as follows:

[0007] A high-efficiency heterojunction solar cell includes a silicon substrate, wherein a front intrinsic amorphous silicon layer, a front doped layer, a front transparent conductive thin film layer and a front metal electrode are sequentially disposed on the front side of the silicon substrate; and a back intrinsic amorphous silicon layer, a back doped layer, a back transparent conductive thin film layer and a back metal electrode are sequentially disposed on the back side.

[0008] Both the front transparent conductive film layer and the back transparent conductive film layer include a first film region and a second film region. The carrier concentration of the first film region is lower than that of the second film region, the transmittance of the first film region is greater than that of the second film region, and the work function of the first film region is different from that of the second film region.

[0009] To compensate for contact losses from the perspective of transparent conductive films, it is necessary to increase the carrier concentration of the transparent conductive film to reduce sheet resistance, thereby reducing Rs loss and achieving FF improvement. However, increasing the carrier concentration of the transparent conductive film will affect the transmittance of the transparent conductive film, resulting in reduced transmitted light and ultimately leading to Isc loss.

[0010] This approach takes a different approach, setting a first thin film region and a second thin film region on a transparent conductive film, and controlling the carrier concentration, transmittance, and work function of the second thin film region and the first thin film region. While reducing the contact resistance between the transparent conductive film and the metal, it does not affect the properties of the transparent conductive film in the light-exposed area, thereby improving the fill factor of the battery and achieving the goal of improving the battery conversion efficiency.

[0011] Preferably, the carrier concentration in the first thin film region is 5-15e19cm. -3 The carrier concentration in the second thin film region is 10⁻³⁰e¹⁹cm⁻¹ -3 .

[0012] Preferably, the transparent conductive film in the first thin film region has a transmittance of 85-95% in the wavelength range of 400-800nm, and the transparent conductive film in the second thin film region has a transmittance of 75-85% in the wavelength range of 400-800nm.

[0013] Preferably, the sheet resistance of the first thin film region is greater than that of the second thin film region, and satisfies the following conditions: the sheet resistance of the first thin film region is 50-150 ohms, and the sheet resistance of the second thin film region is 10-100 ohms.

[0014] Preferably, of the front doped layer and the back doped layer, one layer is an n-type doped layer formed by n-type doped amorphous silicon, microcrystalline silicon, nanocrystalline silicon, silicon oxide or silicon carbide, and the other layer is a p-type doped layer formed by p-type doped amorphous silicon, microcrystalline silicon, nanocrystalline silicon, silicon oxide or silicon carbide.

[0015] The work function of the first thin film region covering the surface of the n-type doped layer is less than the work function of the second thin film region, and / or the work function of the first thin film region covering the surface of the p-type doped layer is greater than the work function of the second thin film region.

[0016] Preferably, the work function of the first thin film region covering the surface of the n-type doped layer is less than the work function of the second thin film region, and the work function of the second thin film region is less than or equal to the work function of the metal electrode;

[0017] Alternatively, the work function of the first thin film region covering the surface of the p-type doped layer is greater than the work function of the second thin film region, and the work function of the second thin film region is greater than or equal to the work function of the metal electrode.

[0018] This invention also provides a method for preparing a high-efficiency heterojunction solar cell, comprising the following steps:

[0019] Step 1: Double-sided texturing of the silicon wafer forms a surface with a light-trapping structure;

[0020] Step 2: Intrinsic amorphous silicon is formed on the front and back sides of the silicon wafer, and an n-type doped layer and a p-type doped layer are formed on the intrinsic amorphous silicon on the front and back sides, respectively; wherein the n-type doped layer is n-type doped amorphous silicon, microcrystalline silicon, nanocrystalline silicon, silicon oxide or silicon carbide, and the p-type doped layer is p-type doped amorphous silicon, microcrystalline silicon, nanocrystalline silicon, silicon oxide or silicon carbide.

[0021] Step 3: Form transparent conductive films on the surfaces of the n-type doped layer and the p-type doped layer respectively, and anneal the transparent conductive films in the metal-covered area by patterned photoheating.

[0022] Step 4: Form metal electrodes on the metal-covered areas of the transparent conductive film on both the front and back sides.

[0023] By using patterned photoheating, the transparent conductive film in the metal contact area is locally thermally annealed to increase the carrier concentration and reduce the sheet resistance, thereby reducing the contact resistance between the transparent conductive film and the metal.

[0024] Preferably, in step three, a transparent conductive film is formed on the surface of the n-type doped layer and the p-type doped layer respectively using a PVD coating process, wherein the substrate temperature is 100-200℃ and the O2 / Ar flow ratio is 1-10%.

[0025] Preferably, in step three, the light source for the patterned light heating method is one of infrared laser, ultraviolet laser, white light source, or microwave.

[0026] Preferably, in step three, the patterned photothermal heating method uses a square, circular, or elliptical light spot with a spot size of 30-100 μm and a power per unit area of ​​2-100 J / cm². 2 By adjusting the light energy and the light spot size, the carrier concentration can be controlled to achieve the optimal sheet resistance.

[0027] Preferably, the metal electrode is pure silver or low-silver metal.

[0028] Beneficial effects:

[0029] The beneficial effects of adopting the technical solution of this invention are as follows:

[0030] (1) A first thin film region and a second thin film region are set on a transparent conductive film, and the carrier concentration, transmittance and work function of the second thin film region and the first thin film region are controlled. While reducing the contact resistance between the transparent conductive film and the metal, the properties of the transparent conductive film in the light-visible area are not affected, thereby improving the fill factor of the battery and achieving the purpose of improving the battery conversion efficiency.

[0031] (2) By adjusting the PVD process and adjusting the light energy and spot size, the work function of the transparent conductive film can be controlled, the contact barrier between the materials in each layer can be reduced, thereby reducing the contact resistance, increasing the fill factor of the battery, and achieving the goal of improving the battery conversion efficiency. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort.

[0033] Figure 1 This is a preferred heterojunction solar cell layer structure diagram of the present invention;

[0034] Figure 2 This is a flowchart illustrating the preferred process for fabricating a heterojunction solar cell according to the present invention.

[0035] Figure 3 This is a schematic diagram showing the work function relationship of each structural layer on the corresponding side of the n-type doped layer in a silicon substrate.

[0036] Figure 4 This is a schematic diagram showing the work function relationship of each structural layer on the corresponding side of the p-type doped layer in a silicon substrate.

[0037] In the figure, 1 is the silicon substrate; 2 is the front intrinsic amorphous silicon layer; 3 is the front doped layer; 4 is the front transparent conductive thin film layer; 5 is the front metal electrode; 6 is the back intrinsic amorphous silicon layer; 7 is the back doped layer; 8 is the back transparent conductive thin film layer; 9 is the back metal electrode; 11 is the first thin film region; and 12 is the second thin film region. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to represent selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0039] In this embodiment, a first thin film region and a second thin film region are formed on a transparent conductive film, and the carrier concentration, transmittance and work function of the second thin film region and the first thin film region are controlled. While reducing the contact resistance between the transparent conductive film and the metal, the properties of the transparent conductive film in the light-exposed area are not affected, thereby improving the fill factor of the battery and achieving the purpose of improving the battery conversion efficiency.

[0040] like Figure 1 As shown, a high-efficiency heterojunction solar cell includes a silicon substrate 1, which can be an n-type silicon substrate or a p-type silicon substrate. The front side of the silicon substrate 1 is sequentially provided with a front intrinsic amorphous silicon layer 2, a front doped layer 3, a front transparent conductive thin film layer 4, and a front metal electrode 5; the back side is sequentially provided with a back intrinsic amorphous silicon layer 6, a back doped layer 7, a back transparent conductive thin film layer 8, and a back metal electrode 9.

[0041] Both the front transparent conductive thin film layer 4 and the back transparent conductive thin film layer 8 include a first thin film region 11 and a second thin film region 12. The carrier concentration of the first thin film region 11 is less than that of the second thin film region 12, and the transmittance of the first thin film region 11 is greater than that of the second thin film region 12. Furthermore, the work function of the first thin film region 11 is different from that of the second thin film region 12.

[0042] In a preferred embodiment, the carrier concentration in the first thin film region 11 is 5-15e19cm. -3 The carrier concentration in the second thin film region 12 is 10⁻³⁰e¹⁹cm⁻¹. -3 .

[0043] In a preferred embodiment, the transparent conductive film in the first thin film region 11 has a transmittance of 85-95% in the wavelength range of 400-800nm, and the transparent conductive film in the second thin film region 12 has a transmittance of 75-85% in the wavelength range of 400-800nm.

[0044] In a preferred embodiment, the sheet resistance of the first thin film region 11 is greater than that of the second thin film region 12, and satisfies the following conditions: the sheet resistance of the first thin film region 11 is 50-150 ohms, and the sheet resistance of the second thin film region 12 is 10-100 ohms.

[0045] In a preferred embodiment, of the front doped layer 3 and the back doped layer 7, one layer is an n-type doped layer formed by n-type doped amorphous silicon, microcrystalline silicon, nanocrystalline silicon, silicon oxide or silicon carbide, and the other layer is a p-type doped layer formed by p-type doped amorphous silicon, microcrystalline silicon, nanocrystalline silicon, silicon oxide or silicon carbide.

[0046] like Figure 3 and 4As shown, the work function Φ of the first thin film region 11 covering the surface of the n-type doped layer is... TCO The work function Φ of the second thin film region 12 is less than TCO-金属 , and / or the work function Φ of the first thin film region 11 covering the surface of the p-type doped layer TCO The work function Φ of the second thin film region 12 is greater than that of the second thin film region. TCO-金属 .

[0047] As a preferred embodiment, the work function Φ of the first thin film region 11 covering the surface of the n-type doped layer is... TCO The work function Φ of the second thin film region 12 is less than TCO-金属 Furthermore, the work function of the second thin film region 11 is less than or equal to the work function Φ of the metal electrode. 金属 ;

[0048] Or the work function Φ of the first thin film region covering the surface of the p-type doped layer TCO The work function Φ of the second thin film region is greater than that of the second thin film region. TCO-金属 And the work function Φ of the second thin film region TCO-金属 The work function Φ of the metal electrode is greater than or equal to that of the metal electrode. 金属 .

[0049] This embodiment also provides a method for preparing a high-efficiency heterojunction solar cell, comprising the following steps:

[0050] Step S101: Double-sided texturing of the silicon wafer forms a surface with a light-trapping structure; alkaline texturing is used.

[0051] Step S102: Intrinsic amorphous silicon is formed on the front and back sides of the silicon wafer by PECVD, and an n-type doped layer and a p-type doped layer are formed on the intrinsic amorphous silicon on the front and back sides by PECVD, respectively; wherein the n-type doped layer is n-type doped amorphous silicon, microcrystalline silicon, nanocrystalline silicon, silicon oxide or silicon carbide, and the p-type doped layer is p-type doped amorphous silicon, microcrystalline silicon, nanocrystalline silicon, silicon oxide or silicon carbide;

[0052] Specifically, intrinsic amorphous silicon can be formed on the back side first, and then intrinsic amorphous silicon can be formed on the front side. It can be formed in one or more steps to form a single layer or multiple layers of intrinsic amorphous silicon. The difference between multilayer amorphous silicon lies in the different SiH4 / H2 flow ratio, pressure, temperature or power used.

[0053] The front side is formed with n-type doped amorphous silicon, microcrystalline silicon, nanocrystalline silicon, silicon oxide or silicon carbide, and the back side is formed with p-type doped amorphous silicon, microcrystalline silicon, nanocrystalline silicon, silicon oxide or silicon carbide. Generally, it is a multilayer doped layer, but it can also be a single-layer doped layer. The difference between multilayer amorphous silicon lies in the different SiH4 / H2 / doped gas flow ratio, pressure, temperature or power.

[0054] Step S103: A transparent conductive film is formed on the surface of the n-type doped layer and the p-type doped layer by PVD, and the transparent conductive film in the metal-covered area is annealed by patterned photoheating.

[0055] Step S104: Form metal electrodes on the metal-covered areas of the transparent conductive film surfaces on the front and back sides.

[0056] By using patterned photoheating, the transparent conductive film in the metal contact area is locally thermally annealed to increase the carrier concentration and reduce the sheet resistance, thereby reducing the contact resistance between the transparent conductive film and the metal. At the same time, the further activation of carriers and the crystallization transformation of the film layer achieve the purpose of adjusting the transmittance and work function.

[0057] In a preferred embodiment, step S103 involves forming transparent conductive films on the surfaces of the n-type doped layer and the p-type doped layer using a PVD deposition process, wherein the substrate temperature is 100-200°C and the O2 / Ar flow ratio is 1-10%. Specifically, the thickness of the transparent conductive film is 70-90 nm, and the carrier concentration is 5-15e19 cm⁻¹. -3 Its transmittance in the wavelength range of 400-800nm ​​is 85-95%; its sheet resistance is 50-150 ohms.

[0058] As a preferred embodiment, the patterned light heating method in step S103 uses an infrared laser, an ultraviolet laser, a white light source, or a microwave as its light source.

[0059] In a preferred embodiment, the patterned photothermal heating method in step S103 uses a square, circular, or elliptical light spot with a spot size of 30-100 μm and a power per unit area of ​​2-100 J / cm². 2 By adjusting the light energy and spot size, the carrier concentration can be controlled to achieve optimal sheet resistance; the carrier concentration of the treated transparent conductive film is 10⁻³⁰e¹⁹cm⁻¹. -3 Its transmittance in the wavelength range of 400-800nm ​​is 75-85%, and its sheet resistance is 10-100 ohms.

[0060] In a preferred embodiment, the metal electrode can be pure silver or low-silver metal formed by screen printing, or other metal formed by electroplating; it covers the front and back sides of the silicon wafer. Generally, the front gate line width is 15-50µm, and the back line width is 30-80µm.

[0061] The beneficial effects of the heterojunction solar cell and its preparation method in this embodiment will be further evaluated below through examples and comparative examples.

[0062] Example 1:

[0063] A method for fabricating a heterojunction solar cell includes the following steps:

[0064] Step 1: Use alkaline texturing to texture both sides of the silicon wafer to form a surface with a light-trapping structure;

[0065] Step 2: Intrinsic amorphous silicon is formed on the front and back sides of the silicon wafer by PECVD. An n-type doped layer is formed on the front intrinsic amorphous silicon by PECVD, and a p-type doped layer is formed on the back intrinsic amorphous silicon by PECVD.

[0066] Step 3: Transparent conductive films are formed on the surfaces of the n-type doped layer and the p-type doped layer respectively using a PVD coating process. The thickness of the resulting transparent conductive films is 80 nm, and the carrier concentration is 10e19 cm⁻¹. -3 Its transmittance is 92% in the wavelength range of 400-800nm; its sheet resistance is 100 ohms.

[0067] The transparent conductive film covering the metal area was annealed using patterned photothermal heating; the substrate temperature was 150℃, and the O2 / Ar flow ratio was 5%. An infrared laser was used as the light source, with a square spot size of 30µm on the front and 60µm on the back, and a power per unit area of ​​50J / cm². 2 The carrier concentration of the treated transparent conductive film is 20e19cm⁻¹. -3 Its transmittance is 80% in the wavelength range of 400-800nm, and its sheet resistance is 50 ohms.

[0068] Step 4: Use screen printing to form pure silver metal electrodes on the metal-covered areas of the transparent conductive film on the front and back sides; the front grid line width is 30um and the back line width is 60um.

[0069] The work function relationship of each structural layer on the corresponding side of the n-type doped layer satisfies: work function of the first thin film region < work function of the second thin film region ≤ work function of the metal electrode.

[0070] The work function relationship of each structural layer on the corresponding side of the p-type doped layer satisfies: the work function of the first thin film region is greater than the work function of the second thin film region and is greater than or equal to the work function of the metal electrode.

[0071] Example 2:

[0072] A method for fabricating a heterojunction solar cell includes the following steps:

[0073] Step 1: Use alkaline texturing to texture both sides of the silicon wafer to form a surface with a light-trapping structure;

[0074] Step 2: Intrinsic amorphous silicon is formed on the front and back sides of the silicon wafer by PECVD. A p-type doped layer is formed on the front intrinsic amorphous silicon by PECVD, and an n-type doped layer is formed on the back intrinsic amorphous silicon by PECVD.

[0075] Step 3: Transparent conductive films are formed on the surfaces of the n-type doped layer and the p-type doped layer respectively using a PVD coating process. The thickness of the resulting transparent conductive films is 80 nm, and the carrier concentration is 10e19 cm⁻¹. -3 Its transmittance is 92% in the wavelength range of 400-800nm; its sheet resistance is 100 ohms.

[0076] The transparent conductive film covering the metal area was annealed using patterned photothermal heating; the substrate temperature was 150℃, and the O2 / Ar flow ratio was 5%. An ultraviolet laser was used as the light source, with a circular spot size of 30µm on the front and 60µm on the back, and a power per unit area of ​​50J / cm². 2 The carrier concentration of the treated transparent conductive film is 20e19cm⁻¹. -3 Its transmittance is 80% in the wavelength range of 400-800nm, and its sheet resistance is 50 ohms.

[0077] Step 4: Use screen printing to form pure silver metal electrodes on the metal-covered areas of the transparent conductive film on the front and back sides; the front grid line width is 30um and the back line width is 60um.

[0078] The work function relationship of each structural layer on the corresponding side of the n-type doped layer satisfies: work function of the first thin film region < work function of the second thin film region ≤ work function of the metal electrode.

[0079] The work function relationship of each structural layer on the corresponding side of the p-type doped layer satisfies: the work function of the first thin film region is greater than the work function of the second thin film region and is greater than or equal to the work function of the metal electrode.

[0080] Example 3:

[0081] A method for fabricating a heterojunction solar cell includes the following steps:

[0082] Step 1: Use alkaline texturing to texture both sides of the silicon wafer to form a surface with a light-trapping structure;

[0083] Step 2: Intrinsic amorphous silicon is formed on the front and back sides of the silicon wafer by PECVD. An n-type doped layer is formed on the front intrinsic amorphous silicon by PECVD, and a p-type doped layer is formed on the back intrinsic amorphous silicon by PECVD.

[0084] Step 3: Transparent conductive films are formed on the surfaces of the n-type doped layer and the p-type doped layer respectively using a PVD coating process. The thickness of the resulting transparent conductive films is 80 nm, and the carrier concentration is 10e19 cm⁻¹. -3 Its transmittance is 92% in the wavelength range of 400-800nm; its sheet resistance is 100 ohms.

[0085] The transparent conductive film covering the metal area was annealed using patterned photothermal heating; the substrate temperature was 150℃, and the O2 / Ar flow ratio was 5%. An infrared laser was used as the light source, with a square spot size of 30µm on the front and 60µm on the back, and a power per unit area of ​​50J / cm². 2 The carrier concentration of the treated transparent conductive film is 20e19cm⁻¹. -3 Its transmittance is 80% in the wavelength range of 400-800nm, and its sheet resistance is 50 ohms.

[0086] Step 4: Low-silver metal electrodes are formed on the metal-covered areas of the transparent conductive film on the front and back sides using screen printing; the front grid line width is 30um and the back line width is 60um.

[0087] The work function relationship of each structural layer on the corresponding side of the n-type doped layer satisfies: work function of the first thin film region < work function of the second thin film region ≤ work function of the metal electrode.

[0088] The work function relationship of each structural layer on the corresponding side of the p-type doped layer satisfies: the work function of the first thin film region is greater than the work function of the second thin film region and is greater than or equal to the work function of the metal electrode.

[0089] Comparative Example 1:

[0090] A method for fabricating a heterojunction solar cell includes the following steps:

[0091] Step 1: Use alkaline texturing to texture both sides of the silicon wafer to form a surface with a light-trapping structure;

[0092] Step 2: Intrinsic amorphous silicon is formed on the front and back sides of the silicon wafer by PECVD. An n-type doped layer is formed on the front intrinsic amorphous silicon by PECVD, and a p-type doped layer is formed on the back intrinsic amorphous silicon by PECVD.

[0093] Step 3: Transparent conductive films are formed on the surfaces of the n-type doped layer and the p-type doped layer using a PVD coating process. The thickness of the resulting transparent conductive films is 80 nm, and the carrier concentration is 15e19 cm⁻¹. -3 Its transmittance in the wavelength range of 400-800nm ​​is 89%; its sheet resistance is 60 ohms.

[0094] Step 4: Use screen printing to form pure silver metal electrodes on the transparent conductive film surfaces of the front and back sides; the front grid line width is 30um and the back line width is 60um.

[0095] Comparative Example 2:

[0096] A method for fabricating a heterojunction solar cell includes the following steps:

[0097] Step 1: Use alkaline texturing to texture both sides of the silicon wafer to form a surface with a light-trapping structure;

[0098] Step 2: Intrinsic amorphous silicon is formed on the front and back sides of the silicon wafer by PECVD. A p-type doped layer is formed on the front intrinsic amorphous silicon by PECVD, and an n-type doped layer is formed on the back intrinsic amorphous silicon by PECVD.

[0099] Step 3: Transparent conductive films are formed on the surfaces of the n-type doped layer and the p-type doped layer using a PVD coating process. The thickness of the resulting transparent conductive films is 80 nm, and the carrier concentration is 15e19 cm⁻¹. -3 Its transmittance in the wavelength range of 400-800nm ​​is 89%; its sheet resistance is 60 ohms.

[0100] Step 4: Use screen printing to form pure silver metal electrodes on the transparent conductive film surfaces of the front and back sides; the front grid line width is 30um and the back line width is 60um.

[0101] Comparative Example 3:

[0102] A method for fabricating a heterojunction solar cell includes the following steps:

[0103] Step 1: Use alkaline texturing to texture both sides of the silicon wafer to form a surface with a light-trapping structure;

[0104] Step 2: Intrinsic amorphous silicon is formed on the front and back sides of the silicon wafer by PECVD. An n-type doped layer is formed on the front intrinsic amorphous silicon by PECVD, and a p-type doped layer is formed on the back intrinsic amorphous silicon by PECVD.

[0105] Step 3: Transparent conductive films are formed on the surfaces of the n-type doped layer and the p-type doped layer using a PVD coating process. The thickness of the resulting transparent conductive films is 80 nm, and the carrier concentration is 15e19 cm⁻¹. -3 Its transmittance in the wavelength range of 400-800nm ​​is 89%; its sheet resistance is 60 ohms.

[0106] Step 4: Low-silver metal electrodes are formed on the transparent conductive film surfaces of the front and back sides using screen printing; the front grid line width is 30um and the back line width is 60um.

[0107] Comparative Example 4:

[0108] A method for fabricating a heterojunction solar cell includes the following steps:

[0109] Step 1: Use alkaline texturing to texture both sides of the silicon wafer to form a surface with a light-trapping structure;

[0110] Step 2: Intrinsic amorphous silicon is formed on the front and back sides of the silicon wafer by PECVD. A p-type doped layer is formed on the front intrinsic amorphous silicon by PECVD, and an n-type doped layer is formed on the back intrinsic amorphous silicon by PECVD.

[0111] Step 3: Transparent conductive films are formed on the surfaces of the n-type doped layer and the p-type doped layer using a PVD coating process. The thickness of the resulting transparent conductive films is 80 nm, and the carrier concentration is 15e19 cm⁻¹. -3 Its transmittance in the wavelength range of 400-800nm ​​is 89%; its sheet resistance is 60 ohms.

[0112] Step 4: Low-silver metal electrodes are formed on the transparent conductive film surfaces of the front and back sides using screen printing; the front grid line width is 30um and the back line width is 60um.

[0113] The performance of the batteries obtained in the examples and comparative examples will be tested below. The results of measuring various parameters of the solar cells using an IV tester are shown in Table 1.

[0114] Table 1. Battery test results for the examples and comparative examples.

[0115]

[0116] As can be seen from Table 1, the batteries obtained in Examples 1-3 showed improvements in Jsc and FF compared to Comparative Examples 1-4. The improvement in Jsc was caused by the increase in transmittance of the non-metallic covered area, while the improvement in FF was caused by the decrease in resistance of the metallic covered area, which in turn led to a decrease in contact resistance and a reduction in the carrier penetration barrier due to the adjustment of the work function.

[0117] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the invention should be included within the scope of protection of the invention.

Claims

1. A high-efficiency heterojunction solar cell, characterized in that, The substrate includes a silicon substrate. The front side of the silicon substrate has a front intrinsic amorphous silicon layer, a front doped layer, a front transparent conductive thin film layer, and a front metal electrode sequentially disposed therefrom. The back side has a back intrinsic amorphous silicon layer, a back doped layer, a back transparent conductive thin film layer, and a back metal electrode sequentially disposed therefrom. Both the front and back transparent conductive thin film layers include a first thin film region not covered by metal and a second thin film region covered by metal. The carrier concentration in the first thin film region is lower than that in the second thin film region, and the transmittance of the first thin film region is higher than that of the second thin film region. The work function of the first thin film region is different from that of the second thin film region. Of the front and back doped layers, one is an n-type doped layer and the other is a p-type doped layer. The work function of the first thin film region covering the surface of the n-type doped layer is lower than that of the second thin film region, and the work function of the second thin film region is less than or equal to the work function of the metal electrode. The work function of the first thin film region covering the surface of the p-type doped layer is greater than that of the second thin film region, and the work function of the second thin film region is greater than or equal to the work function of the metal electrode.

2. The high-efficiency heterojunction solar cell according to claim 1, characterized in that, The carrier concentration in the first thin film region is 5-15e19cm. -3 The carrier concentration in the second thin film region is 10⁻³⁰e¹⁹ cm⁻¹. -3 .

3. The high-efficiency heterojunction solar cell according to claim 1, characterized in that, The transparent conductive film in the first thin film region has a transmittance of 85-95% in the wavelength range of 400-800nm, while the transparent conductive film in the second thin film region has a transmittance of 75-85% in the wavelength range of 400-800nm.

4. The high-efficiency heterojunction solar cell according to claim 1, characterized in that, The sheet resistance of the first thin film region is greater than that of the second thin film region, and the following conditions are met: the sheet resistance of the first thin film region is 50-150 ohms, and the sheet resistance of the second thin film region is 10-100 ohms.

5. A high-efficiency heterojunction solar cell according to claim 1, characterized in that, Of the front doped layer and the back doped layer, one layer is a single n-type doped layer or a combination of multiple n-type doped layers formed by n-type doped amorphous silicon, microcrystalline silicon, nanocrystalline silicon, silicon oxide or silicon carbide, and the other layer is a single p-type doped layer or a combination of multiple p-type doped layers formed by p-type doped amorphous silicon, microcrystalline silicon, nanocrystalline silicon, silicon oxide or silicon carbide.

6. A method for preparing a high-efficiency heterojunction solar cell, characterized in that, Includes the following steps: Step 1: Double-sided texturing of the silicon wafer forms a surface with a light-trapping structure; Step 2: Intrinsic amorphous silicon is formed on the front and back sides of the silicon wafer, and an n-type doped layer and a p-type doped layer are formed on the intrinsic amorphous silicon on the front and back sides, respectively. Step 3: Form transparent conductive films on the surfaces of the n-type doped layer and the p-type doped layer respectively. Anneal the transparent conductive films in the metal-covered areas by patterned photoheating, so that the metal-covered areas form the second film region and the areas not covered by metal form the first film region. When the doped layer is an n-type doped layer, the work function of the first film region is less than the work function of the second film region, and the work function of the second film region is less than or equal to the work function of the metal electrode formed thereon. When the doped layer is a p-type doped layer, the work function of the first film region is greater than the work function of the second film region, and the work function of the second film region is greater than or equal to the work function of the metal electrode formed thereon. Step 4: Form metal electrodes on the metal-covered areas of the transparent conductive film on both the front and back sides.

7. The method for preparing a high-efficiency heterojunction solar cell according to claim 6, characterized in that, In step three, a transparent conductive film is formed on the surface of the n-type doped layer and the p-type doped layer using a PVD coating process, wherein the substrate temperature is 100-200℃ and the O2 / Ar flow ratio is 1-10%.

8. The method for preparing a high-efficiency heterojunction solar cell according to claim 6, characterized in that, In step three, the graphic light heating method uses one of the following light sources: infrared laser, ultraviolet laser, white light source, or microwave.

9. The method for preparing a high-efficiency heterojunction solar cell according to claim 6, characterized in that, In step three, the patterned photothermal heating method uses a square, circular, or elliptical light spot with a spot size of 30-100 μm and a power per unit area of ​​2-100 J / cm². 2 .

10. A photovoltaic module, characterized in that, Includes the solar cell as described in any one of claims 1-5.

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