Power supply circuit and power supply method thereof

Abstract

The present disclosure provides a power supply circuit and a power supply method. The power supply circuit includes at least one first charge pump circuit, at least one second charge pump circuit, a first control circuit, a signal latch, and a voltage detector. The first charge pump circuit is configured to receive a first clock to generate a first pump voltage. The second charge pump circuit is configured to receive the first clock to generate the first pump voltage. The first control circuit is configured to provide the first clock to the first charge pump circuit and the second charge pump circuit according to a power-on detection signal. The signal latch is coupled to the second charge pump circuit. The voltage detector is configured to receive an operating voltage and generate the power-on detection signal by detecting the operating voltage.

Description

Technical Field

[0001] This disclosure relates to a power supply circuit and a power supply method; more specifically, this disclosure relates to a power supply circuit and a power supply method for reducing the power-up current. Background Technology

[0002] Charge pump circuits are often used to boost lower voltages to produce higher voltages. Multiple charge pump circuits are used to generate multiple different voltages when an electronic device requires them. Charge pump circuits are enabled when the electronic device is powered on. However, due to the large number of charge pump circuits, excessive peak current can damage electronic components within the device. Summary of the Invention

[0003] This disclosure relates to a power supply circuit and a power supply method for reducing the current carried.

[0004] In this disclosure, the power supply circuit includes at least one first charge pump circuit, at least one second charge pump circuit, a first control circuit, a latch, and a voltage detector. The first charge pump circuit is configured to receive a first clock to generate a first pump voltage. The second charge pump circuit is configured to receive the first clock to generate the first pump voltage. The first control circuit is configured to provide the first clock to both the first and second charge pump circuits based on a power-on detection signal. The latch is coupled to the second charge pump circuit. The voltage detector is configured to receive an operating voltage and generate the power-on detection signal by detecting the operating voltage.

[0005] In this disclosure, the power supply method is applicable to a power supply circuit including at least one first charge pump circuit and at least one second charge pump circuit. The power supply method includes: enabling the first charge pump circuit according to an operating voltage, wherein the first charge pump circuit is configured to receive a first clock to generate a first pump voltage; and enabling the second charge pump circuit according to a power-on detection signal and an external command, wherein the second charge pump circuit is configured to receive the first clock to generate the first pump voltage.

[0006] Based on the above, according to the power supply circuit and power supply method of this disclosure, the second charge pump circuit remains disabled until the power-on ready signal received by the second charge pump circuit is enabled according to the power-on detection signal and an external command. Therefore, while the power supply circuit or power supply method is implemented in the electronic device, the peak currents induced by the first charge pump circuit and the second charge pump circuit are generated at different points in time, thereby preventing damage to electronic components due to excessive peak current.

[0007] To make the above content easier to understand, several embodiments accompanied by the accompanying drawings will be described in detail below. Attached Figure Description

[0008] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and form a part of this specification. The drawings illustrate exemplary embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0009] Figure 1 This is a schematic block diagram of a power supply circuit according to an embodiment of the present disclosure;

[0010] Figure 2 This is a schematic timing diagram of a power supply circuit according to an embodiment of the present disclosure;

[0011] Figure 3 This is a schematic block diagram of a signal latch according to an embodiment of the present disclosure;

[0012] Figure 4 This is a schematic block diagram of a power supply circuit according to an embodiment of the present disclosure;

[0013] Figure 5 This is a schematic flowchart of a power supply method according to an embodiment of the present disclosure.

[0014] [Explanation of Symbols]

[0015] 100, 400: Power supply circuit

[0016] 200: Time Series Chart

[0017] 310, 320, 330: NAND gates

[0018] 340: NOT gate

[0019] 500: Methods of Electricity Provision

[0020] C1: First control circuit

[0021] C2: Second control circuit

[0022] CLOCK1: First Clock

[0023] CLOCK2: The Second Clock

[0024] EN: Enable terminal

[0025] EXT: External command

[0026] P1: First charge pump circuit

[0027] P2: Second charge pump circuit

[0028] P3: Third charge pump circuit

[0029] P4: Fourth charge pump circuit

[0030] PwrUp: Power-on detection signal

[0031] PwrUpRd: Power-on ready signal

[0032] S510, S520: Steps

[0033] SL: Signal latch

[0034] t0, t1, t2: Time points

[0035] VD: Voltage detector

[0036] VDD: Operating voltage

[0037] VP1: First pump voltage

[0038] VP2: Second pump voltage

[0039] Vt: Preset threshold voltage Detailed Implementation

[0040] Examples of the exemplary embodiments described herein will now be shown in detail in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or similar components.

[0041] Throughout this disclosure and the appended claims, certain terms are used to refer to specific components. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same components. This document is not intended to distinguish between components that function identically but have different names. In the following description and claims, words such as "comprise" and "include" are open-ended terms and should be interpreted as "including but not limited to...".

[0042] Figure 1 This is a schematic block diagram of a power supply circuit according to an embodiment of the present disclosure. (Refer to...) Figure 1The power supply circuit 100 may include at least one first charge pump circuit P1, at least one second charge pump circuit P2, a first control circuit C1, a signal latch SL, and a voltage detector VD. The first charge pump circuit P1 is configured to receive a first clock CLOCK1 to generate a first pump voltage VP1. The second charge pump circuit P2 is configured to receive the first clock CLOCK1 to generate the first pump voltage VP1. The first control circuit C1 is configured to provide the first clock CLOCK1 to the first charge pump circuit P1 and the second charge pump circuit P2 according to a power-on detection signal PwrUp. The signal latch SL is coupled to the second charge pump circuit P2. The voltage detector VD is configured to receive an operating voltage VDD and generate a power-on detection signal PwrUp by detecting the operating voltage VDD.

[0043] Note that the first charge pump circuit P1 is enabled based on the operating voltage VDD, and the signal latch SL enables the second charge pump circuit P2 based on the power-on detection signal PwrUp and the external command EXT. That is, only the first charge pump circuit P1 is enabled based on the operating voltage VDD, while the second charge pump circuit P2 is enabled not only based on the operating voltage VDD. Therefore, while the power supply circuit 100 is implemented in the electronic device, the peak current induced by the first charge pump circuit P1 can be effectively limited, thereby preventing damage to the electronic components of the electronic device due to excessive peak current.

[0044] In one embodiment, the electronic device may be, for example, a memory device or other device that includes electronic components, and this disclosure is not limited thereto.

[0045] In one embodiment, the first charge pump circuit P1 and the second charge pump circuit P2 may receive a first clock CLOCK1 to generate the same voltage (i.e., the first pump voltage VP1). In another embodiment, the first charge pump circuit P1 and the second charge pump circuit P2 may receive the first clock CLOCK1 to generate different voltages. That is, one or more first charge pump circuits P1 used to generate the first pump voltage VP1 are enabled at a first time point, and one or more second charge pump circuits P2 used to generate the first pump voltage VP1 or a different voltage are enabled at a second time point different from the first time point. In this way, the total current supplied by the power supply circuit 100 can be divided into two parts, which occur at the first time point and the second time point, respectively. This prevents damage to the electronic components of the electronic device due to excessive peak current.

[0046] In one embodiment, the first charge pump circuit P1 may include an enable terminal EN connected to the operating voltage VDD. When the operating voltage VDD is greater than a preset threshold voltage Vt, the voltage detector VD can enable the energization detection signal PwrUp by comparing the operating voltage VDD with the preset threshold voltage Vt. Accordingly, when the energization detection signal PwrUp is enabled, the first control circuit C1 can provide a first clock CLOCK1. For example, the first charge pump circuit P1 can receive the first clock CLOCK1 to generate a first pump voltage VP1 based on the operating voltage VDD being enabled.

[0047] In one embodiment, the second charge pump circuit P2 may also include an enable terminal EN. The enable terminal EN is coupled to a signal latch SL. The signal latch SL can provide a power-on ready signal PwrUpRd to the enable terminal EN of the second charge pump circuit P2 to enable the second charge pump circuit P2.

[0048] Specifically, the signal latch SL can provide a power-on ready signal PwrUpRd to the enable terminal EN of the second charge pump circuit P2 based on the power-on detection signal PwrUp and the external command EXT. It is worth noting that the signal latch SL can receive the external command EXT after the power-on detection signal PwrUp is enabled. In one embodiment, the external command EXT can be a non-operation (NOP) command, and the NOP command can be generated by the electronic device after it is powered on. The signal latch SL can latch the enable states of the external command EXT and the power-on detection signal PwrUp to generate the power-on ready signal PwrUpRd. When both the power-on detection signal PwrUp and the external command EXT are enabled, the signal latch SL can provide the power-on ready signal PwrUpRd to enable the second charge pump circuit P2, thereby receiving the first clock CLOCK1 to generate the first pump voltage VP1.

[0049] Of course, in some embodiments, the external command EXT may be a specific command other than the NOP command, and this disclosure is not limited thereto.

[0050] In one embodiment, the power supply circuit 100 may further include a command decoder. The command decoder can be used to decode external commands EXT. In one embodiment, the command decoder may be integrated with the signal latch SL, or may be located outside the signal latch SL, but this disclosure is not limited thereto.

[0051] In this way, the second charge pump circuit P2 can remain deactivated until the power-on ready signal PwrUpRd received by the second charge pump circuit P2 is enabled. Therefore, while the power supply circuit 100 is implemented in the electronic device, the peak currents induced by the first charge pump circuit P1 and the second charge pump circuit P2 are generated at different points in time, thereby preventing damage to the electronic components of the electronic device due to excessive peak current.

[0052] Figure 2 This is a schematic timing diagram of a power supply circuit according to an embodiment of the present disclosure. (Refer to...) Figure 1 and Figure 2 The timing diagram 200 may include the operating voltage VDD, the power-on detection signal PwrUp, the external command EXT, and the power-on ready signal PwrUpRd. To make the relationship between the operating voltage VDD, the power-on detection signal PwrUp, and the external command EXT easier to understand, the sequence of the operating voltage VDD, the power-on detection signal PwrUp, and the external command EXT is explained in detail below.

[0053] At time point t0, the operating voltage VDD can begin to gradually increase from the preset turn-off voltage to the preset turn-on voltage. At time point t1, the operating voltage VDD can exceed the preset threshold voltage Vt. In response to the operating voltage VDD exceeding the preset threshold voltage Vt, the voltage detector VD can enable the power-on detection signal PwrUp. That is, the power-on detection signal PwrUp can switch from a low logic level to a high logic level.

[0054] In response to the power-on detection signal PwrUp, the first control circuit C1 can provide a first clock CLOCK1 to the first charge pump circuit P1, and enable the first charge pump circuit P1 through the operating voltage VDD to receive the first clock CLOCK1 to generate a first pump voltage VP1. In particular, between time point t1 and time point t2, the first charge pump circuit P1 is enabled, and the second charge pump circuit P2 remains disabled.

[0055] At time t2, the signal latch SL can receive an enabled external command EXT with a high logic level. In response to the external command EXT and the power-on detection signal PwrUp, the signal latch SL can provide a power-on ready signal PwrUpRd to the second charge pump circuit P2, and enable the second charge pump circuit P2 through the power-on ready signal PwrUpRd to receive the first clock CLOCK1 to generate the first pump voltage VP1. That is, the second charge pump circuit P2 is enabled after the first charge pump circuit P1 is enabled.

[0056] In this way, the second charge pump circuit P2 can remain de-energized until time point t2. Therefore, while the power supply circuit 100 is implemented in the electronic device, the peak currents induced by the first charge pump circuit P1 and the second charge pump circuit P2 are generated at different time points, thereby preventing damage to the electronic components of the electronic device due to excessive peak current.

[0057] Note that the high and low logic levels of signals, voltages, and commands are exemplary embodiments, and this disclosure is not limited thereto.

[0058] Figure 3 This is a schematic block diagram of a signal latch according to an embodiment of the present disclosure. (Refer to...) Figure 1 and Figure 3 The signal latch SL can be an SR latch, and includes NAND gate 310, NAND gate 320, NAND gate 330 and NOT gate 340.

[0059] When the power-on detection signal PwrUp is at a high logic level and the external command EXT is at a high logic level, NAND gate 310 can output a first output signal with a low logic level. NAND gates 320 and 330 are cross-coupled to form a latch for holding the first output signal of NAND gate 310. NAND gates 320 and 330 can maintain the output signal of NAND gate 310 at a low logic level and output a second output signal with a low logic level. When the second output signal is at a low logic level, NOT gate 340 can enable the power-on ready signal PwrUpRd.

[0060] In this embodiment, the signal latch SL is a NAND-type SR latch. In another embodiment, the signal latch SL may be an NOR-type SR latch, and this disclosure is not limited thereto.

[0061] Figure 4 This is a schematic block diagram of a power supply circuit according to an embodiment of the present disclosure. (Refer to...) Figure 1 and Figure 4 ,and Figure 1 Compared to the power supply circuit 100 shown, the power supply circuit 400 may further include at least one third charge pump circuit P3, at least one fourth charge pump circuit P4, and a second control circuit C2. Details of the first charge pump circuit P1, the second charge pump circuit P2, the first control circuit C1, the signal latch SL, and the voltage detector VD can be found in [reference needed]. Figure 1 The explanation is provided, but the details will not be elaborated upon in this article.

[0062] The third charge pump circuit P3 is configured to receive the second clock CLOCK2 and generate the second pump voltage VP2. The fourth charge pump circuit P4 is configured to receive the second clock CLOCK2 and generate the second pump voltage VP2. The second control circuit C2 is configured to provide the second clock CLOCK2 to the third charge pump circuit P3 and the fourth charge pump circuit P4 according to the power-on detection signal PwrUp. The signal latch SL is coupled to the fourth charge pump circuit P4.

[0063] Note that the third charge pump circuit P3 is enabled based on the operating voltage VDD, and the signal latch SL enables the fourth charge pump circuit P4 based on the power-on detection signal PwrUp and the external command EXT. Detailed embodiments of the third charge pump circuit P3, the fourth charge pump circuit P4, and the second control circuit C2 can be found in the first charge pump circuit P1, the second charge pump circuit P2, and the first control circuit C1.

[0064] In one embodiment, the first clock CLOCK1 may be the same as the second clock CLOCK2. That is, one or more charge pump circuits (e.g., the first charge pump circuit P1 and the third charge pump circuit P3) used to pump the same voltage are first enabled, and one or more charge pump circuits (e.g., the second charge pump circuit P2 and the fourth charge pump circuit P4) used to receive the same clock are later enabled. In another embodiment, the first clock CLOCK1 may be different from the second clock CLOCK2. That is, one or more charge pump circuits (e.g., the first charge pump circuit P1 and the third charge pump circuit P3) used to receive two different clocks are first enabled, and one or more charge pump circuits (e.g., the second charge pump circuit P2 and the fourth charge pump circuit P4) used to receive two different clocks are later enabled. In other words, this disclosure does not limit the first clock CLOCK1 and the second clock CLOCK2 to be the same or different.

[0065] In this way, the second charge pump circuit P2 and the fourth charge pump circuit P4 can remain deactivated until the power-on ready signal PwrUpRd received by the second charge pump circuit P2 and the fourth charge pump circuit P4 is enabled. Therefore, while the power supply circuit 400 is implemented in the electronic device, the peak current induced by the charge pump circuit is generated at different points in time, thereby preventing damage to the electronic components of the electronic device due to excessive peak current.

[0066] Figure 5 This is a schematic flowchart of a power supply method according to an embodiment of the present disclosure. (Refer to...) Figure 1 and Figure 5The power supply method 500 is applicable to a power supply circuit 100 or a power supply circuit 400 that includes at least one first charge pump circuit P1 and at least one second charge pump circuit P2. Further details regarding the implementation of the power supply method 500 can be found in [reference needed]. Figures 1 to 4 The description is provided to provide sufficient teaching, suggestions and implementation examples, but details will not be repeated here.

[0067] In step S510, the first charge pump circuit P1 is enabled according to the operating voltage VDD. The first charge pump circuit P1 is configured to receive a first clock CLOCK1 to generate a first pump voltage VP1.

[0068] In step S520, the second charge pump circuit P2 is enabled according to the power-on detection signal PwrUp and the external command EXT. The second charge pump circuit P2 is configured to receive the first clock CLOCK1 to generate the first pump voltage VP1.

[0069] The details of steps S510 and S520 have been described in the above embodiments and will not be repeated here.

[0070] Therefore, while the power supply method 500 is implemented in the electronic device, the peak currents induced by the first charge pump circuit P1 and the second charge pump circuit P2 are generated at different times, thereby preventing damage to the electronic components of the electronic device due to excessive peak current.

[0071] In summary, according to the power supply circuit and power supply method of this disclosure, the second charge pump circuit remains deactivated until a power-on ready signal received by the second charge pump circuit is enabled. Therefore, when the power supply circuit or power supply method is implemented in the electronic device, the peak currents induced by the first charge pump circuit and the second charge pump circuit are generated at different times, thereby preventing damage to electronic components due to excessive peak current.

[0072] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of this disclosure. In view of the foregoing, this disclosure is intended to cover modifications and variations falling within the scope of the foregoing claims and their equivalents.

Claims

1. A power supply circuit, comprising: At least one first charge pump circuit receives a first clock to generate a first pump voltage; At least one second charge pump circuit receives the first clock to generate the first pump voltage; At least one third charge pump circuit receives a second clock and generates a second pump voltage; At least one fourth charge pump circuit receives the second clock and generates the second pump voltage; A first control circuit provides the first clock to the at least one first charge pump circuit and the at least one second charge pump circuit according to the power-on detection signal; The second control circuit provides the second clock to the at least one third charge pump circuit and the at least one fourth charge pump circuit according to the power-on detection signal; A signal latch is coupled to the at least one second charge pump circuit and the at least one fourth charge pump circuit; as well as A voltage detector receives the operating voltage and generates the energization detection signal by detecting the operating voltage. The at least one first charge pump circuit is enabled according to the operating voltage, and the signal latch enables the at least one second charge pump circuit according to the power-on detection signal and an external command. The at least one third charge pump circuit is enabled according to the operating voltage, and the signal latch enables the at least one fourth charge pump circuit according to the power-on detection signal and the external command.

2. The power supply circuit according to claim 1, wherein the signal latch receives the external command after the power-on detection signal is enabled.

3. The power supply circuit according to claim 1, wherein when the operating voltage is greater than a preset threshold voltage, the voltage detector enables the power-on detection signal.

4. The power supply circuit of claim 1, wherein the at least one first charge pump circuit includes an enable terminal connected to the operating voltage.

5. The power supply circuit according to claim 1, wherein The at least one second charge pump circuit includes an enable terminal, and The signal latch provides a power-on ready signal to the enable terminal of the at least one second charge pump circuit based on the power-on detection signal and the external command.

6. The power supply circuit according to claim 1, wherein The external command is a Non-Operation (NOP) command.

7. A power supply method, applicable to a power supply circuit including at least one first charge pump circuit, at least one second charge pump circuit, at least one third charge pump circuit, and at least one fourth charge pump circuit, wherein the power supply method includes: The at least one first charge pump circuit is enabled according to an operating voltage, wherein the at least one first charge pump circuit is configured to receive a first clock to generate a first pump voltage. The at least one third charge pump circuit is enabled according to the operating voltage, wherein the at least one third charge pump circuit is configured to receive a second clock to generate a second pump voltage. The at least one second charge pump circuit is enabled according to a power-on detection signal and an external command, wherein the at least one second charge pump circuit is configured to receive the first clock to generate the first pump voltage. as well as The at least one fourth charge pump circuit is enabled according to the power-on detection signal and the external command, wherein the at least one fourth charge pump circuit is configured to receive the second clock to generate the second pump voltage.

8. The power supply method according to claim 7, further comprising: The external command is received after the power-on detection signal is enabled.

9. The power supply method according to claim 7, further comprising: When the operating voltage is greater than the preset threshold voltage, the power-on detection signal is enabled.

10. The power supply method according to claim 7, wherein The at least one first charge pump circuit includes an enable terminal connected to the operating voltage.

11. The power supply method of claim 7, wherein the at least one second charge pump circuit includes an enable terminal, and the power supply method further includes: A power-on ready signal is provided to the enable terminal of the at least one second charge pump circuit according to the power-on detection signal and the external command.

12. The power supply method according to claim 7, wherein The external command is a Non-Operation (NOP) command.

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