Voltage generator and voltage generation method thereof

Abstract

This disclosure provides a voltage generator and a voltage generation method thereof. The voltage generator includes at least one first charge pump circuit, at least one second charge pump circuit, an oscillator, a transmission circuit, and a voltage detector. The first charge pump circuit is configured to receive a clock signal to generate a first pump voltage. The second charge pump circuit is configured to receive a clock signal to generate the first pump voltage. The oscillator is configured to provide a clock signal. The transmission circuit is configured to receive the clock signal, a power-on detection signal, and an external command. The voltage detector is configured to receive an operating voltage and generate a power-on detection signal by detecting the operating voltage. The transmission circuit determines whether to transmit the clock signal to the second charge pump circuit to enable or disable the second charge pump circuit.

Description

Technical Field

[0001] This disclosure relates to a voltage generator and a voltage generation method; more specifically, this disclosure relates to a voltage generator and a voltage generation method for reducing the power-up current. Background Technology

[0002] Charge pump circuits are often used to boost lower voltages to produce higher voltages. Multiple charge pump circuits are used to generate multiple different voltages when an electronic device requires them. Charge pump circuits are enabled when power is applied to the electronic device. However, excessive peak current caused by a large number of charge pump circuits can damage electronic components within the device. Summary of the Invention

[0003] This disclosure relates to a voltage generator and a voltage generation method for reducing applied current.

[0004] In this disclosure, the voltage generator includes at least one first charge pump circuit, at least one second charge pump circuit, an oscillator, a passing circuit, and a voltage detector. The first charge pump circuit is configured to receive a clock signal to generate a first pump voltage. The second charge pump circuit is configured to receive a clock signal to generate the first pump voltage. The oscillator is configured to provide the clock signal. The passing circuit is configured to receive the clock signal, a power-on detection signal, and an external command. The voltage detector is configured to receive an operating voltage and generate a power-on detection signal by detecting the operating voltage. The passing circuit determines whether to transmit the clock signal to the second charge pump circuit to activate or deactivate the second charge pump circuit.

[0005] In this disclosure, the voltage generation method is applicable to a voltage generator including at least one first charge pump circuit and at least one second charge pump circuit. The voltage generation method includes: receiving a clock signal via the at least one first charge pump circuit to generate a first pump voltage; and determining whether to transmit the clock signal to the at least one second charge pump circuit to enable or disable the at least one second charge pump circuit for receiving the clock signal to generate the first pump voltage.

[0006] Based on the above, according to the voltage generator and voltage generation method of this disclosure, the second charge pump circuit remains disabled until the transmission circuit transmits the clock signal to the second charge pump circuit. Therefore, when the voltage generator or voltage generation method is implemented in the electronic device, the peak currents induced by the first charge pump circuit and the second charge pump circuit are generated at different times, thereby preventing damage to electronic components due to excessive peak current.

[0007] To make the above content easier to understand, several embodiments with accompanying drawings will be described in detail below. Attached Figure Description

[0008] This document includes accompanying drawings to provide a further understanding of the present disclosure, and the drawings are incorporated in and form a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0009] Figure 1 This is a schematic block diagram of a voltage generator according to an embodiment of the present disclosure;

[0010] Figure 2 This is a schematic timing diagram of a voltage generator according to an embodiment of the present disclosure;

[0011] Figure 3 This is a schematic block diagram of a transmission circuit according to an embodiment of the present disclosure;

[0012] Figure 4 This is a schematic block diagram of a voltage generator according to an embodiment of the present disclosure;

[0013] Figure 5 This is a schematic flowchart of a voltage generation method according to an embodiment of the present disclosure.

[0014] [Explanation of Symbols]

[0015] 100, 400: Voltage generator

[0016] 200: Timing Diagram

[0017] 310: NOT gate

[0018] 320, 330: NAND gates

[0019] 340: Switch

[0020] CLK: Clock signal

[0021] CTR: Control Signal

[0022] EN: Enable terminal

[0023] EXT: External command

[0024] OSC: Oscillator

[0025] OT: Output terminal

[0026] P1: First charge pump circuit

[0027] P2: Second charge pump circuit

[0028] P3: Third charge pump circuit

[0029] P4: Fourth charge pump circuit

[0030] PS: Transmission circuit

[0031] PwrUp: Power-on detection signal

[0032] RST: Reset pin

[0033] S510, S520: Steps

[0034] ST: Set terminal

[0035] t0, t1, t2, t3: Time points

[0036] VD: Voltage detector

[0037] VDD: Operating voltage

[0038] VP1: First pump voltage

[0039] VP2: Second pump voltage

[0040] Vt: Threshold voltage Detailed Implementation

[0041] Examples of the exemplary embodiments described herein will now be shown in detail in the accompanying drawings. Wherever possible, the same reference numerals will be used in the drawings and description to refer to the same or similar components.

[0042] Throughout this disclosure and the appended claims, certain terms are used to refer to specific components. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same components. This document is not intended to distinguish between components that function identically but have different names. In the following description and claims, words such as "comprise" and "include" are open-ended terms and should be interpreted as "including but not limited to...".

[0043] Figure 1 This is a schematic block diagram of a voltage generator according to an embodiment of the present disclosure. (Refer to...) Figure 1The voltage generator 100 may include at least one first charge pump circuit P1, at least one second charge pump circuit P2, an oscillator OSC, a transfer circuit PS, and a voltage detector VD. The first charge pump circuit P1 is configured to receive a clock signal CLK to generate a first pump voltage VP1. The second charge pump circuit P2 is configured to receive a clock signal CLK to generate the first pump voltage VP1. The oscillator OSC is configured to provide the clock signal CLK. The transfer circuit PS is configured to receive the clock signal CLK, a power-on detection signal PwrUp, and an external command EXT. The voltage detector VD is configured to receive an operating voltage VDD and generate the power-on detection signal PwrUp by detecting the operating voltage VDD.

[0044] Note that the oscillator OSC can provide a clock signal CLK to enable the first charge pump circuit, and the transmission circuit PS determines whether to transmit the clock signal CLK to the second charge pump circuit P2 to enable or disable the second charge pump circuit P2. That is, only the first charge pump circuit P1 is enabled and activated according to the operating voltage VDD to generate the first pump voltage VP1, and the second charge pump circuit P2 is activated according to the transmission circuit PS to generate the first pump voltage VP1. Therefore, when the voltage generator 100 is implemented in the electronic device, the peak currents induced by the first charge pump circuit P1 and the second charge pump circuit P2 are generated at different times, thereby preventing damage to the electronic components of the electronic device due to excessive peak current.

[0045] It should be noted that the second charge pump circuit P2 can be enabled after the first charge pump circuit P1 is enabled. In this embodiment, when the power-on detection signal PwrUp is enabled and an external command has been received, the transmission circuit PS can transmit the clock signal CLK to the second charge pump circuit P2.

[0046] In one embodiment, the first charge pump circuit P1 and the second charge pump circuit P2 may each include an enable terminal EN connected to the operating voltage VDD. Specifically, the enable terminal EN of the first charge pump circuit P1 and the enable terminal EN of the second charge pump circuit P2 can receive the operating voltage VDD.

[0047] During the power-on sequence, when the operating voltage VDD is greater than a preset threshold voltage Vt, the voltage detector VD enables the power-on detection signal PwrUp by comparing the operating voltage VDD with the preset threshold voltage Vt. Correspondingly, when the power-on detection signal PwrUp is enabled, the oscillator OSC provides a clock signal CLK to the first charge pump circuit P1. Therefore, the first charge pump circuit P1 can boost the first voltage V1 according to the clock signal CLK to generate a first pump voltage VP1.

[0048] In one embodiment, the transmission circuit PS can generate a control signal CTR based on the power-on detection signal PwrUp and the external command EXT, and transmit a clock signal to the second charge pump circuit P2 based on the control signal CTR. The transmission circuit PS can latch the enable state of the external command EXT and the enable state of the power-on detection signal PwrUp to generate the control signal CTR.

[0049] If both the power-on detection signal PwrUp and the external command EXT are enabled, the control signal CTR can be enabled, and the transmission circuit PS can transmit the clock signal CLK to the second charge pump circuit P2 to enable the second charge pump circuit P2. If at least one of the power-on detection signal PwrUp and the external command EXT is disabled, the transmission circuit PS can prevent the transmission of the clock signal CLK to the second charge pump circuit P2 to disable the second charge pump circuit P2. In other words, the transmission circuit PS can determine whether to transmit the clock signal CLK to the second charge pump circuit P2 based on the power-on detection signal PwrUp and the external command EXT.

[0050] It is worth mentioning that the power-on detection signal PwrUp is enabled before the enable time of the external command EXT. In other words, the transmission circuit PS can receive the external command EXT, which is enabled after the power-on detection signal PwrUp is enabled.

[0051] In one embodiment, the external command EXT can be a non-operation (NOP) command, and the NOP command can be generated by the electronic device after it is powered on. Of course, in some embodiments, the external command EXT can be other specific commands besides NOP commands, and this disclosure is not limited thereto.

[0052] In one embodiment, the electronic device may be, for example, a memory device or other device that includes electronic components, and this disclosure is not limited thereto.

[0053] In one embodiment, the oscillator OSC may be coupled between the voltage detector VD and the first charge pump circuit P1. The transfer circuit PS may be coupled between the oscillator OSC and the second charge pump circuit P2.

[0054] In one embodiment, the first charge pump circuit P1 and the second charge pump circuit P2 may receive a first clock Clock1 to generate the same voltage (i.e., the first pump voltage VP1). In another embodiment, the first charge pump circuit P1 and the second charge pump circuit P2 may receive the first clock Clock1 to generate different voltages. That is, in some embodiments, one or more first charge pump circuits P1 for generating the first pump voltage VP1 may be activated at a first time point, and one or more second charge pump circuits P2 for generating the first pump voltage VP1 or a different voltage may be activated at a second time point different from the first time point. Therefore, the total applied current of the voltage generator 100 can be divided into several parts, which appear at different time points. This can prevent damage to the electronic components of the electronic device due to excessive peak current.

[0055] In this way, the second charge pump circuit P2 can remain disabled until the transmission circuit PS transmits the clock signal CLK to the second charge pump circuit P2. Therefore, while the voltage generator 100 is implemented in the electronic device, the peak currents induced by the first charge pump circuit P1 and the second charge pump circuit P2 are generated at different times, thereby preventing damage to the electronic components of the electronic device due to excessive peak current.

[0056] Figure 2 This is a schematic timing diagram of a voltage generator according to an embodiment of the present disclosure. (Refer to...) Figure 1 and Figure 2 The timing diagram 200 may include the operating voltage VDD, the power-on detection signal PwrUp, the clock signal CLK, and the external command EXT. To make the relationship between the operating voltage VDD, the power-on detection signal PwrUp, the clock signal CLK, and the external command EXT easier to understand, the sequence of the operating voltage VDD, the power-on detection signal PwrUp, the clock signal CLK, and the external command EXT is described in detail below.

[0057] At time point t0, during the power-on sequence, the operating voltage VDD can gradually increase from a preset turn-off voltage to a preset turn-on voltage. At time point t1, the operating voltage VDD can exceed a preset threshold voltage Vt. In response to the operating voltage VDD exceeding the preset threshold voltage Vt, the voltage detector VD can enable the power-on detection signal PwrUp. That is, the power-on detection signal PwrUp can be switched from a low logic level to a high logic level.

[0058] At time t2, in response to the power-on detection signal PwrUp, the oscillator OSC provides the clock signal CLK to the first charge pump circuit P1. The first charge pump circuit P1 is enabled by the operating voltage VDD and activated by the clock signal CLK to receive the clock signal CLK to generate the first pump voltage VP1. Specifically, between time t0 and time t3, the first charge pump circuit P1 is activated, while the second charge pump circuit P2 remains disabled.

[0059] At time t3, the transfer circuit PS can receive an enabled external command EXT with a high logic level. In response to the external command EXT and the power-on detection signal PwrUp being enabled, the transfer circuit PS can provide an enabled control signal CTR. Furthermore, based on the control signal CTR, the transfer circuit PS can transmit the clock signal CLK to the second charge pump circuit P2, and the second charge pump circuit P2 is enabled to receive the clock signal CLK, thereby generating the first pump voltage VP1. That is, the second charge pump circuit P2 is enabled after the first charge pump circuit P1 is enabled.

[0060] In this way, the second charge pump circuit P2 can remain disabled until time point t3. Therefore, while the voltage generator 100 is implemented in the electronic device, the peak currents induced by the first charge pump circuit P1 and the second charge pump circuit P2 are generated at different time points, thereby preventing damage to the electronic components of the electronic device due to excessive peak current.

[0061] Note that the high and low logic levels of signals, voltages, and commands are exemplary embodiments, and this disclosure is not limited thereto.

[0062] Figure 3 This is a schematic block diagram of a transmission circuit according to an embodiment of the present disclosure. (Refer to...) Figure 1 and Figure 3 The transmission circuit PS can be a set-reset (SR) latch, including a NOT gate 310, a NAND gate 320, a NAND gate 330, and a switch 340. The SR latch may have a set terminal ST for receiving an inverted signal of an external command EXT, a reset terminal RST for receiving a power-on detection signal PwrUp, and an output terminal OT for generating a control signal CTR. The switch 340 may have a first terminal for receiving a clock signal CLK, a second terminal coupled to the second charge pump circuit P2, and a control terminal for receiving the control signal CTR.

[0063] When an external command is at a high logic level, the NOT gate can output a first output signal with a low logic level. NAND gates 320 and 330 are cross-coupled to form a latch for maintaining the first output signal of NOT gate 310.

[0064] NAND gates 320 and 330 can maintain the low logic level of the output signal of NAND gate 310. When the power-on detection signal PwrUp is also at a high logic level, NAND gates 320 and 330 can output a control signal CTR with a high logic level. Switch 340 can be enabled by the control signal CTR and transmit the clock signal CLK to the second charge pump circuit P2.

[0065] In this embodiment, the signal latch SL is a NAND-type SR latch. In another embodiment, the signal latch SL may be an NOR-type SR latch, and this disclosure is not limited thereto.

[0066] Figure 4 This is a schematic block diagram of a voltage generator according to an embodiment of the present disclosure. (Refer to...) Figure 1 and Figure 4 ,and Figure 1 Compared to the voltage generator 100 shown, the voltage generator 400 may further include at least one third charge pump circuit P3 and at least one fourth charge pump circuit P4. Details of the first charge pump circuit P1, the second charge pump circuit P2, the oscillator OSC, the transfer circuit PS, and the voltage detector VD can be found in [reference needed]. Figure 1 The explanation is provided, but the details will not be elaborated upon in this article.

[0067] In one embodiment, the oscillator OSC may be coupled between the voltage detector VD and the third charge pump circuit P3. The transfer circuit PS may be coupled between the oscillator OSC and the fourth charge pump circuit P4.

[0068] In one embodiment, the third charge pump circuit P3 is configured to receive a clock signal CLK to generate a second pump voltage VP2. The fourth charge pump circuit P4 is configured to receive a clock signal CLK to generate the second pump voltage VP2. A transmission circuit PS determines whether to transmit the clock signal CLK to the fourth charge pump circuit P4 to enable or disable it. That is, only the first charge pump circuit P1 is enabled and activated according to the operating voltage VDD to generate the second pump voltage VP2, and the second charge pump circuit P2 is activated according to the transmission circuit PS to generate the second pump voltage VP2. Detailed embodiments of the third charge pump circuit P3 and the fourth charge pump circuit P4 can be found with reference to the first charge pump circuit P1 and the second charge pump circuit P2.

[0069] In one embodiment, the first pump voltage VP1 may be the same as the second pump voltage VP2. That is, one or more charge pump circuits in all charge pump circuits that generate the same voltage (e.g., the first charge pump circuit P1 and the third charge pump circuit P3) are first activated, and one or more charge pump circuits in all charge pump circuits that receive the same voltage (e.g., the second charge pump circuit P2 and the fourth charge pump circuit P4) are subsequently activated. In another embodiment, the first pump voltage VP1 may be different from the second pump voltage VP2. That is, one or more charge pump circuits in all charge pump circuits that generate two different voltages (e.g., the first charge pump circuit P1 and the third charge pump circuit P3) are first activated, and one or more charge pump circuits in all charge pump circuits that generate said two different voltages (e.g., the second charge pump circuit P2 and the fourth charge pump circuit P4) are subsequently activated. In other words, this disclosure does not limit the first pump voltage VP1 to be the same as or different from the second pump voltage VP2.

[0070] In this way, the second charge pump circuit P2 and the fourth charge pump circuit P4 can remain disabled until the transmission circuit PS transmits the clock signal CLK to the second charge pump circuit P2 and the fourth charge pump circuit P4. Therefore, while the voltage generator 400 is implemented in the electronic device, the peak current induced by the charge pump circuits is generated at different points in time, thereby preventing damage to the electronic components of the electronic device due to excessive peak current.

[0071] Figure 5 This is a schematic flowchart of a voltage generation method according to an embodiment of the present disclosure. (Refer to...) Figure 1 and Figure 5 The voltage generation method 500 is applicable to a voltage generator 100 or voltage generator 400 that includes at least one first charge pump circuit P1 and at least one second charge pump circuit P2. Furthermore, implementation details of the voltage generation method 500 can be found in [reference needed]. Figures 1 to 4 The description is provided to provide sufficient teaching, advice and practical examples, but the details are not repeated here.

[0072] In step S510, the first charge pump circuit P1 is enabled and configured to receive the clock signal CLK to generate the first pump voltage VP1.

[0073] In step S520, the transmission circuit determines whether to transmit the clock signal CLK to the second charge pump circuit P2 to enable or disable the second charge pump circuit P2 used to generate the first pump voltage VP1.

[0074] The details of steps S510 and S520 have been described in the above-mentioned embodiments and will not be repeated here.

[0075] Therefore, when the voltage generation method 500 is implemented in the electronic device, the peak currents induced by the first charge pump circuit P1 and the second charge pump circuit P2 are generated at different time points, thereby preventing damage to the electronic components of the electronic device due to excessive peak current.

[0076] In summary, according to the voltage generator and voltage generation method of this disclosure, the second charge pump circuit remains disabled until the transmission circuit transmits the clock signal to the second charge pump circuit. Therefore, while the voltage generator or voltage generation method is implemented in the electronic device, the peak currents induced by the first charge pump circuit and the second charge pump circuit are generated at different times, thereby preventing damage to electronic components due to excessive peak current.

[0077] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of this disclosure. In view of the foregoing, this disclosure is intended to cover modifications and variations falling within the scope of the foregoing claims and their equivalents.

Claims

1. A voltage generator, characterized in that, include: At least one first charge pump circuit receives a clock signal to generate a first pump voltage; At least one second charge pump circuit receives the clock signal to generate the first pump voltage; An oscillator provides the clock signal; The transmission circuit receives the clock signal, the power-on detection signal, and external commands. as well as A voltage detector receives an operating voltage and generates the energization detection signal by detecting the operating voltage. The transmission circuit determines whether to transmit the clock signal to the at least one second charge pump circuit to enable or disable the at least one second charge pump circuit. The transmission circuit includes: The set-reset latch has a set terminal for receiving an inverted signal of the external command, a reset terminal for receiving the power-on detection signal, and an output terminal for generating a control signal. as well as The switch has a first terminal for receiving the clock signal, a second terminal coupled to the at least one second charge pump circuit, and a control terminal for receiving the control signal.

2. The voltage generator according to claim 1, characterized in that, The transmission circuit generates the control signal based on the power-on detection signal and the external command, and transmits the clock signal to the at least one second charge pump circuit based on the control signal.

3. The voltage generator according to claim 1, characterized in that, If the power-on detection signal and the external command are enabled, the transmission circuit transmits the clock signal to the at least one second charge pump circuit to enable the at least one second charge pump circuit.

4. The voltage generator according to claim 1, characterized in that, If at least one of the power-on detection signal and the external command is deactivated, the transmission circuit prevents the clock signal from being transmitted to the at least one second charge pump circuit, thereby disabling the at least one second charge pump circuit.

5. The voltage generator according to claim 1, characterized in that, The at least one first charge pump circuit boosts the first voltage according to the clock signal to generate the first pump voltage.

6. The voltage generator according to claim 1, characterized in that, The power-on detection signal is enabled before the enable time of the external command.

7. The voltage generator according to claim 1, characterized in that, When the operating voltage is greater than the threshold voltage, the voltage detector enables the power-on detection signal.

8. The voltage generator according to claim 1, characterized in that, The enable terminal of the at least one first charge pump circuit and the enable terminal of the at least one second charge pump circuit receive the operating voltage.

9. The voltage generator according to claim 1, characterized in that, The external command is a non-operational command.

10. The voltage generator according to claim 1, characterized in that, Also includes: At least one third charge pump circuit receives the clock signal to generate a second pump voltage; as well as At least one fourth charge pump circuit receives the clock signal to generate the second pump voltage. The at least one third charge pump circuit boosts the second voltage according to the clock signal to generate the second pump voltage. The transmission circuit determines whether to transmit the clock signal to the at least one fourth charge pump circuit to enable or disable the at least one fourth charge pump circuit.

11. A voltage generation method, applicable to a voltage generator comprising at least one first charge pump circuit and at least one second charge pump circuit, characterized in that, The voltage generation method includes: A clock signal is received via the at least one first charge pump circuit to generate a first pump voltage; and The operating voltage is received via a voltage detector; A power-on detection signal is generated by detecting the operating voltage via the voltage detector. The clock signal is provided via an oscillator; The clock signal, the power-on detection signal, and external commands are received via a transmission circuit; and The transmission circuit determines whether to transmit the clock signal to the at least one second charge pump circuit to enable or disable the at least one second charge pump circuit used to generate the first pump voltage. The transmission circuit includes: A set-reset latch has a set terminal for receiving an inverted signal of the external command, a reset terminal for receiving the power-on detection signal, and an output terminal for generating a control signal; and The switch has a first terminal for receiving the clock signal, a second terminal coupled to the at least one second charge pump circuit, and a control terminal for receiving the control signal.

12. The voltage generation method according to claim 11, characterized in that, Also includes: The control signal is generated via the transmission circuit based on the power-on detection signal and the external command. as well as The clock signal is transmitted to the at least one second charge pump circuit via the transmission circuit according to the control signal.

13. The voltage generation method according to claim 11, characterized in that, Also includes: If the power-on detection signal and the external command are enabled, the clock signal is transmitted to the at least one second charge pump circuit via the transmission circuit to enable the at least one second charge pump circuit.

14. The voltage generation method according to claim 11, characterized in that, Also includes: If at least one of the power-on detection signal and the external command is deactivated, the clock signal is prevented from being transmitted to the at least one second charge pump circuit via the transmission circuit, thereby disabling the at least one second charge pump circuit.

15. The voltage generation method according to claim 11, characterized in that, Also includes: The first voltage is boosted via the at least one first charge pump circuit to generate the first pump voltage according to the clock signal.

16. The voltage generation method according to claim 11, characterized in that, The power-on detection signal is enabled before the enable time of the external command.

17. The voltage generation method according to claim 11, characterized in that, The enable terminal of the at least one first charge pump circuit and the enable terminal of the at least one second charge pump circuit receive the operating voltage.

18. The voltage generation method according to claim 11, characterized in that, The external command is a non-operational command.

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