LLC resonant load inductive heating power supply variable dead time control method

Abstract

This invention discloses a method for controlling the dead time of an induction heating power supply for an LLC resonant load. The invention includes the following steps: First, the full-bridge inverter circuit in the LLC resonant load induction heating system is connected to a low-turn-off loss capacitor and a non-ZVS state protection circuit. The non-ZVS state protection circuit performs signal conversion based on the voltages at each CE terminal of the full-bridge inverter circuit to obtain the ZVS state judgment result and sends it to the digital signal processor in the system control circuit. Next, a phase detection circuit is used to convert the output current of the full-bridge inverter circuit and the output voltage of the digital signal processor before inputting them into the digital signal processor. Finally, the digital signal processor controls the induction heating system based on a reference DC voltage and all ZVS state judgment results. This invention effectively reduces the turn-off loss of the inverter circuit in the induction heating system and ensures the stable operation of the induction heating system.

Description

Technical Field

[0001] This invention relates to a voltage-type induction heating power supply control method belonging to the field of resonant topology power supplies, specifically to a dead-time control method for an induction heating power supply with an LLC resonant load. Background Technology

[0002] Voltage-type induction heating power supplies are increasingly used in actual production. They generally include LC series resonant topologies and the newer LLC series-parallel resonant topologies. Compared to the traditional LC topology, the new resonant topology eliminates the need for a load matching transformer, improving power supply efficiency. Furthermore, due to its unique structure, the LLC resonant topology is particularly suitable for parallel connection to extend capacity. LLC induction heating power supplies can be categorized into DC power regulation and inverter power regulation based on the adjustment position. DC power regulation can be further divided into chopper power regulation and semi-controlled rectification power regulation, while inverter power regulation is generally divided into frequency sweep modulation (PFM), pulse density modulation (PDM), and phase shift modulation (PSM).

[0003] In the frequency sweep power regulation mode, the circuit operating frequency must be higher than the load's equivalent resonant frequency to operate in an inductive state, thus satisfying the ZVS turn-on condition of the power transistor. Although the power transistor operates in the ZVS conduction state, it is actually in a hard-turn-off state. When the power transistor is turned off, the turn-off current is large, resulting in significant turn-off losses. Especially at low impedance, to ensure the inverter's output current, the operating frequency must increase, and the turn-off current also increases accordingly, further amplifying the turn-off losses. This leads to more severe heating of the power transistor, seriously affecting the normal operation of the circuit. Summary of the Invention

[0004] The purpose of this invention is to provide a method for controlling the dead time of an induction heating power supply with an LLC resonant load. This aims to solve the problems of excessive turn-off losses and the inability of a fixed dead time to maintain ZVS (Zero-Voltage Switching) over a wide output range in traditional frequency sweep power regulation. This invention proposes a method of connecting a capacitor in parallel across the power transistor to reduce turn-off losses, and simultaneously proposes a method for controlling the dead time, enabling the system to maintain ZVS of the power transistor over a wide output range.

[0005] The technical solution adopted in this invention is:

[0006] 1) Connect the full-bridge inverter circuit in the LLC resonant load induction heating system to the low-turn-off loss capacitor and the non-ZVS state protection circuit. The non-ZVS state protection circuit performs signal conversion based on the voltage of each CE terminal of the upper arm of the full-bridge inverter circuit, obtains the ZVS state judgment result, and sends it to the digital signal processor in the system control circuit.

[0007] 2) After the output current of the full-bridge inverter circuit and the output voltage of the digital signal processor are converted by the phase detection circuit, the reference DC voltage Phase2 is obtained and input into the digital signal processor.

[0008] 3) The digital signal processor calculates the maximum dead time based on the reference DC voltage Phase2, and then controls the LLC resonant load induction heating system based on the maximum dead time and the ZVS state judgment result of the full-bridge inverter circuit, thereby realizing the dead time control of the induction heating power supply.

[0009] In step 1), each power transistor (IGBT) of the full-bridge inverter circuit is connected in parallel with its corresponding low-turn-off-loss capacitor.

[0010] In step 1), the non-ZVS state protection circuit includes two CE terminal voltage detection circuits and one ZVS state judgment circuit. The two power transistors (IGBTs) of the upper bridge arm in the full-bridge inverter circuit are respectively connected to the corresponding CE terminal voltage detection circuits. The two input terminals of each CE terminal voltage detection circuit are respectively connected to the C terminal and E terminal of the corresponding power transistor (IGBT) in the upper bridge arm. Each CE terminal voltage detection circuit is used to convert the acquired CE voltage of the power transistor (IGBT) into a 5V square wave voltage signal. The two CE terminal voltage detection circuits of the full-bridge inverter circuit are connected to the ZVS state judgment circuit. The ZVS state judgment circuit judges the ZVS status in the bridge arm based on the two input 5V square wave voltage signals, obtains the ZVS status judgment result, and sends it to the digital signal processor.

[0011] Each CE terminal voltage detection circuit includes a comparator, an optocoupler, and a diode. The C terminal of each power transistor IGBT is connected to the non-inverting input of the comparator via two anti-series diodes and a seventh resistor. One end of the third resistor is connected to the power supply VCC, and the other end of the third resistor is grounded via a third capacitor. The anode of the diode closest to the seventh resistor is connected to the other end of the third resistor. The E terminal of each power transistor IGBT is connected to the inverting input of the comparator via a parallel eighth resistor, a fourth capacitor, and one end of a ninth resistor. The other end of the ninth resistor is connected to the power supply VCC. The output terminal of the comparator is connected to the non-inverting input of the comparator via a fourth resistor. The output terminal of the comparator is also connected to the power supply VCC via a second resistor. The output terminal of the comparator is connected to the input terminal of the optocoupler, and the output terminal of the optocoupler outputs a 5V square wave voltage signal.

[0012] The ZVS state judgment circuit includes two DQ latches and two diodes. The clock signal CLK terminal and the set signal D terminal of each DQ latch are connected to the two output terminals of the corresponding CE terminal voltage detection circuit. The Q output terminal of the DQ latch is connected to the positive terminal of the corresponding diode. The negative terminals of the two diodes are connected and then led out as the output of the ZVS state judgment circuit.

[0013] In the digital signal processor, the number of times N is high in the output of each of the two ZVS state judgment circuits is recorded. When the system starts, if the number of high-level times N is greater than or equal to a preset threshold M, the highest frequency f of the LLC resonant load induction heating system is reduced. max If the number of high-level events N during normal operation is greater than or equal to the preset threshold M, the system operating frequency will be reduced until it reaches the minimum operating frequency and then the system will be shut down.

[0014] In step 2), the phase detection circuit includes an XOR gate and an operational amplifier circuit. The output current of the full-bridge inverter circuit is converted into a voltage square wave signal, which is then used as the two inputs of the XOR gate along with the output voltage square wave signal of the digital signal processor. The output of the XOR gate is connected to the non-inverting input of the operational amplifier circuit via the 36th resistor. The non-inverting input of the operational amplifier circuit is also connected to one end of the grounded 43rd capacitor and the cathode of the 5th diode. The inverting input of the operational amplifier circuit is connected to its output. The output of the operational amplifier circuit is grounded via the 37th resistor and the 44th capacitor. The reference DC voltage Phase2 is output after the connection between the 37th resistor and the 44th capacitor.

[0015] In the digital signal processor, the angle θ by which the output current of the full-bridge inverter lags behind the output voltage of the full-bridge inverter is determined based on the reference DC voltage Phase2, and then the maximum dead time t is calculated. dmax The calculation formula is as follows:

[0016]

[0017] Where f is the system's operating frequency.

[0018] The beneficial effects of this invention are:

[0019] This invention effectively reduces the turn-off loss of the inverter circuit in the induction heating system by setting a maximum dead time and connecting each power transistor (IGBT) of the inverter circuit in parallel with its own low turn-off loss capacitor, combined with a frequency sweep control power adjustment method. At the same time, a ZVS detection circuit is used to detect the circuit's operating status, and the power supply operating frequency is changed in the non-ZVS state to ensure the stable operation of the induction heating system. Attached Figure Description

[0020] Figure 1 This is the main circuit diagram of the LLC resonant load induction heating system in this embodiment.

[0021] Figure 2 This is the control circuit diagram of the LLC resonant load induction heating system in this embodiment.

[0022] Figure 3 This is a circuit diagram of the phase detection circuit in this embodiment.

[0023] Figure 4 This is a schematic diagram of the relationship between Phase 2 and phase in this embodiment.

[0024] Figure 5 This is a circuit diagram of the CE terminal voltage detection circuit in this embodiment.

[0025] Figure 6 This is the circuit diagram for ZVS state determination in this embodiment. Detailed Implementation

[0026] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] The main circuit of the LLC resonant load induction heating system is divided into three parts: a three-phase uncontrolled rectifier, a full-bridge inverter, and an LLC resonant load. The main circuit diagram of the LLC resonant load induction heating system is shown below. Figure 1 As shown. The rectifier section uses a three-phase uncontrolled rectifier to obtain a DC voltage source V. dc Because of the uncontrolled rectification method, a higher power factor can be achieved in the grid-side system. Considering system capacity, the inverter section ultimately adopts a full-bridge structure, with the control method being the previously mentioned frequency sweep control. The full-bridge inverter outputs a square wave voltage with a variable frequency and a 50% duty cycle. The load section uses an LLC structure, consisting of a series resonant inductor L... s Parallel resonant capacitor C r Load equivalent inductance L r The inverter output square wave passes through the LLC resonant load structure to generate an approximately sinusoidal current, which the system then transmits power to the load to heat the workpiece. In this invention, each power transistor (IGBT) in the inverter circuit is connected in parallel with its own low-turn-off-loss capacitor (non-junction capacitor).

[0028] System control circuit design such as Figure 2 As shown in the figure, the control circuit of the induction heating system includes a sampling main control circuit, a drive circuit, and an external communication circuit. The main control circuit includes a sampling processing circuit, a DSP chip processing circuit, and a protection processing circuit.

[0029] The sampling processing circuit is used to sample the inverter output current i from external sensors. s and the voltage V of the parallel resonant capacitor cr The data is processed and then used as input to the DSP chip.

[0030] The DSP chip processing circuit processes the sampled results using certain control methods; in short, it controls the inverter output current i. sThe closed-loop control keeps the inverter output current constant, thus controlling the power transmitted by the system to control the workpiece heating. The DSP processing circuit also needs to perform phase limiting, voltage limiting, and dead-time adjustment. Phase limiting ensures the inverter operates in the inductive region with a margin to prevent the system from entering the capacitive region. Voltage limiting controls the voltage across the parallel resonant capacitor to prevent it from exceeding its limit, which also protects the induction furnace and the parallel capacitor. Dead-time adjustment calculates the maximum dead time of the drive signal by processing the phase difference between the output voltage and current. After current closed-loop, voltage limiting, phase limiting, and dead-time adjustment, the DSP chip outputs a square wave drive signal with a specific frequency and dead time.

[0031] The protection processing circuit is used to process various circuit protection signals, such as output overcurrent, parallel resonant capacitor overvoltage, capacitive, overtemperature, short circuit, and insufficient auxiliary power supply. When a protection signal arrives, the protection circuit automatically blocks the drive output and sends the protection signal to the DSP chip.

[0032] The drive circuit amplifies the PWM drive signal output by the DSP chip through optical fiber isolation, and then processes it through a dedicated drive chip to drive the IGBT.

[0033] The external communication circuit is the circuit for communication between the DSP chip and the human-machine interface. The DSP reads some manually preset parameters into the internal register of the DSP through communication with the human-machine interface to prepare for subsequent control. When the system is working normally, it sends the circuit operation parameters to the human-machine interface, such as output current, operating frequency, dead time, and parallel capacitor voltage, so that the staff can observe the operation status of the system in real time.

[0034] The present invention achieves dead-time control of the heating power supply by comprising the following steps:

[0035] 1) Connect the full-bridge inverter circuit in the LLC resonant load induction heating system to the low-turn-off loss capacitor and the non-ZVS state protection circuit. The non-ZVS state protection circuit performs signal conversion based on the voltage of each CE terminal of the upper arm of the full-bridge inverter circuit, obtains the ZVS state judgment result, and sends it to the digital signal processor in the system control circuit.

[0036] In the full-bridge inverter circuit, each power transistor (IGBT) is connected in parallel with its corresponding low-turn-off-loss capacitor.

[0037] In certain high-frequency situations, even with variable dead-time control, zero-VS (Zero-Voltage-Side-Time) cannot be achieved. When each IGBT in the inverter circuit is connected in parallel with its own low-turn-off-loss capacitor, and the system operating frequency is much higher than the resonant point, ZVS cannot be achieved. Furthermore, in frequency sweep power regulation, system startup is a high-frequency start-up. Due to potential deviations in load matching by the user, the set maximum startup frequency may be much higher than the system's resonant frequency. This results in a situation where, although the operating current of the circuit is small during startup, the turn-on loss is still significant due to the high frequency. Therefore, it is crucial to avoid this non-ZVS region as quickly as possible after startup.

[0038] The non-ZVS state protection circuit includes two CE terminal voltage detection circuits and one ZVS state judgment circuit. In the full-bridge inverter circuit, the two power transistors (IGBTs) of the upper bridge arm are connected to the corresponding CE terminal voltage detection circuits. The two input terminals of each CE terminal voltage detection circuit are connected to the C and E terminals of the corresponding power transistor (IGBT) in the upper bridge arm, respectively. Each CE terminal voltage detection circuit is used to convert the acquired CE voltage of the power transistor (IGBT) into a 5V square wave voltage signal. The two CE terminal voltage detection circuits of the full-bridge inverter circuit are connected to the ZVS state judgment circuit. The ZVS state judgment circuit judges the ZVS status of the bridge arm based on the two input 5V square wave voltage signals, obtains the ZVS status judgment result, and sends it to the digital signal processor.

[0039] like Figure 5 As shown, each CE terminal voltage detection circuit includes a comparator, an optocoupler, and a diode. The C terminal of each power transistor IGBT is connected to the non-inverting input of the comparator via two anti-series diodes and a seventh resistor. One end of the third resistor is connected to the power supply VCC, and the other end of the third resistor is grounded via a third capacitor. The anode of the diode closest to the seventh resistor is connected to the other end of the third resistor. The E terminal of each power transistor IGBT is connected to the inverting input of the comparator via a parallel eighth resistor, a fourth capacitor, and one end of a ninth resistor. The other end of the ninth resistor is connected to the power supply VCC. The output terminal of the comparator is connected to the non-inverting input terminal of the comparator via a fourth resistor. The output terminal of the comparator is also connected to the power supply VCC via a second resistor. The output terminal of the comparator is connected to the input terminal of the optocoupler, and the output terminal of the optocoupler outputs a 5V square wave signal.

[0040] The two input terminals (i.e., port 103 and CGND) of each CE voltage detection circuit are connected to the C and E terminals of the corresponding power transistor IGBT in the upper arm of the full-bridge inverter circuit, respectively. This acquires the CE voltage, which is then connected to a comparator through two anti-series diodes. The output of the comparator is then connected to an optocoupler for isolation conversion, and finally the high-voltage square wave signal at the CE terminal is successfully converted into a 5V square wave signal.

[0041] like Figure 6 As shown, the ZVS state judgment circuit includes two DQ latches and two diodes. The clock signal CLK terminal and the set signal D terminal of each DQ latch are connected to the two output terminals of the corresponding CE terminal voltage detection circuit. The Q output terminal of the DQ latch is connected to the positive terminal of the corresponding diode. The negative terminals of the two diodes are connected and then led out as the output of the ZVS state judgment circuit (i.e., the ZVS state judgment result).

[0042] VCE1 and VCE2 are the square wave signals of the CE terminal voltage output by the voltage detection circuit corresponding to the two transistors of the upper bridge arm, respectively. Vg233 and Vg234 are the drive signals output by the DSP (Digital Signal Processor) control board, which correspond to the upper and lower transistors respectively. Figure 6 The DQ latch is used to detect ZVS status. Simply put, the VCE square wave signal is used as the D signal. When the Vg signal arrives (the drive signal), the CE voltage remains high (VCE is high), so the Q output of the flip-flop is high, meaning port 208 is high; this is a non-ZVS state. Conversely, when the drive signal arrives, the CE voltage drops to 0 (VCE is low), so the Q output of the flip-flop is low, and port 208 is low; this is a ZVS state. Therefore, the potential at port 208 represents the ZVS status of the circuit at that moment. The signal at port 208 is connected to the DSP, and the circuit's operating status is determined based on the level sampled at port 208 during operation.

[0043] In the digital signal processor, the number of times N is high in the output of each of the two ZVS state judgment circuits is recorded. When starting up, if the number of high levels N is greater than or equal to a preset threshold M, the highest frequency f of the LLC resonant load induction heating system is reduced. max If the number of high-level events N during normal operation is greater than or equal to the preset threshold M, the system operating frequency will be reduced until it reaches the minimum operating frequency and then the system will be shut down.

[0044] Specifically:

[0045] This involves two aspects of operation. Firstly, during startup, the LLC resonant load induction heating system operates at the set maximum frequency f. max If N is less than M at this point, meaning the system is considered to be operating in ZVS state, then no additional action is needed, and the system can function normally. If N is detected to be greater than M during startup, then f needs to be quickly... max Lowering the value reduces the startup frequency. The specific adjustment step size and adjustment time can be determined according to the specific situation. When the system can achieve ZVS, then the current f value is set. max This is recorded as the new startup frequency, and the circuit enters its normal operating range.

[0046] On the other hand, if N is detected to be greater than M during normal system operation, it indicates that the circuit has entered a non-ZVS state. At this time, adjusting the system operating frequency usually means reducing the frequency. If ZVS cannot be satisfied even when the frequency is reduced to the set minimum operating frequency, it indicates that the system has a serious load mismatch and needs to be shut down, the load rematched, and the circuit checked.

[0047] 2) After the output current of the full-bridge inverter circuit and the output voltage of the digital signal processor are converted by the phase detection circuit, the reference DC voltage Phase2 is obtained and input into the digital signal processor.

[0048] like Figure 3 As shown, the phase detection circuit includes an XOR gate and an operational amplifier circuit.

[0049] The output current of the full-bridge inverter circuit is converted into a voltage square wave signal and then used as the two inputs of the XOR gate along with the output voltage square wave signal of the digital signal processor. The output of the XOR gate is connected to the non-inverting input of the operational amplifier circuit via the 36th resistor. The non-inverting input of the operational amplifier circuit is also connected to one end of the grounded 43rd capacitor and the cathode of the 5th diode. The inverting input of the operational amplifier circuit is connected to its output. The output of the operational amplifier circuit is grounded via the 37th resistor and the 44th capacitor. The reference DC voltage Phase2 is output after leading out from the 37th resistor and the 44th capacitor.

[0050] 3) The digital signal processor calculates the maximum dead time based on the reference DC voltage Phase2, and then controls the LLC resonant load induction heating system based on the maximum dead time and the ZVS state judgment results of the full-bridge inverter circuit, thereby realizing the dead time control of the induction heating power supply.

[0051] In a digital signal processor, the angle θ between the output current and the output voltage of the full-bridge inverter circuit is determined based on the reference DC voltage Phase2. Figure 4 As shown, the two satisfy a direct proportional relationship, and thus the maximum dead time t can be calculated. dmax The calculation formula is as follows:

[0052]

[0053] Where f is the system's operating frequency.

[0054] In practical variable dead-time control, a certain margin must be allowed. This invention reduces the turn-off loss of the inverter circuit by setting a maximum dead time and connecting each power transistor (IGBT) in parallel with its own low-turn-off-loss capacitor.

[0055] Finally, it should be noted that the above embodiments and descriptions are only used to illustrate the technical solutions of the present invention and not to limit it. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the disclosure of the technical solutions of the present invention, and all such modifications and substitutions should be covered within the protection scope of the claims of the present invention.

Claims

1. A dead-time control method for an LLC resonant load induction heating power supply, characterized by, Includes the following steps: 1) Connect the full-bridge inverter circuit in the LLC resonant load induction heating system to the low-turn-off loss capacitor and the non-ZVS state protection circuit. The non-ZVS state protection circuit converts the signal based on the voltage of each CE terminal of the upper arm of the full-bridge inverter circuit, obtains the ZVS state judgment result, and sends it to the digital signal processor in the system control circuit. Each power transistor IGBT of the full-bridge inverter circuit is connected in parallel with the corresponding low-turn-off loss capacitor. The non-ZVS state protection circuit includes one ZVS state judgment circuit. 2) After the output current of the full-bridge inverter circuit and the output voltage of the digital signal processor are converted by the phase detection circuit, the reference DC voltage Phase2 is obtained and input into the digital signal processor. 3) The digital signal processor calculates the maximum dead time based on the reference DC voltage Phase2, and then controls the LLC resonant load induction heating system based on the maximum dead time and the ZVS state judgment result of the full-bridge inverter circuit, so as to realize the dead time control of the induction heating power supply. In the digital signal processor, the number of times N is a high level in the output of the ZVS state judgment circuit is recorded. When the circuit starts up, if the number of high levels N is greater than or equal to a preset threshold M, then the highest frequency f of the LLC resonant load induction heating system is reduced. max If the number of high-level events N during normal operation is greater than or equal to the preset threshold M, the system operating frequency will be reduced until it reaches the minimum operating frequency and then the system will be shut down. In the digital signal processor, the angle by which the output current of the full-bridge inverter lags behind the output voltage of the full-bridge inverter is determined based on the reference DC voltage Phase2. Then, the maximum dead time is calculated. The calculation formula is as follows: wherein, is the operating frequency of the system.

2. The LLC resonant load induction heating power supply dead time control method of claim 1, wherein, In step 1), the non-ZVS state protection circuit also includes two CE terminal voltage detection circuits. The two power transistors (IGBTs) of the upper bridge arm in the full-bridge inverter circuit are respectively connected to the corresponding CE terminal voltage detection circuits. The two input terminals of each CE terminal voltage detection circuit are respectively connected to the C terminal and E terminal of the corresponding power transistor (IGBT) in the upper bridge arm. Each CE terminal voltage detection circuit is used to convert the acquired CE voltage of the power transistor (IGBT) into a 5V square wave voltage signal. The two CE terminal voltage detection circuits of the full-bridge inverter circuit are connected to the ZVS state judgment circuit. The ZVS state judgment circuit judges the ZVS state in the bridge arm based on the two input 5V square wave voltage signals, obtains the ZVS state judgment result, and sends it to the digital signal processor.

3. The LLC resonant load induction heating power supply dead time control method of claim 2, wherein, Each CE terminal voltage detection circuit includes a comparator, an optocoupler, and a diode. The C terminal of each power IGBT is connected to the non-inverting input of the comparator via two anti-series diodes and a seventh resistor. One end of the third resistor is connected to the power supply VCC, and the other end of the third resistor is grounded via a third capacitor. The anode of the diode closest to the seventh resistor is connected to the other end of the third resistor. The E terminal of each power IGBT is connected to the inverting input of the comparator via a parallel eighth resistor, a fourth capacitor, and one end of a ninth resistor. The other end of the ninth resistor is connected to the power supply VCC. The output terminal of the comparator is connected to the non-inverting input of the comparator via a fourth resistor. The output terminal of the comparator is also connected to the power supply VCC via a second resistor. The output terminal of the comparator is connected to the input terminal of the optocoupler, and the output terminal of the optocoupler outputs a 5V square wave voltage signal.

4. The dead-time control method of an LLC resonant load induction heating power supply according to claim 2, wherein, The ZVS state judgment circuit includes two DQ latches and two diodes. The clock signal CLK terminal and the set signal D terminal of each DQ latch are connected to the two output terminals of the corresponding CE terminal voltage detection circuit. The Q output terminal of the DQ latch is connected to the positive terminal of the corresponding diode. The negative terminals of the two diodes are connected and then led out as the output of the ZVS state judgment circuit.

5. The LLC resonant load induction heating power supply dead time control method of claim 1, wherein, In step 2), the phase detection circuit includes an XOR gate and an operational amplifier circuit. The output current of the full-bridge inverter circuit is converted into a current square wave signal and then used as the two inputs of the XOR gate along with the output voltage square wave signal of the digital signal processor. The output of the XOR gate is connected to the non-inverting input of the operational amplifier circuit via the 36th resistor. The non-inverting input of the operational amplifier circuit is also connected to one end of the grounded 43rd capacitor and the cathode of the 5th diode. The inverting input of the operational amplifier circuit is connected to its output. The output of the operational amplifier circuit is grounded via the 37th resistor and the 44th capacitor. The reference DC voltage Phase2 is output after leading out from between the 37th resistor and the 44th capacitor.

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