Resonant clock network, chip, and electronic device

Abstract

The resonant clock network, the chip and the electronic equipment provided in the application comprise: an adjusting circuit, an inverter, a resonant branch and a load; the output end of the adjusting circuit is connected with the control end of the inverter, the output end of the inverter is connected with the resonant branch and the load; the first end of the inverter is connected with a power supply, and the second end of the inverter is grounded; the resonant branch is grounded; the load is grounded; the adjusting circuit is used for outputting a control signal to the control end of the inverter based on the frequency value of the received initial clock signal, the voltage value of the power supply, the capacitance value of the load and the initial clock signal, and the control signal is used for controlling the length of time when the inverter is in the off state; wherein, when the working state of the inverter is the off state, the resonant branch is used for supplying power to the load. The resonant clock network in the application can realize the reuse of the energy stored in the resonant branch when the load is in the dynamic frequency modulation, voltage modulation and load capacitance adjustment, and the power consumption of the resonant clock network is reduced.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a resonant clock network, chip, and electronic device. Background Technology

[0002] Currently, with the continuous development of electronic technology, the power required by chips is constantly increasing. In order to reduce the power consumption of chips, a resonant clock network is usually set in the chip to store energy. When the circuits and other loads in the chip are in a charging state, the resonant clock network will supply power to the loads in the chip based on its stored energy.

[0003] In related technologies, since the operating frequency of a chip is not fixed and the resonant clock network can only reduce chip power consumption at a specific resonant frequency point, multiple sets of inductors are usually added to the resonant clock network when designing it. By changing the number of inductors in the resonant clock network, the resonant frequency point of the resonant clock network can be changed to adapt to the current chip operating frequency and reduce chip power consumption.

[0004] However, the number of inductors that can be added to the resonant clock network is limited by the chip space, resulting in a limited set of resonant frequencies that can be expanded by increasing the number of inductors. When the chip operates at a resonant frequency outside the set of resonant frequencies, the power consumption of the chip cannot be reduced, resulting in a waste of resources. Summary of the Invention

[0005] The resonant clock network, chip, and electronic device provided in this application are used to solve the problem in related technologies that the resonant clock network cannot reduce chip power consumption when the chip operating frequency is not fixed.

[0006] In a first aspect, this application provides a resonant clock network, including: an adjustment circuit, an inverter, a resonant branch, and a load;

[0007] The output terminal of the regulating circuit is connected to the control terminal of the inverter, and the output terminal of the inverter is connected to the resonant branch and the load; the first terminal of the inverter is connected to the power supply, and the second terminal of the inverter is grounded; the resonant branch is grounded; the load is grounded.

[0008] The adjustment circuit is used to output a control signal to the control terminal of the inverter based on the frequency value of the received initial clock signal, the voltage value of the power supply, the capacitance value of the load, and the initial clock signal. The control signal is used to control the duration for which the inverter is in the off state.

[0009] When the inverter is in the off state, the resonant branch is used to supply power to the load.

[0010] In some embodiments, the adjustment circuit includes: a signal generation circuit, a delay circuit, and a control circuit;

[0011] The output terminal of the signal generation circuit is connected to the input terminal of the delay circuit; the output terminal of the delay circuit is connected to the input terminal of the control circuit; the output terminal of the control circuit serves as the output terminal of the adjustment circuit and is connected to the control terminal of the inverter.

[0012] The signal generation circuit is used to generate a delay signal based on the frequency value of the initial clock signal, the voltage value of the power supply, and the capacitance value of the load, and to send the delay signal to the delay circuit.

[0013] The delay circuit is used to perform phase adjustment on the received initial clock signal based on the delay signal, thereby obtaining a phase-adjusted clock signal;

[0014] The control circuit is used to process the initial clock signal and the phase-adjusted clock signal to obtain the control signal.

[0015] In some embodiments, the inverter includes a first switching element and a second switching element; the output terminal of the control circuit includes a first output port and a second output port; the control signal includes a first signal and a second signal; the operating state is a first on state, or a second on state, or an off state;

[0016] One end of the first switching element is connected to the power supply, and the other end of the first switching element is connected to one end of the second switching element, the resonant branch, and the load. The other end of the second switching element is grounded. The control terminals of the first and second switching elements serve as the control terminals of the inverter and are respectively connected to the first and second output ports of the control circuit.

[0017] The control circuit is specifically configured to process the initial clock signal and the phase-adjusted clock signal, and then output a first signal to the first switching element and a second signal to the second switching element. The first signal is used to control the first switching element to be turned on or off; the second signal is used to control the second switching element to be turned on or off.

[0018] The closed state is used to characterize the state when both the first switching element and the second switching element are turned off; the first on state is used to characterize the state when the first switching element is on and the second switching element is off; the second on state is used to characterize the state when the first switching element is off and the second switching element is on.

[0019] In some embodiments, the delay circuit includes: a plurality of buffers connected in series and a data selector corresponding to each of the buffers;

[0020] The input terminal of the first buffer in the plurality of buffers connected in series is connected to the first input terminal of its corresponding data selector, and the second input terminal of the data selector is connected to the output terminal of the first buffer; the input terminal of the first buffer is used to receive the initial clock signal.

[0021] The first input terminal of the data selector corresponding to the non-first buffer in the plurality of buffers connected in series is connected to the output terminal of the data selector corresponding to the buffer preceding the non-first buffer, and the second input terminal of the data selector corresponding to the non-first buffer is connected to the output terminal of the buffer corresponding to it.

[0022] The control terminal of the data selector is connected to the output terminal of the signal generation circuit, and is used to receive the delayed signal output by the signal generation circuit. The delayed signal is used to control the data selector to select the output signal.

[0023] The output terminal of the data selector corresponding to the last buffer in the plurality of buffers connected in series in sequence serves as the output terminal of the delay circuit and is connected to the input terminal of the control circuit.

[0024] In some embodiments, the delay circuit includes: a plurality of delay units connected in series and a plurality of transmission units connected in series; the delay units correspond one-to-one with the transmission units;

[0025] The output of the delay unit is connected to the input of its corresponding transmission unit;

[0026] The control terminal of the last delay unit in the plurality of delay units connected in series is grounded; the control terminal of the non-last delay unit in the plurality of delay units connected in series is connected to the output terminal of the signal generation circuit.

[0027] The output terminal of the transmission unit corresponding to the first delay unit in the plurality of sequentially connected delay units serves as the output terminal of the delay circuit and is connected to the input terminal of the control circuit; the input terminal of the first delay unit is used to receive the initial clock signal; wherein, the delay signal is used to control the turn-on or turn-off of the delay unit; the transmission unit corresponding to the last delay unit in the plurality of sequentially connected delay units is connected to the reference voltage;

[0028] When the delay unit is in the on state, the delay unit is used to transmit the received signal to the next delay unit connected in series with it; when the delay unit is in the off state, the delay unit is used to transmit the received signal to the output terminal of the transmission unit corresponding to the first delay unit through the corresponding transmission unit.

[0029] In some embodiments, the transmission unit includes a first NAND gate circuit; the delay unit includes a second NAND gate circuit, a third NAND gate circuit, and a first NOT gate circuit.

[0030] For each non-first delay unit in a plurality of delay units connected in series, the second input terminal of the second NAND gate circuit in the delay unit is connected to the output terminal of the second NAND gate circuit in the preceding delay unit; for the first delay unit in a plurality of delay units connected in series, the second NAND gate circuit in the delay unit is used to receive the initial clock signal;

[0031] In the last delay unit among the plurality of delay units connected in series, the first input terminal of the second NAND gate and the input terminal of the first NOT gate are connected to ground.

[0032] In the plurality of delay units connected in series, except for the last delay unit, the first input terminal of the second NAND gate is connected to the input terminal of the first NOT gate and the output terminal of the signal generation circuit.

[0033] In each of the delay units, the output terminal of the first NOT gate is connected to the first input terminal of the third NAND gate; the second input terminal of the second NAND gate is connected to the second input terminal of the third NAND gate; the output terminal of the third NAND gate serves as the output terminal of the delay unit and is connected to the input terminal of its corresponding first NAND gate.

[0034] The output terminal of the first NAND gate circuit corresponding to the first delay unit in the plurality of delay units connected in series in sequence serves as the output terminal of the delay circuit and is connected to the input terminal of the control circuit.

[0035] The first NAND gate circuit corresponding to the last delay unit in the plurality of delay units connected in series is connected to the reference voltage.

[0036] In some embodiments, the control circuit includes: an AND gate circuit and an OR gate circuit;

[0037] The first input terminal of the OR gate is connected to the first input terminal of the AND gate for receiving the initial clock signal; the second input terminal of the OR gate is connected to the second input terminal of the AND gate and the output terminal of the delay circuit; the output terminal of the OR gate serves as the first output port of the control circuit and is connected to the control terminal of the first switching element; the output terminal of the AND gate serves as the second output port of the control circuit and is connected to the control terminal of the second switching element.

[0038] In some embodiments, the resonant clock network further includes a second NOT gate; the control circuit includes a fourth NAND gate and a NOR gate.

[0039] The input terminal of the second NOT gate is connected to the output terminal of the delay circuit, and the output terminal of the delay circuit is connected to the first input terminal of the fourth NAND gate and the first input terminal of the NOR gate through the second NOT gate.

[0040] The second input terminal of the fourth NAND gate is connected to the second input terminal of the NOR gate to receive the initial clock signal; the output terminal of the fourth NAND gate serves as the first output port of the control circuit and is connected to the control terminal of the first switching element; the output terminal of the NOR gate serves as the second output port of the control circuit and is connected to the control terminal of the second switching element.

[0041] In some embodiments, the duration for which the inverter is in the off state satisfies the following condition with respect to the frequency value of the initial clock signal: the higher the frequency value of the initial clock signal, the shorter the duration for which the inverter is in the off state.

[0042] In some embodiments, the duration for which the inverter is in the off state satisfies the following condition with respect to the voltage value of the power supply: the higher the voltage value of the power supply, the longer the inverter is in the off state.

[0043] In some embodiments, the duration for which the inverter is in the off state satisfies the following condition with respect to the capacitance value of the load: the larger the capacitance value of the load, the shorter the duration for which the inverter is in the off state.

[0044] In a second aspect, this application provides a chip including a resonant clock network as described in any of the first aspects.

[0045] Thirdly, this application provides an electronic device including a resonant clock network as described in any of the first aspects.

[0046] This application provides a resonant clock network, chip, and electronic device. The resonant clock network includes: an adjustment circuit, an inverter, a resonant branch, and a load. The output terminal of the adjustment circuit is connected to the control terminal of the inverter, and the output terminal of the inverter is connected to the resonant branch and the load. The first terminal of the inverter is connected to a power supply, and the second terminal of the inverter is grounded. The resonant branch is grounded. The load is grounded. The adjustment circuit outputs a control signal to the control terminal of the inverter based on the frequency value of the received initial clock signal, the voltage value of the power supply, the capacitance value of the load, and the initial clock signal. The control signal is used to control the duration of the inverter being in the off state. When the inverter is in the off state, the resonant branch supplies power to the load, thereby enabling the resonant clock network to achieve greater reuse of the energy stored in the resonant branch even when the load is dynamically frequency-adjusted, voltage-adjusted, or its capacitance is adjusted, thus reducing the power consumption of the resonant clock network. Compared to related technologies that expand the resonant frequency of a resonant clock network by increasing the number of inductors, this application expands the resonant frequency of the resonant clock network by controlling the duration of the inverter's off state. Furthermore, to expand more resonant power points, it is not necessary to add a large number of inductors; only an adjustment circuit is needed to expand the resonant frequency. The resonant clock network of this application has a high degree of integration, avoiding the problem of large space occupation caused by a large number of inductors. Attached Figure Description

[0047] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0048] Figure 1 This is a schematic diagram of the structure of a resonant clock network provided in an embodiment of this application;

[0049] Figure 2 This is a schematic diagram of the structure of the second resonant clock network provided in the embodiments of this application;

[0050] Figure 3 This is a schematic diagram of the structure of the third resonant clock network provided in the embodiments of this application;

[0051] Figure 4 A waveform diagram of a load level value provided in an embodiment of this application;

[0052] Figure 5 A schematic diagram of the circuit structure of a delay circuit provided in an embodiment of this application;

[0053] Figure 6 A schematic diagram of the circuit structure of another delay circuit provided in an embodiment of this application;

[0054] Figure 7 A schematic diagram of a delay circuit provided for an embodiment of this application;

[0055] Figure 8 This is a schematic diagram of a control circuit provided in an embodiment of this application;

[0056] Figure 9 This is a schematic diagram of the structure of the fourth resonant clock network provided in the embodiments of this application;

[0057] Figure 10 This application provides a schematic diagram of signal changes as an embodiment of the present application.

[0058] Figure 11 This is a schematic diagram of signal comparison provided in an embodiment of this application;

[0059] Figure 12 This is another signal comparison diagram provided in the embodiments of this application;

[0060] Figure 13 This is another signal comparison diagram provided for an embodiment of this application.

[0061] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0062] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0063] Currently, with the continuous development of electronic technology and the increasing integration of chips, the power required by chips is also constantly increasing. When the circuit in the chip is in a discharging state, the resonant clock network stores the acquired electric field energy as magnetic field energy. When the circuit in the chip is in a discharging state, the resonant clock network converts the stored magnetic field energy into electric field energy to charge the circuit in the chip. Furthermore, the power consumption of the resonant clock network is lowest when the frequency of the initial clock signal input to the chip matches the resonant frequency of the resonant clock network.

[0064] In related technologies, the operating frequency of a chip is not fixed during operation (i.e., the frequency value of the initial clock signal received by the chip is not fixed). However, the resonant clock network has a fixed resonant frequency determined by the inductors and capacitors it contains. Therefore, when the chip's operating frequency changes, the power consumption optimization capability of the resonant clock network weakens.

[0065] In one example, to expand the resonant frequency of the resonant clock network, multiple sets of inductors can be set in the resonant clock network. By controlling the number of inductors in the resonant clock network, the resonant frequency value of the resonant clock network can be changed to adapt to the current operating frequency of the chip.

[0066] However, in the above scheme, as the number of inductors increases, the required space also increases, which is not conducive to improving the chip's integration density. Furthermore, due to space limitations, the number of inductors that can be added is also limited, thus limiting the expandable resonant frequency. When the chip operates at a frequency outside the expanded resonant frequency range, the resonant clock network still cannot reduce chip power consumption.

[0067] In one example, the resonant frequency of a resonant clock network can be changed by adding a capacitor. However, since the capacitance value is easily affected by factors such as ambient temperature, the actual capacitance value will deviate from the expected value. This leads to an error between the resonant frequency of the resonant clock network and the expected resonant frequency, thus preventing the resonant clock network from achieving the effect of reducing chip power consumption.

[0068] The resonant clock network, chip, and electronic device provided in this application are intended to solve at least one technical problem in the related art.

[0069] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0070] Figure 1 This is a schematic diagram of a resonant clock network provided in an embodiment of this application. Figure 1As shown, the resonant clock network provided in this embodiment includes: an adjustment circuit, an inverter, a resonant branch, and a load; the output terminal of the adjustment circuit is connected to the control terminal of the inverter, and the output terminal of the inverter is connected to the resonant branch and the load; the first terminal of the inverter is connected to the power supply, and the second terminal of the inverter is grounded; the adjustment circuit is used to output a control signal to the control terminal of the inverter based on the frequency value of the received initial clock signal (represented by signal 1 in the figure), the voltage value of the power supply (represented by signal 2 in the figure), the capacitance value of the load (represented by signal 3 in the figure), and the initial clock signal, and the control signal is used to control the duration of the inverter being in the off state; wherein, when the inverter is in the off state, the resonant branch is used to supply power to the load.

[0071] For example, the resonant clock network in this embodiment includes an adjustment circuit, an inverter, a resonant branch, and a load. The output of the adjustment circuit is connected to the control terminal of the inverter. The adjustment circuit processes the received initial clock signal based on the frequency value of the received initial clock signal, the voltage value of the power supply, and the capacitance value of the load to obtain a control signal, which is then sent to the control terminal of the inverter connected to the output of the adjustment circuit.

[0072] Furthermore, the inverter in the resonant clock network is connected to the resonant branch and the load. The first terminal of the inverter is also connected to the power supply, which can charge the load or the inverter itself when it is turned on. When the inverter's control terminal receives a control signal from the adjustment circuit, it adjusts the duration of the inverter's off state based on the received signal. When the inverter is off, the resonant branch supplies power to the load using its stored energy, thereby reducing power consumption.

[0073] Furthermore, in this embodiment, the control signal is generated by adjusting the initial clock signal based on the frequency value of the initial clock signal, the voltage value of the power supply, and the capacitance value of the load. That is, when the operating voltage (i.e., the voltage of the power supply), the operating frequency (i.e., the frequency value of the initial clock signal), or the capacitance value of the load changes, the adjustment circuit will process the initial clock signal differently based on the frequency value of the initial clock signal, the voltage value of the power supply, and the capacitance value of the load obtained in real time, thereby generating different control signals. This results in different inverter turn-off times under different control signals, i.e., different charging times for the load through the resonant branch.

[0074] In one example, when the load is in different operating states, the inverter's off-time needs to be less than or equal to half of the resonant period.

[0075] In one example, since the longer the inverter's turn-off time is, the longer it takes for the load to charge to the voltage value of the power supply, the load charging time is also needed when determining the inverter's turn-off time to avoid inaccurate operation caused by a long load charging time.

[0076] In one example, a detection circuit can be set in the resonant clock network to obtain the frequency value of the initial clock signal, the voltage value of the power supply, and the capacitance value of the load; no specific restrictions are imposed here.

[0077] In one example, a mapping relationship can be pre-stored in the regulating circuit. The regulating circuit can process the initial clock signal based on the received initial clock signal frequency value, power supply voltage value, load capacitance value, and the mapping relationship to determine the output control signal. The mapping relationship is used to indicate the correspondence between the control signal and the initial clock signal frequency value, power supply voltage value, and load capacitance value.

[0078] In this embodiment, the adjustment circuit can obtain a control signal based on the received initial clock signal frequency, power supply voltage, load capacitance, and the initial clock signal, thereby controlling the duration of the inverter being in the off state. When one or more of the load's operating frequency, operating voltage, and load capacitance change, the adjustment circuit can adjust the control signal to regulate the duration of power supply from the resonant branch to the load. This allows the resonant clock network to achieve greater reuse of the energy stored in the resonant branch (i.e., as much energy as possible can be used to power the load) under dynamic frequency adjustment, voltage adjustment, and load capacitance adjustment, thereby reducing the power consumption of the resonant clock network.

[0079] Figure 2 This is a schematic diagram of the structure of a second type of resonant clock network provided in an embodiment of this application. Figure 2 As shown, in Figure 1 Based on the structure of the resonant clock network shown, the adjustment circuit in this embodiment includes: a signal generation circuit, a delay circuit, and a control circuit; the output terminal of the signal generation circuit is connected to the input terminal of the delay circuit; the output terminal of the delay circuit is connected to the input terminal of the control circuit; the output terminal of the control circuit serves as the output terminal of the adjustment circuit and is connected to the control terminal of the inverter; the signal generation circuit generates a delay signal based on the frequency value of the initial clock signal, the voltage value of the power supply, and the capacitance value of the load, and sends the delay signal to the delay circuit; the delay circuit adjusts the phase of the received initial clock signal based on the delay signal to obtain a phase-adjusted clock signal; the control circuit processes the initial clock signal and the phase-adjusted clock signal to obtain a control signal.

[0080] In this embodiment, the adjustment circuit includes a signal generation circuit, a delay circuit, and a control circuit. The signal generation circuit generates a delay signal based on the frequency of the received initial clock signal, the voltage of the power supply, and the capacitance of the load. This delayed signal is then sent to the control circuit connected to the output of the signal generation circuit. Upon receiving the delayed signal, the control circuit adjusts the phase of the received initial clock signal based on the signal values ​​contained in the delayed signal. The phase-adjusted clock signal is then output to the control circuit connected to the output of the delay circuit. The control circuit performs logical operations on the received initial clock signal and the phase-adjusted clock signal to obtain a control signal, which controls the turn-off time of the inverter connected to the output of the control circuit.

[0081] In one example, the frequency value of the initial clock signal, the voltage value of the power supply, and the capacitance value of the load received by the signal generation circuit are all digitally encoded signals. Furthermore, the signal generation circuit can also store the corresponding delay signal values ​​for different initial clock signal frequencies, power supply voltage values, and load capacitance values. For example, when the delay signal value is 20 ps, ​​it indicates that the initial clock signal needs to be delayed by 20 ps.

[0082] For example, a lookup table can be set up in the signal generation circuit. The frequency value of the initial clock signal received by the signal generation circuit, the voltage value of the power supply, and the capacitance value of the load can be used as indices in the lookup table to find the corresponding signal parameters. For instance, the lookup table can include multiple pages, with the load capacitance value serving as the page index. Furthermore, each page of the lookup table can be divided into multiple rows and columns, with the frequency value of the initial clock signal serving as the row index and the voltage value of the power supply serving as the column index. These three indices can uniquely determine the signal value of a delayed signal.

[0083] In this embodiment, the signal generation circuit in the adjustment circuit can determine the delay signal corresponding to the initial clock signal at the current moment based on the frequency value of the initial clock signal, the voltage value of the power supply, and the capacitance value of the load. Then, the delay circuit performs phase adjustment processing on the initial clock signal based on the delay signal. Finally, the control circuit processes the phase-adjusted clock signal and the initial clock signal to obtain a control signal for controlling the inverter's turn-off duration. That is, the inverter's turn-off duration in this embodiment is jointly determined by the frequency value of the initial clock signal, the voltage value of the power supply, and the capacitance value of the load. This allows the energy stored in the resonant branch to be reused to the greatest extent possible (i.e., as much energy as possible can be used to power the load), thereby reducing the power consumption of the resonant clock network.

[0084] Figure 3 This is a schematic diagram of the structure of a third resonant clock network provided in an embodiment of this application. Figure 2 Based on the resonant clock network structure shown, the inverter in this embodiment includes a first switching element and a second switching element; the output terminal of the control circuit includes a first output port and a second output port; the control signal includes a first signal and a second signal; the inverter's operating state is a first conducting state, or a second conducting state, or a closed state;

[0085] One end of the first switching element is connected to the power supply, and the other end of the first switching element is connected to one end of the second switching element, the resonant branch, and the load. The other end of the second switching element is grounded. The control terminals of the first and second switching elements serve as the control terminals of the inverter and are respectively connected to the first and second output ports of the control circuit.

[0086] The control circuit is specifically used to process the initial clock signal and the phase-adjusted clock signal, output a first signal to the first switching element, and output a second signal to the second switching element. The first signal is used to control the first switching element to be turned on or off; the second signal is used to control the second switching element to be turned on or off.

[0087] The closed state is used to characterize the state when both the first and second switching elements are turned off; the first on state is used to characterize the state when the first switching element is on and the second switching element is off; and the second on state is used to characterize the state when the first switching element is off and the second switching element is on.

[0088] For example, the inverter in this embodiment includes a first switching element and a second switching element. The control circuit specifically processes the phase-adjusted clock signal and the initial clock signal generated by the delay circuit to obtain a control signal, which includes a first signal and a second signal. The first signal in the control signal generated by the control circuit is output through the first output port of the control circuit to the control terminal of the first switching element connected to the first output port, thereby controlling the first switching element in the inverter to be turned on or off. The second signal in the control signal generated by the control circuit is output through the second output port of the control circuit to the control terminal of the second switching element connected to the second output port, thereby controlling the second switching element in the inverter to be turned on or off. When the first switching element and the second switching element are in the off state under the control of the first signal and the second signal respectively, the inverter is in the off state; when the first switching element is in the on state under the action of the first signal and the second switching element is in the off state under the action of the second signal, the inverter is in the first on state; when the first switching element is in the off state under the action of the first signal and the second switching element is in the on state under the action of the second signal, the inverter is in the second on state.

[0089] When the inverter is in the off state, only the resonant branch in the resonant clock network can supply power to the load connected to it. When the inverter is in the first on state, since the first switching element is on and the second switching element is off, the power supply connected to one end of the first switching element can supply power to the resonant branch connected to the other end of the first switching element and the load through the first switching element and the other end of the first switching element until the voltage on the load reaches the preset charging level. When the inverter is in the second on state, since the first switching element is off and the second switching element is on, one end of the second switching element, the resonant branch, and the load are connected. Therefore, the load can charge the resonant branch to store energy, and the load can also discharge through the second switching element to reach the preset discharge level.

[0090] For example, Figure 4 This is a waveform diagram of a load level provided in an embodiment of this application. The horizontal axis represents the change in time, and the vertical axis represents the change in the load level. The load level is the level at the connection point when the load is connected to the inverter output (e.g., ...). Figure 1(Connection point above the load). In this embodiment, the first switching element is a PMOS and the second switching element is an NMOS as an example. The resonant branch in this embodiment includes an inductor L and two bias capacitors C1 and C2. One end of the inductor L is connected to the other end of the first switching element and one end of the second switching element. One end of the inductor L is also connected to one end of the bias capacitor C1 and one end of the bias capacitor C2. The other end of the bias capacitor C1 is connected to the power supply, and the other end of the bias capacitor C2 is grounded. The change in the load level can be divided into four stages. When the level of the first signal and the second signal output by the control circuit changes according to the following state transitions, the next stage is entered.

[0091] like Figure 4 As shown in the figure, in the first stage (represented by the symbol ① in the figure), the first signal output by the control circuit is a high-level signal, and the second signal output by the control circuit is a low-level signal. At this time, both the first and second switching elements are in the off state. The resonant branch charges the load without the need for the power supply connected to the first switching element, thereby achieving power consumption optimization of the resonant clock circuit.

[0092] In the second stage, when both the first and second signals change to low levels, it signifies entering the second stage. At this time, the first switching element is turned on, and the second switching element is turned off. The power supply charges the load through the first switching element, and simultaneously, the resonant branch continues to charge the load. That is, the increase in the voltage level at the load is partly due to the energy provided by the power supply and partly due to the energy provided by the resonant branch. Specifically, the second stage can be divided into the following processes:

[0093] The first process (represented by label ② in the diagram): When the voltage level in the resonant branch (i.e., the voltage level at one end of inductor L) is higher than the voltage level of the power supply, both the power supply and the inductor L in the resonant branch simultaneously charge the load. The voltage level of the resonant branch is the voltage level at the connection point between the resonant branch and the inverter (e.g., ...). Figure 1 (Level value at the connection point above the middle resonant branch).

[0094] The second process (represented by label ③ in the diagram): When the voltage level in the resonant branch is lower than the voltage level of the power supply, and energy is still stored in the resonant branch, the power supply and the load simultaneously charge the inductor L in the resonant branch, and the voltage level at the load begins to decrease.

[0095] The third process (represented by label ④ in the diagram): As the power supply and the load simultaneously charge the inductor L in the resonant branch, the load level gradually stabilizes. At this point, the resonant branch stops oscillating, and the inductor L in the resonant branch can be considered as a resistor. The energy stored in the inductor L is released through the bias capacitor C2 connected to the inductor. The energy provided by the power supply charging the inductor L through the first switching element is also released through the bias capacitor C2 connected to the other end of the inductor L.

[0096] In the third stage (represented by label ⑤ in the figure), when the first signal output by the control circuit switches to a high-level signal and the second signal output by the control circuit switches to a low-level signal, both the first and second switching elements are in the off state, and the load can discharge through the resonant branch. In this stage, the load level begins to decrease.

[0097] In the fourth stage, both the first and second signals change to high-level signals, the second switching element in the inverter turns on, and the first switching element turns off. Since the other end of the second switching element is grounded, the load can discharge through the grounded branch formed by the second switching element's conduction. Furthermore, the load capacitance also discharges through the resonant branch. That is, part of the energy stored in the load is released to ground level through the grounded second switching element, and the other part is released to the resonant branch and stored therein. Specifically, the second stage can be divided into the following time periods:

[0098] The first period (represented by label ⑥ in the figure): When the voltage level in the resonant branch is lower than the voltage level of the load, the load discharges simultaneously through the ground branch formed by the conduction to the second switching element (i.e., the conduction between the second switching element and ground) and the resonant branch. During this period, the voltage level of the load continues to decrease.

[0099] The second time period (represented by label ⑦ in the diagram): When the voltage level in the resonant branch is higher than the voltage level of the load, the resonant branch discharges to the ground branch formed by the conduction of the load and the second switching element, and the voltage level at the load increases slightly.

[0100] The third time period (represented by label ⑧ in the diagram): When the voltage level in the resonant branch is in a stable state, the voltage level at the load remains unchanged.

[0101] Figure 5This is a schematic diagram of the circuit structure of a delay circuit provided in an embodiment of this application. The delay circuit in this embodiment includes multiple buffers connected in series and a data selector corresponding to each buffer. The input terminal of the first buffer in the series-connected buffers is connected to the first input terminal of its corresponding data selector, and the second input terminal of the data selector is connected to the output terminal of the first buffer. The input terminal of the first buffer is used to receive an initial clock signal. The first input terminal of the data selector corresponding to a buffer other than the first buffer in the series-connected buffers is connected to the output terminal of the data selector corresponding to the buffer preceding the first buffer, and the second input terminal of the data selector corresponding to the buffer preceding the first buffer is connected to the output terminal of its corresponding buffer. The control terminal of the data selector is connected to the output terminal of a signal generation circuit and is used to receive a delay signal output by the signal generation circuit. The delay signal is used to control the data selector to select the output signal. The output terminal of the data selector corresponding to the last buffer in the series-connected buffers serves as the output terminal of the delay circuit and is connected to the input terminal of the control circuit.

[0102] For example, Figure 5 The delay circuit shown includes four buffers and four data selectors. Buffer 1 corresponds to data selector 1, buffer 2 corresponds to data selector 2, buffer 3 corresponds to data selector 3, and buffer 4 corresponds to data selector 4. Buffers 1 through 4 are connected in series. The input terminal of the first buffer (buffer 1) is connected to the first input terminal of data selector 1, and the second input terminal of data selector 1 is connected to the output terminal of buffer 1. The first input terminal of each of the remaining data selectors (i.e., data selectors 2 through 4) is connected to the output terminal of the data selector corresponding to the buffer preceding it. For example, the first input terminal of data selector 2 is connected to the output terminal of data selector 1 corresponding to buffer 1. The second input terminals of the remaining data selectors are connected to the output terminals of their respective buffers to receive the output signals of their corresponding buffers. Furthermore, each data selector has a control terminal for receiving the delay signal output by the signal generation circuit. It should be noted that the delay signal in this embodiment is a data signal, including a 4-bit digital code. The control terminal of each data selector receives one bit of the digital code in the delay signal. Furthermore, the digital encoding in the delayed signal received by the data selector can be used to control whether the output signal of the data selector is the signal input to its first input terminal or the signal input to its second input terminal.

[0103] For example, when it is necessary to select the signal output from buffer 3 as the phase-adjusted clock signal, the signal generation circuit can control the signal output by the data selector 3 corresponding to buffer 3 to be the signal output by buffer 3, that is, the signal input to the second input terminal of data selector 3. Furthermore, the signal generation circuit also needs to control the signal output by data selector 4 to be the signal output by data selector 3 connected to it, that is, the signal output by data selector 4 to be the signal input to its first input terminal. Then, the delay signal generated by the signal generation circuit controls the phase adjustment length of the initial clock signal by controlling the data selector in the delay circuit, thus obtaining the final phase-adjusted clock signal.

[0104] Optionally, Figure 5 Only a circuit containing four buffers and their corresponding data selectors is shown. In practical applications, the number of buffers and their corresponding data selectors can be set according to specific requirements.

[0105] In this embodiment, the phase adjustment of the initial clock signal is achieved by setting multiple buffers and data selectors corresponding to each buffer. This allows the control circuit to control the turn-off duration of the inverter based on the phase-adjusted clock signal and the initial clock signal, thereby improving the power consumption optimization capability of the resonant clock network.

[0106] Figure 6 This is a schematic diagram of the circuit structure of another delay circuit provided in an embodiment of this application. The delay circuit in this embodiment includes: multiple delay units connected in series and multiple transmission units connected in series; each delay unit has a unique corresponding transmission unit; the output terminal of the delay unit is connected to the input terminal of its corresponding transmission unit; the control terminal of the last delay unit in the multiple series-connected delay units is grounded; the control terminal of the non-last delay unit in the multiple series-connected delay units is connected to the output terminal of the signal generation circuit; the output terminal of the transmission unit corresponding to the first delay unit in the multiple series-connected delay units serves as the output terminal of the delay circuit and is connected to the input terminal of the control circuit; the input terminal of the first delay unit is used to receive an initial clock signal; wherein, the delay signal is used to control the turn-on or turn-off of the delay unit; the transmission unit corresponding to the last delay unit in the multiple series-connected delay units is connected to a reference voltage.

[0107] For example, such as Figure 6 As shown, in Figure 6The circuit includes four delay units and corresponding transmission units. Delay units 1 through 4 are connected in series. Delay unit 1 corresponds to transmission unit 1, delay unit 2 to transmission unit 2, delay unit 3 to transmission unit 3, and delay unit 4 to transmission unit 4. The output of each delay unit is connected to the input of its corresponding transmission unit. Transmission units 4 through 1 are also connected in series. For example, each transmission unit includes two inputs and one output. The output of transmission unit 4 is connected to one input of transmission unit 3, and the other input of transmission unit 3 is connected to the output of its corresponding delay unit 3. Transmission unit 4 is also connected to a reference voltage, which controls the switching on and off of transmission unit 4. In practical applications, the reference voltage can be a high-level signal. Furthermore, in the four series-connected delay units, the control terminal of the last delay unit (delay unit 4) is grounded, and the control terminals of the remaining delay units (i.e., any one of delay units 1 through 3) are connected to the output of the signal generation circuit. Furthermore, the first delay unit (i.e., delay unit 1) is used to receive the initial clock signal. The signal generation circuit is used to control the conduction or de-conduction of the delay units connected to it. It should be noted that the states of the various delay units in this embodiment may be inconsistent. The number of delay units to be controlled can be selected after determining the phase adjustment magnitude of the initial clock signal.

[0108] In actual operation, when the delay unit is in the on state, it is used to transmit the received signal to the next delay unit connected in series with it; when the delay unit is in the off state, it is used to transmit the received signal to the output terminal of the transmission unit corresponding to the first delay unit through the corresponding transmission unit.

[0109] For example, in this embodiment, the delay signal generated by the signal generation circuit is a 3-bit encoded digital signal, and the number of bits in the delay signal is related to the number of delay units. Furthermore, the digital signal in the delay signal is input to its corresponding delay unit to control the turn-on or turn-off of the delay unit. When the delay unit is in the on state, it can output the received signal to the next delay unit connected to it. When the delay unit is in the off state, it transmits the received signal to the transmission unit connected to it, and along the path of multiple sequentially connected transmission units, it transmits the signal to the output of the transmission unit corresponding to the first delay unit, thereby obtaining a phase-adjusted clock signal.

[0110] For example, when it is necessary to control the phase adjustment of the initial clock signal to correspond to the sum of the phase adjustments of the two delay units, the signal generation circuit can control delay unit 1 and delay unit 2 to be in the on state, and delay unit 3 to be in the off state. In this case, delay unit 1 performs phase adjustment processing on the received initial clock signal and outputs it to delay unit 2. After receiving the signal output by delay unit 1, delay unit 2 continues to perform phase adjustment processing on the signal and outputs the processed signal to delay unit 3. Since delay unit 3 is in the off state, delay unit 3 directly sends the signal sent from delay unit 2 to delay unit 3 to transmission unit 3 connected to delay unit 3. Then, transmission unit 3 transmits the signal to the output terminal of transmission unit 1 through transmission units 2 and 1 connected in series, thereby obtaining the phase-adjusted initial clock signal.

[0111] If the signal generation circuit controls delay units 1 to 3 to be in the on state, then, since the control terminal of delay unit 4 is grounded, the initial clock signal is processed by delay unit 1, delay unit 2 and delay unit 3 in sequence. Then, delay unit 4 sends the signal processed by delay unit 3 to transmission unit 4. The signal is then processed by transmission unit 4, transmission unit 3, transmission unit 2 and transmission unit 1 in sequence and finally output.

[0112] In this embodiment, the signal generation circuit controls the on and off states of multiple delay units, thereby controlling the phase adjustment of the initial clock signal to control the off-time of the inverter under different initial clock frequencies, different power supply voltage values, or different load capacitance values, thereby improving the power consumption optimization capability of the resonant clock network.

[0113] Figure 7 A schematic diagram of another delay circuit provided as an embodiment of this application. For example... Figure 7 As shown, in Figure 6Based on the structure shown, the transmission unit in this embodiment includes a first NAND gate circuit; the delay unit includes a second NAND gate circuit, a third NAND gate circuit, and a first NOT gate circuit. Specifically, for each delay unit that is not the first delay unit in the series-connected sequence, the second input terminal of the second NAND gate circuit in the delay unit is connected to the output terminal of the second NAND gate circuit in the preceding delay unit; for the first delay unit in the series-connected sequence, the second input terminal of the second NAND gate circuit in the delay unit is used to receive the initial clock signal; in the last delay unit in the series-connected sequence, the first input terminal of the second NAND gate circuit and the input terminal of the first NOT gate circuit are connected and then grounded; in delay units that are not the last delay unit in the series-connected sequence, the first input terminal of the second NAND gate circuit and the input terminal of the first NOT gate circuit are connected and then grounded. The output of the signal generation circuit is connected; in each delay unit, the output of the first NOT gate is connected to the first input of the third NAND gate in its own delay unit; the second input of the second NAND gate is connected to the second input of the third NAND gate in its own delay unit; the output of the third NAND gate serves as the output of the delay unit and is connected to the input of its corresponding first NAND gate; the output of the first NAND gate in the first delay unit of the multiple delay units connected in series serves as the output of the delay circuit and is connected to the input of the control circuit; the first NAND gate in the last delay unit of the multiple delay units connected in series is connected to the reference voltage.

[0114] For example, the delay unit in this embodiment is composed of a second NAND gate circuit, a first NOT gate circuit, and a third NAND gate circuit. Figure 7 The embodiment shown uses four delay units (i.e., delay unit 1 to delay unit 4) as an example. As shown in the figure, in this embodiment, the transmission unit corresponding to each delay unit is composed of a first NAND gate circuit. The first NAND gate circuit 1 corresponds to delay unit 1, the first NAND gate circuit 2 corresponds to delay unit 2, the first NAND gate circuit 3 corresponds to delay unit 3, and the second NAND gate circuit 4 corresponds to delay unit 4. Delay units 2 to 4 are not the first delay units in a series of sequentially connected delay units. Delay unit 1 is the first delay unit in a series of sequentially connected delay units, and the second input terminal of the second NAND gate circuit 1 in delay unit 1 is used to receive the initial clock signal.

[0115] Furthermore, the second NAND gates in each delay circuit are connected in series, such as... Figure 7As shown, the output of the second NAND gate 1 is connected to the second input of the second NAND gate 2, the output of the second NAND gate 2 is connected to the second input of the second NAND gate 3, and the output of the second NAND gate 3 is connected to the second input of the second NAND gate 4. Furthermore, in the delay unit 4 (i.e., the last delay unit among multiple delay units connected in series), the first input of the second NAND gate 4 is connected to the input of the first NOT gate 4 and then grounded, serving as the control terminal of the delay unit 4.

[0116] In each of the delay units 1 to 3, the first input terminal of the second NAND gate is connected to the input terminal of the first NOT gate and the output terminal of the signal generation circuit.

[0117] In each delay unit 1-4, the output of the first NOT gate is connected to the first input of the third NAND gate, the second input of the second NAND gate is connected to the second input of the third NAND gate, and the output of the third NAND gate serves as the output of the delay circuit, connected to the corresponding first NAND gate. Furthermore, multiple first NAND gates are connected in series, and the first NAND gate 4 corresponding to delay unit 4 is connected to a reference voltage. The output of the first NAND gate 1 corresponding to delay unit 1 serves as the output of the delay circuit, used to output the delayed initial clock signal.

[0118] In actual operation, when the delayed signal input to the first input terminal of the second NAND gate is high, the signal input to the second input terminal of the second NAND gate will be transmitted through the second NAND gate to the second input terminal of the next second NAND gate connected in series with it. When the delayed signal input to the first input terminal of the second NAND gate is low, since the second input terminal of the second NAND gate is also connected to the second input terminal of the third NAND gate in the delay unit, the signal received at the second input terminal of the second NAND gate will be transmitted through the third NAND gate connected to the second NAND gate to the first NAND gate connected to the third NAND gate. Then, it is transmitted to the output terminal of the delay circuit via the remaining first NAND gates connected in series with the aforementioned first NAND gate.

[0119] Optionally, Figure 6 and Figure 7 Only a circuit containing four delay units and their corresponding transmission units is shown. In practical applications, the number of delay units and their corresponding transmission units can be set according to specific requirements.

[0120] In this embodiment, the delay circuit consists of a second NAND gate, a first NOT gate, and a third NOT gate, while the transmission unit consists of a first NAND gate. This circuit structure is simple, easy to implement, and occupies little space, which is beneficial for improving circuit integration.

[0121] Figure 8 This is a schematic diagram of a control circuit provided in an embodiment of this application. Figure 8 As shown, the control circuit in this embodiment includes: an AND gate circuit and an OR gate circuit; wherein, the first input terminal of the OR gate circuit is connected to the first input terminal of the AND gate circuit for receiving an initial clock signal; the second input terminal of the OR gate circuit is connected to the second input terminal of the AND gate circuit and the output terminal of the delay circuit; the output terminal of the OR gate circuit serves as the first output port of the control circuit and is connected to the control terminal of the first switching element; the output terminal of the AND gate circuit serves as the second output port of the control circuit and is connected to the control terminal of the second switching element.

[0122] For example, such as Figure 8 As shown, the inverter in this embodiment consists of a PMOS transistor and an NMOS transistor. The output of the OR gate in the control circuit is connected to the gate of the PMOS transistor, and the output of the AND gate in the control circuit is connected to the gate of the NMOS transistor. The sources of the PMOS transistor and the NMOS transistor are connected together and then connected to the resonant branch and the load capacitor. The drain of the NMOS transistor is grounded. The drain of the PMOS transistor is connected to the power supply. Furthermore, the resonant branch in this embodiment also includes an inductor L and an equivalent resistance R. L Wherein, the equivalent resistance R L This includes the connection resistance between the inverter and the inductor, and the parasitic resistance of the inductor. Furthermore, the capacitor C in the resonant clock network characterizes the load capacitance. The inductor L, acting as an energy storage element, charges the load capacitance when the inverter is turned off. In addition, the inductor L is connected to two bias capacitors, C1 and C2.

[0123] Furthermore, the first input terminals of the OR gate and the AND gate are connected to receive the initial clock signal. The second input terminals of the OR gate and the AND gate are then connected to the output of the delay circuit to receive the phase-adjusted clock signal output by the delay circuit. Subsequently, the PMOS and NMOS transistors in the inverter are in either on or off state based on the signal output from the OR gate (i.e., the first signal in the control signal) and the signal output from the AND gate (i.e., the second signal in the control signal), respectively.

[0124] In this embodiment, the control circuit consists of AND gates and OR gates to control the inverter. The circuit structure is simple, easy to implement, and has a high degree of integration.

[0125] Figure 9 This is a schematic diagram of the structure of the fourth resonant clock network provided in an embodiment of this application. Figure 3 Based on the illustrated device, the control circuit in this embodiment includes a fourth NAND gate and a NOR gate; furthermore, a second NOT gate is included in the resonant clock network. The input terminal of the second NOT gate is connected to the output terminal of the delay circuit, and the output terminal of the delay circuit is connected to the first input terminal of both the fourth NAND gate and the NOR gate via the second NOT gate. The second input terminal of the fourth NAND gate is connected to the second input terminal of the NOR gate for receiving the initial clock signal; the output terminal of the fourth NAND gate serves as the first output port of the control circuit and is connected to the control terminal of the first switching element; the output terminal of the NOR gate serves as the second output port of the control circuit and is connected to the control terminal of the second switching element.

[0126] For example, such as Figure 9 As shown, the resonant clock network in this embodiment also includes a second NOT gate circuit. The input terminal of the second NOT gate circuit is connected to the output terminal of the delay circuit, and the output terminal of the second NOT gate circuit is connected to the first input terminal of the fourth NAND gate circuit and the first input terminal of the NOR gate circuit in the control circuit. The second NOT gate circuit is used to invert the phase-adjusted clock signal output by the delay circuit, thereby obtaining an inverted signal, which is then input to the first input terminals of the fourth NAND gate circuit and the NOR gate circuit in the control circuit. Furthermore, the second input terminal of the fourth NAND gate circuit is connected to the second input terminal of the NOR gate circuit to receive the initial clock signal. Based on the signals received at its first and second input terminals, the fourth NAND gate circuit outputs a first signal from the control signals to the PMOS transistor in the inverter, and the NOR gate circuit outputs a second signal from the control signals to the NMOS transistor in the inverter, thereby controlling the off-time of the inverter.

[0127] In this embodiment, the control circuit consists of a fourth NAND gate circuit and a NOR gate circuit, thereby realizing the control of the inverter. The circuit structure is simple, easy to implement, and has a high degree of integration.

[0128] For example, Figure 10 A schematic diagram of signal change provided in an embodiment of this application, such as... Figure 10As shown in the figure, the horizontal axis represents the change of time, and the vertical axis represents the magnitude of the signal level. The initial clock signal in the figure is a signal with a 50% duty cycle. After phase adjustment by the delay circuit, the delay circuit outputs a phase-adjusted clock signal. Since the output of the delay circuit is connected to the second NOT gate, after inversion by the second NOT gate, the inverted signal output by the second NOT gate is sent to the fourth NOT gate and NOR gate in the control circuit connected to the second NOT gate. Furthermore, the fourth NAND gate and NOR gate in the control circuit are also used to receive the initial clock signal. Based on the received inverted signal and the initial clock signal, the fourth NAND gate outputs a first signal to the PMOS transistor in the inverter, and the NOR gate outputs a second signal to the NMOS transistor in the inverter. When the first signal is at a high level and the second signal is at a low level, both the PMOS transistor and the NMOS transistor are in the off state, that is, the inverter is in the off state. The length indicated by the double-headed arrows in the diagram can be used to characterize the duration for which the inverter is in the off state.

[0129] In one example, the duration for which the inverter is off satisfies the following condition with respect to the frequency of the initial clock signal: the higher the frequency of the initial clock signal, the shorter the duration for which the inverter is off.

[0130] For example, in this embodiment, the duration of the inverter being in the off state is related to the frequency value of the initial clock signal. When the load capacitance is fixed, the power supply voltage is fixed, and the inverter is in the off state, the rate of change of the voltage level at the load (i.e., corresponding to...) Figure 4 The slope of the waveform in the first stage and Figure 4 The slope of the waveform in the third stage can be expressed by the following formula:

[0131]

[0132] Among them, S LC The slope is used to characterize the load level; L is used to characterize the inductance in the resonant branch; C is used to characterize the capacitance of the load; f(L) is an empirical factor related to the inductance L in the resonant branch; the equivalent resistance R... L This includes the resistance between the inverter and the inductor, and the parasitic resistance of the inductor; R c The equivalent resistance of the load is used to characterize the load; V is used to characterize the voltage of the power supply; U S The voltage at the connection point of bias capacitors C1 and C2 is used to characterize the voltage. e is a mathematical constant, approximately 2.718. The constant term A... opt_LC and the constant term β opt It can be expressed by the following formula:

[0133]

[0134] Among them, the constant term A opt_LC The constant term β is used to characterize the amplitude of the waveform corresponding to the voltage values ​​across the load in the first and third stages. opt The initial phase is used to characterize the waveform corresponding to the voltage values ​​across the load in the first and third stages.

[0135] also, ω0 is used to characterize the resonant angular frequency, ω LC Used to characterize the inherent oscillation angular frequency.

[0136] In practical applications, the transmission time of a clock signal transition (i.e., a change from high to low or vice versa) is generally the same as the duration the inverter is in the off state. Furthermore, the clock signal transition time typically cannot exceed 10% of the clock period. Therefore, when the clock frequency of the initial clock signal changes (i.e., the clock period of the initial clock signal changes), the transmission time of the initial clock signal transition will also change. Thus, the higher the frequency of the initial clock signal, the shorter the corresponding clock period of the initial clock signal, and the shorter the duration the inverter is in the off state. Figure 11 As shown, Figure 11 This is a signal comparison diagram provided in an embodiment of this application. Curve 1 in the diagram represents the change in the load's voltage level when the clock frequency is 2.5 GHz. Curve 2 in the diagram represents the change in the load's voltage level when the clock frequency is 1 GHz. The duration T1 of the off state in curve 1 is less than the duration T2 of the off state in curve 2. In this example, by setting the above conditions, the power consumption of the clock distribution network can be effectively reduced.

[0137] In one example, the duration the inverter is in the off state satisfies the following condition with respect to the voltage of the power supply: the higher the voltage of the power supply, the longer the inverter is in the off state.

[0138] For example, Figure 12This is another signal comparison diagram provided in an embodiment of this application. Curve 3 shows the change in voltage at the load when the power supply voltage is 0.8V. Curve 4 shows the change in voltage at the load when the power supply voltage is 0.8V. In the resonant clock network, the lower the power supply voltage, the smaller the equivalent on-resistance of the switching element in the inverter connected to the power supply. Therefore, the rate of change of the load voltage is smaller when the inverter is in the first and second on states. To ensure that the inverter is off for no more than 10% of the clock cycle, the lower the power supply voltage, the shorter the off-state time. That is, the off-state duration T3 in curve 3 is less than the off-state duration T4 in curve 4. Thus, the power consumption of the resonant clock distribution network can be effectively reduced through the condition settings in this example.

[0139] In one example, the duration the inverter is in the off state is related to the load capacitance as follows: the larger the load capacitance, the shorter the duration the inverter is in the off state.

[0140] For example, Figure 13 This is another signal comparison diagram provided in an embodiment of this application. Curves 5 and 6 represent the changes in the voltage level at the load under different load capacitance values, respectively. The load capacitance value corresponding to curve 5 is smaller than the load capacitance value corresponding to curve 6. When the load capacitance value changes, but the inductance value in the resonant branch remains constant, the larger the capacitance value, the stronger the corresponding voltage level. Figure 4 The slope of the waveform in the first stage and Figure 4 The smaller the slope of the waveform in the third stage, the shorter the duration of the inverter's off state needs to be, thus ensuring that the time the inverter is off does not exceed 10% of the clock cycle, thereby effectively reducing the power consumption of the resonant clock distribution network. That is, the off state duration T5 of curve 5 in the figure is greater than the off state duration T6 of curve 6.

[0141] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0142] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A resonant clock network, characterized in that, include: The regulating circuit, inverter, resonant branch, and load; The output terminal of the regulating circuit is connected to the control terminal of the inverter, and the output terminal of the inverter is connected to the resonant branch and the load; the first terminal of the inverter is connected to the power supply, and the second terminal of the inverter is grounded; the resonant branch is grounded; the load is grounded. The adjustment circuit is used to output a control signal to the control terminal of the inverter based on the frequency value of the received initial clock signal, the voltage value of the power supply, the capacitance value of the load, and the initial clock signal. The control signal is used to control the duration for which the inverter is in the off state. When the inverter is in the off state, the resonant branch is used to supply power to the load. The adjustment circuit includes: a signal generation circuit, a delay circuit, and a control circuit; The signal generation circuit is used to generate a delay signal based on the frequency value of the initial clock signal, the voltage value of the power supply, and the capacitance value of the load, and to send the delay signal to the delay circuit. The delay circuit is used to perform phase adjustment on the received initial clock signal based on the delay signal, thereby obtaining a phase-adjusted clock signal; The control circuit is used to process the initial clock signal and the phase-adjusted clock signal to obtain the control signal.

2. The resonant clock network according to claim 1, characterized in that, The output terminal of the signal generation circuit is connected to the input terminal of the delay circuit; the output terminal of the delay circuit is connected to the input terminal of the control circuit; the output terminal of the control circuit serves as the output terminal of the adjustment circuit and is connected to the control terminal of the inverter.

3. The resonant clock network according to claim 2, characterized in that, The inverter includes a first switching element and a second switching element; The output terminals of the control circuit include a first output port and a second output port; the control signal includes a first signal and a second signal; the operating state is a first on state, a second on state, or an off state; One end of the first switching element is connected to the power supply, and the other end of the first switching element is connected to one end of the second switching element, the resonant branch, and the load. The other end of the second switching element is grounded. The control terminals of the first and second switching elements serve as the control terminals of the inverter and are respectively connected to the first and second output ports of the control circuit. The control circuit is specifically configured to process the initial clock signal and the phase-adjusted clock signal, and then output a first signal to the first switching element and a second signal to the second switching element. The first signal is used to control the first switching element to be turned on or off; the second signal is used to control the second switching element to be turned on or off. The closed state is used to characterize the state when both the first switching element and the second switching element are turned off; the first on state is used to characterize the state when the first switching element is on and the second switching element is off; the second on state is used to characterize the state when the first switching element is off and the second switching element is on.

4. The resonant clock network according to claim 3, characterized in that, The delay circuit includes: a plurality of buffers connected in series and a data selector corresponding to each buffer; The input terminal of the first buffer in the plurality of buffers connected in series is connected to the first input terminal of its corresponding data selector, and the second input terminal of the data selector is connected to the output terminal of the first buffer; the input terminal of the first buffer is used to receive the initial clock signal. The first input terminal of the data selector corresponding to the non-first buffer in the plurality of buffers connected in series is connected to the output terminal of the data selector corresponding to the buffer preceding the non-first buffer, and the second input terminal of the data selector corresponding to the non-first buffer is connected to the output terminal of the buffer corresponding to it. The control terminal of the data selector is connected to the output terminal of the signal generation circuit, and is used to receive the delayed signal output by the signal generation circuit. The delayed signal is used to control the data selector to select the output signal. The output terminal of the data selector corresponding to the last buffer in the plurality of buffers connected in series in sequence serves as the output terminal of the delay circuit and is connected to the input terminal of the control circuit.

5. The resonant clock network according to claim 3, characterized in that, The delay circuit includes: a plurality of delay units connected in series and a plurality of transmission units connected in series; the delay units and the transmission units correspond one-to-one. The output of the delay unit is connected to the input of its corresponding transmission unit; The control terminal of the last delay unit in the plurality of delay units connected in series is grounded; the control terminal of the non-last delay unit in the plurality of delay units connected in series is connected to the output terminal of the signal generation circuit. The output terminal of the transmission unit corresponding to the first delay unit in the plurality of sequentially connected delay units serves as the output terminal of the delay circuit and is connected to the input terminal of the control circuit; the input terminal of the first delay unit is used to receive the initial clock signal; wherein, the delay signal is used to control the turn-on or turn-off of the delay unit; the transmission unit corresponding to the last delay unit in the plurality of sequentially connected delay units is connected to the reference voltage; When the delay unit is in the on state, the delay unit is used to transmit the received signal to the next delay unit connected in series with it; when the delay unit is in the off state, the delay unit is used to transmit the received signal to the output terminal of the transmission unit corresponding to the first delay unit through the corresponding transmission unit.

6. The resonant clock network according to claim 5, characterized in that, The transmission unit includes a first NAND gate circuit; the delay unit includes a second NAND gate circuit, a third NAND gate circuit, and a first NOT gate circuit. For each non-first delay unit in a plurality of delay units connected in series, the second input terminal of the second NAND gate circuit in the delay unit is connected to the output terminal of the second NAND gate circuit in the preceding delay unit; for the first delay unit in a plurality of delay units connected in series, the second NAND gate circuit in the delay unit is used to receive the initial clock signal; In the last delay unit among the plurality of delay units connected in series, the first input terminal of the second NAND gate and the input terminal of the first NOT gate are connected to ground. In the plurality of delay units connected in series, except for the last delay unit, the first input terminal of the second NAND gate is connected to the input terminal of the first NOT gate and the output terminal of the signal generation circuit. In each of the delay units, the output terminal of the first NOT gate is connected to the first input terminal of the third NAND gate; the second input terminal of the second NAND gate is connected to the second input terminal of the third NAND gate; the output terminal of the third NAND gate serves as the output terminal of the delay unit and is connected to the input terminal of its corresponding first NAND gate. The output terminal of the first NAND gate circuit corresponding to the first delay unit in the plurality of delay units connected in series in sequence serves as the output terminal of the delay circuit and is connected to the input terminal of the control circuit. The first NAND gate circuit corresponding to the last delay unit in the plurality of delay units connected in series is connected to the reference voltage.

7. The resonant clock network according to any one of claims 3-6, characterized in that, The control circuit includes: an AND gate circuit and an OR gate circuit; The first input terminal of the OR gate is connected to the first input terminal of the AND gate for receiving the initial clock signal; the second input terminal of the OR gate is connected to the second input terminal of the AND gate and the output terminal of the delay circuit; the output terminal of the OR gate serves as the first output port of the control circuit and is connected to the control terminal of the first switching element; the output terminal of the AND gate serves as the second output port of the control circuit and is connected to the control terminal of the second switching element.

8. The resonant clock network according to any one of claims 3-6, characterized in that, The resonant clock network further includes: a second NOT gate circuit; the control circuit includes: a fourth NAND gate circuit and a NOR gate circuit; The input terminal of the second NOT gate is connected to the output terminal of the delay circuit, and the output terminal of the delay circuit is connected to the first input terminal of the fourth NAND gate and the first input terminal of the NOR gate through the second NOT gate. The second input terminal of the fourth NAND gate is connected to the second input terminal of the NOR gate to receive the initial clock signal; the output terminal of the fourth NAND gate serves as the first output port of the control circuit and is connected to the control terminal of the first switching element; the output terminal of the NOR gate serves as the second output port of the control circuit and is connected to the control terminal of the second switching element.

9. The resonant clock network according to any one of claims 1-6, characterized in that, The duration for which the inverter is in the off state satisfies the following condition with respect to the frequency value of the initial clock signal: the higher the frequency value of the initial clock signal, the shorter the duration for which the inverter is in the off state.

10. The resonant clock network according to any one of claims 1-6, characterized in that, The duration for which the inverter is in the off state satisfies the following condition related to the voltage value of the power supply: the higher the voltage value of the power supply, the longer the inverter is in the off state.

11. The resonant clock network according to any one of claims 1-6, characterized in that, The duration for which the inverter is in the off state satisfies the following condition related to the capacitance value of the load: the larger the capacitance value of the load, the shorter the duration for which the inverter is in the off state.

12. A chip, characterized in that, Includes the resonant clock network as described in any one of claims 1-11.

13. An electronic device, characterized in that, Includes the resonant clock network as described in any one of claims 1-11.

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