A bilateral edge D flip-flop based on memristor and electronic product

Abstract

The application discloses a kind of based on memristor double-edge D trigger and electronic product, belong to logic operation device design technical field, the double-edge D trigger includes: bipolarity memristor M1~M3, switching device TG1~TG6, voltage comparator COMP, inverter INV1 and fixed resistance R, by a pair of reverse series memristor (M1, M2 or M2, M3) structure to input data D is stored, data is stored in the form of resistance in data storage memristor M1 or M3.By fixed resistance and memristor series voltage division structure, finally by comparator output follow-up result.The above-mentioned based on memristor double-edge D trigger, since guarantee the non-volatility of data, can also improve the transmission rate of data.

Description

Technical Field

[0001] This invention belongs to the field of logic device design technology, and more specifically, relates to a memristor-based dual-edge D flip-flop and electronic product. Background Technology

[0002] Building a complete system requires not only basic Boolean logic and arithmetic units, but also flip-flops needed to perform timing functions. Among various flip-flops, the D flip-flop is the most widely used, and other types such as JK flip-flops, T flip-flops, and T' flip-flops can all be derived from D flip-flops. The working principle of a double-edge-triggered D flip-flop is as follows: the input signal is output at the rising or falling edge of the clock signal, and the output remains unchanged when the clock signal stabilizes at a high or low level. Double-edge-triggered D flip-flops have higher data transmission efficiency at the same clock frequency compared to rising-edge or falling-edge-triggered D flip-flops, playing a crucial role in performing complex timing calculations.

[0003] Due to its fast read / write speed, low power consumption, long lifespan, and good CMOS compatibility, memristors are strong contenders for next-generation non-volatile memory. The resistance of a memristor changes according to the magnitude and direction of the applied voltage and current. This resistance change process is non-volatile, meaning that the memristor's resistance remains stable after the electrical operation is complete. The high-resistance state and the low-resistance state can represent "0" and "1" data, respectively, thus achieving the purpose of information storage.

[0004] The flip-flop function is implemented using memristors, where data is stored in the memristor in the form of resistance, and the calculation process is non-volatile. Patent "CN201210574495.X - A Non-Volatile D Flip-Flop Based on Memristors" uses a pair of inverted series memristors as the main components to implement a D latch, and further employs a master-slave structure to achieve single-edge D flip-flop functionality. Patent "CN201610054562.3 - A Non-Volatile D Flip-Flop Circuit Based on Memristors" uses a structure of one memristor and one fixed resistor as the main components to implement a D latch, and further employs a master-slave structure to achieve single-edge D flip-flop functionality.

[0005] However, current designs all rely on memristors to achieve single-edge triggering. While this ensures data non-volatility, it limits data transmission efficiency. Therefore, a scheme based on memristors to achieve dual-edge triggering is needed, which can improve data transmission rate while maintaining data non-volatility. Summary of the Invention

[0006] In view of the above-mentioned defects or improvement needs of the existing technology, the present invention provides a dual-edge D flip-flop based on memristor and an electronic product. The purpose is to design a dual-edge D flip-flop that can both ensure the non-volatility of data and improve the data transmission rate.

[0007] To achieve the above objectives, according to one aspect of the present invention, a memristor-based dual-edge D flip-flop is provided, comprising: bipolar memristors M1-M3, switching devices TG1-TG6, a voltage comparator COMP, an inverter INV1, and a fixed resistor R, wherein...

[0008] The upper electrode of memristor M1 is connected to the input signal D via switching device TG1 and to the inverting input terminal of voltage comparator COMP via switching device TG6. The lower electrode of memristor M1 is connected to the lower electrode of memristor M2, and the upper electrode of memristor M2 is connected to the upper electrode of memristor M3. The lower electrode of memristor M3 is connected to the inverting input terminal of voltage comparator COMP via switching device TG3. The inverting input terminal of voltage comparator COMP is also connected to a fixed voltage Vread via a fixed resistor R, the non-inverting input terminal is used to connect to a reference voltage Vreff, and the output terminal serves as the output terminal of a dual-edge D flip-flop. The connection terminal between memristor M1 and memristor M2 is grounded via switching device TG5. The connection terminal between memristor M2 and memristor M3 is grounded via switching device TG2. The input terminal of inverter INV1 is used to connect to the external input signal D, and the output terminal is connected to the lower electrode of memristor M3 via switching device TG4.

[0009] The control terminals of switching devices TG1 to TG6 are all controlled by the clock signal clock. When the dual-edge D flip-flop is working: if the clock signal clock is in the first level state, then switching devices TG1 to TG3 are turned on, and switching devices TG4 to TG6 are turned off. The output level of voltage comparator COMP is opposite to the resistance state of memristor M3. If the clock signal clock is in the second level state, then switching devices TG1 to TG3 are turned off, and switching devices TG4 to TG6 are turned on. The output level of voltage comparator COMP is opposite to the resistance state of memristor M1.

[0010] In one embodiment, the resistance of each memristor in the low-resistance state is R. LRS The resistance in the high-resistance state is R. HRS resistance R HRS Compared to the resistance R, which is an order of magnitude larger, the resistance of R is compared to the resistance of R. LRS An order of magnitude larger.

[0011] In one embodiment, the voltage corresponding to the input signal D being at a high level is V. HD The voltage corresponding to a low level is V.LD The set voltage of each memristor is V. set The reset voltage is V. reset Each voltage satisfies

[0012] In one embodiment, V HD =|V LD |

[0013] In one embodiment, V set =0.5V, V reset = -0.5V, V HD =6V, V LD = -6V, the resistance of each memristor in the low-resistance state is R LRS =1kΩ, the resistance in the high-resistance state is R HRS =100kΩ, the resistance of resistor R is R=10kΩ, the fixed voltage Vread=0.4V, and the reference voltage Vreff=0.2V.

[0014] In one embodiment, the switching devices TG1 to TG6 are output gates or MOSFETs.

[0015] In one embodiment, a power supply module is also included to provide a fixed voltage Vread and a reference voltage Vreff, satisfying:

[0016]

[0017]

[0018]

[0019]

[0020] In the formula, R MLRS R M3.LRS These are the resistance values ​​of memristors M1 and M3 in their low-resistance state, respectively, R. MHRS R M3.HRS These are the resistance values ​​of memristors M1 and M3 in the high-resistivity state, respectively.

[0021] In one embodiment, a clock module is also included for providing a clock signal.

[0022] According to another aspect of the invention, an electronic product is provided, comprising the above-described memristor-based dual-edge D flip-flop.

[0023] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects:

[0024] This invention employs three memristors, one fixed resistor, one voltage comparator, one inverter, and several switching devices to implement a dual-edge triggered D flip-flop. Memristor M2 serves as an auxiliary memristor, forming an anti-parallel series structure with memristors M1 and M3. Memristors M1 and M3 are used to store the input signal D. Because of the introduction of non-volatile memristors to store the input signal, even if power is lost, the input signal remains resistively stored in the memristors, ensuring data non-volatility. The clock signal has two levels: a high level "1" and a low level "0". When the clock signal is in different states, different memristors are connected to the circuit via a linkage switching device, realizing the dual-edge D triggering function. That is, the input signal D can be output on both the rising and falling edges of the clock, resulting in faster data transmission rates. Therefore, the above-described memristor-based dual-edge D flip-flop not only ensures data non-volatility but also improves the data transmission rate. Moreover, the circuit structure of this dual-edge D flip-flop is simple, and the power consumption and quiescent current are low.

[0025] Furthermore, the resistance value R HRS Compared to the resistance R, which is an order of magnitude larger, the resistance of R is compared to the resistance of R. LRS This is an order of magnitude larger. Therefore, when the output of the voltage comparator COMP needs to output a low level, the voltage at its inverting input is a larger value, and when the output of the voltage comparator COMP needs to output a low level, the voltage at its inverting input is a smaller value. This makes it easy to set other parameters to ensure that the high / low level of the voltage comparator COMP output is opposite to the high / low resistance state of the memristor M3.

[0026] Furthermore, the set voltage of each memristor is V. set The reset voltage is V. reset Each voltage satisfies This ensures that the input signal D can store information in the memristor and that the output level of the voltage comparator COMP is opposite to the resistance state of the memristor M3, thereby enabling the D trigger function to be realized on both edges. Attached Figure Description

[0027] Figure 1 A circuit symbol diagram of a bipolar memristor according to one embodiment;

[0028] Figure 2 This is a detailed circuit diagram of a memristor-based dual-edge D flip-flop according to one embodiment;

[0029] Figure 3 This is an equivalent circuit diagram of an embodiment where the clock is in the first level state;

[0030] Figure 4This is an equivalent circuit diagram of an embodiment where the clock is in the second level state;

[0031] Figure 5 The image shows a simulation waveform of a memristor-based dual-edge D flip-flop according to one embodiment. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0033] like Figure 1 The diagram shows a circuit symbol of a bipolar memristor in one embodiment. The bipolar memristor has an upper electrode and a lower electrode. The electrical operation of the memristor is divided into a set operation and a reset operation. For a bipolar memristor, the set operation involves applying a positive set voltage to the memristor, and the reset operation involves applying a negative reset voltage. After a set operation, the memristor changes from a high-resistance state to a low-resistance state, indicating that the memristor is set to "1"; after a reset operation, the memristor changes from a low-resistance state to a high-resistance state, indicating that the memristor is set to "0".

[0034] like Figure 2 The diagram shown is a specific circuit diagram of a memristor-based dual-edge D flip-flop in one embodiment, which includes bipolar memristors M1 to M3, switching devices TG1 to TG6, voltage comparator COMP, inverter INV1, and fixed resistor R. In this circuit, the upper electrode of memristor M1 is connected to the input signal D via switching device TG1 and to the inverting input terminal of voltage comparator COMP via switching device TG6. The lower electrode of memristor M1 is connected to the lower electrode of memristor M2, and the upper electrode of memristor M2 is connected to the upper electrode of memristor M3. The lower electrode of memristor M3 is connected to the inverting input terminal of voltage comparator COMP via switching device TG3. The inverting input terminal of voltage comparator COMP is also connected to a fixed voltage Vread via a fixed resistor R, the non-inverting input terminal is used to connect to a reference voltage Vreff, and the output terminal serves as the output terminal of a dual-edge D flip-flop. The connection terminal between memristor M1 and memristor M2 is grounded via switching device TG5. The connection terminal between memristor M2 and memristor M3 is grounded via switching device TG2. The input terminal of inverter INV1 is used to connect to the external input signal D, and the output terminal is connected to the lower electrode of memristor M3 via switching device TG4.

[0035] The control terminals of switching devices TG1 to TG6 are all controlled by the clock signal clock. The clock signal clock has two levels: a low level (clock = 0) and a high level (clock = 1).

[0036] When the double-edge D flip-flop is working:

[0037] If the clock signal clock is in the first level state, then the switching devices TG1~TG3 are turned on, the switching devices TG4~TG6 are turned off, and the output level of the voltage comparator COMP is opposite to the resistance state of the memristor M3.

[0038] If the clock signal is in the second level state, then the switching devices TG1 to TG3 are turned off, and the switching devices TG4 to TG6 are turned on. The output level of the voltage comparator COMP is opposite to the resistance state of the memristor M1.

[0039] In this case, one of the first level state and the second level state is clock=0 and the other is clock=1. Specifically, the first level state can be clock=0 and the second level state can be clock=1; or the first level state can be clock=1 and the second level state can be clock=0.

[0040] With the above circuit structure, D triggering can be achieved at both edges of the clock signal. The following explanation uses a first level state of clock = 0 and a second level state of clock = 1 as an example.

[0041] When the clock signal clock = 1:

[0042] Switching devices TG1-TG3 are turned on, and switching devices TG4-TG6 are turned off, forming a situation as follows: Figure 3 The circuit structure is shown. In this configuration, memristors M1 and M2 form an inverted series connection. The upper electrode of M1 is connected to the input signal D, and the lower electrode of M1 is connected to the lower electrode of M2. The upper electrode of memristor M2 is connected to ground gnd via TG2. One end of the fixed resistor R is connected to a fixed voltage Vread, and the other end is connected to the negative terminal of comparator COMP and then to the lower electrode of memristor M3 via transmission gate TG3. The upper electrode of memristor M3 is connected to ground gnd via TG2.

[0043] When the clock signal is at this level, there are two aspects of signal processing inside the circuit:

[0044] On one hand, the memristors M1 and M2 are electrically operated through the input signal D, and the resistance state of memristors M1 and M2 varies with different input signals D. At this time, the input signal does not affect the resistance state of memristor M3, which remains unchanged, maintaining the resistance state at the last moment of the clock signal clock=0. Specifically, if the input data D is high (D=1), then memristor M1 is set to "1", making it a low-resistance state, and memristor M2 is set to "0", making it a high-resistance state; if the input data D is low (D=0), then memristor M1 is set to "0", making it a high-resistance state, and memristor M2 is set to "1", making it a low-resistance state.

[0045] On the other hand, when the clock signal transitions from clock=0 to clock=1, the comparator COMP outputs the result of following the input signal D. Specifically, the memristor M3 and the fixed resistor R form a series voltage divider structure, and the voltage at the inverting input of the comparator is... Further comparison with the positive terminal voltage Vreff yields the output Vout. Where R... M3 Let M3 be the resistance value of memristor M3 at the current moment. The resistance value of memristor M3 varies depending on its state, and the resistance state of memristor M3 is controlled by the electrical operation result of the input signal D when the clock signal clock = 0 (refer to the analysis of clock signal clock = 1 for details). In this invention, by setting appropriate parameters so that the output level of voltage comparator COMP is opposite to the resistance state of memristor M3, the input signal D at the moment before the rising edge of the clock signal transitions from clock = 0 to clock = 1 can be output.

[0046] If the input signal D is high (D=1) just before the rising edge (i.e., at the last moment before clock=0), it will set memristor M3 to "1", making memristor M3 a low-impedance state. When the rising edge arrives, memristor M3 will be in a low-impedance state, R M3 =R M3.LRS R M3.LRS R is the resistance value of memristor M3 in the low-resistance state. M3 Smaller, comparator inverting input voltage It is relatively small and easy to set appropriate parameters to make This will enable the comparator COMP output to go high, i.e., Vout = 1 = D;

[0047] If the input signal D is low (D=0) just before the rising edge (i.e., at the last moment before clock=0), it will set memristor M3 to "0", making memristor M3 a high-impedance state. When the rising edge arrives, memristor M3 will be in a high-impedance state, R M3 =R M3.HRS R M3.HRSR is the resistance value of memristor M3 in the high-resistance state. M3 Larger voltage at the inverting input of the comparator It is relatively large, and it is easy to set appropriate parameters to make This will cause the comparator COMP output to go low, i.e., Vout = 0 = D.

[0048] Therefore, the most recently input signal D can be output on the rising edge of the clock signal to achieve the rising edge D trigger function.

[0049] When the clock signal clock = 0:

[0050] Switching devices TG1-TG3 are turned off, and switching devices TG4-TG6 are turned on, forming a situation as follows: Figure 4 The circuit structure is shown. In this configuration, memristors M3 and M2 form an inverting series structure. The input signal D is connected to the lower electrode of M3 via inverter INV1. The upper electrode of M3 is connected to the upper electrode of M2. The lower electrode of memristor M2 is connected to ground gnd via TG5. One end of the fixed resistor R is connected to a fixed voltage Vread, and the other end is connected to the negative terminal of comparator COMP and then to the upper electrode of memristor M1 via transmission gate TG6. The lower electrode of memristor M1 is connected to ground gnd via TG5.

[0051] When the clock signal is at this level, there are two aspects of signal processing inside the circuit:

[0052] On one hand, the memristors M2 and M3 are electrically operated through the input signal D, and the resistance state of memristors M2 and M3 varies with the input signal D. At this time, the input signal D does not affect the resistance state of memristor M1, while the resistance state of memristor M3 remains unchanged, maintaining the resistance state at the last moment of the clock signal clock=1. Specifically, if the input data D is high (D=1), then memristor M3 is set to "1", making it a low-resistance state, and memristor M2 is set to "0", making it a high-resistance state; if the input data D is low (D=0), then memristor M3 is set to "0", making it a high-resistance state, and memristor M2 is set to "1", making it a low-resistance state.

[0053] On the other hand, when the clock signal transitions from clock=1 to clock=0, the comparator COMP outputs the result of following the input signal D. Specifically, the memristor M1 and the fixed resistor R form a series voltage divider structure, and the voltage at the inverting input of the comparator is... Further comparison with the positive terminal voltage Vreff yields the output Vout. Where R... M1Let M1 be the resistance value of memristor M1 at the current moment. The resistance value of memristor M1 varies depending on its state, and the resistance state of memristor M1 is controlled by the electrical operation result of the input signal D when the clock signal clock=1 (refer to the analysis of the clock signal clock=1 for details). In this invention, by setting appropriate parameters so that the output level of the voltage comparator COMP is opposite to the resistance state of memristor M3, the input signal D at the moment before the rising edge of the clock signal transitions from clock=1 to clock=0 can be output.

[0054] If the input signal D is high (D=1) just before the falling edge (i.e., at the last moment of clock=1), it will set memristor M1 to "1", making memristor M1 a low-impedance state. When the falling edge arrives, memristor M1 will be in a low-impedance state, and R... M1 =R M1.LRS R M1.LRS R is the resistance value of memristor M1 in the low-resistance state. M1 Smaller, comparator inverting input voltage It is relatively small and easy to set appropriate parameters to make This will enable the comparator COMP output to go high, i.e., Vout = 1 = D;

[0055] If the input signal D is low (D=0) just before the falling edge (i.e., at the last moment before clock=0), it will set memristor M1 to "0", making memristor M1 a high-impedance state. When the falling edge arrives, memristor M1 will be in a high-impedance state, R M1 =R M1.HRS R M1.HRS R is the resistance value of memristor M1 in the high-resistance state. M1 Larger voltage at the inverting input of the comparator It is relatively large, and it is easy to set appropriate parameters to make This will cause the comparator COMP output to go low, i.e., Vout = 0 = D.

[0056] Therefore, the most recently input signal D can be output on the falling edge of the clock signal to achieve the falling edge D trigger function.

[0057] The above explanation uses the example of clock=0 for the first level state and clock=1 for the second level state. Alternatively, the first level state can be clock=1 and the second level state can be clock=0. Just construct two different circuits for the two different states.

[0058] Therefore, with the above circuit structure, the D trigger function can be realized at both edges of the clock signal.

[0059] In one embodiment, all memristors have the same parameters, and the resistance of each memristor in the low-resistance state is R. LRS The resistance in the high-resistance state is R. HRS When selecting a memristor and setting its parameters, the resistance value R can be adjusted. HRS Compared to the resistance R, which is an order of magnitude larger, the resistance of R is compared to the resistance of R. LRS This is an order of magnitude larger. Therefore, when the output of the voltage comparator COMP needs to output a low level, the voltage at its inverting input is a larger value, and when the output of the voltage comparator COMP needs to output a low level, the voltage at its inverting input is a smaller value. This makes it easy to set other parameters to ensure that the high / low level of the voltage comparator COMP output is opposite to the high / low resistance state of the memristor M3.

[0060] Using this dual-edge D flip-flop, as long as the input signal D satisfies the following conditions: when the input signal D is high, it can set memristor M1 to a low-impedance state and simultaneously reset memristor M2 to a high-impedance state, and set memristor M3 to a low-impedance state and simultaneously reset memristor M2 to a high-impedance state; when the input signal D is low, it can reset memristor M1 to a low-high-impedance state and simultaneously set memristor M2 to a low-impedance state, and reset memristor M3 to a high-impedance state and simultaneously set memristor M2 to a low-impedance state. In one embodiment, the voltage corresponding to the input signal D being high is defined as V. HD The voltage corresponding to a low level is V. LD The set voltage of each memristor is V. set The reset voltage is V. reset Each voltage satisfies This ensures that the above conditions are met. Typically, the absolute values ​​of the amplitudes of the high and low levels of the input signal D are equal, i.e., V... HD =|V LD |

[0061] In one specific embodiment, the parameters can be set as follows:

[0062] V set =0.5V, V reset = -0.5V, V HD =1.6V, V LD = -1.6V, the resistance of each memristor in the low-resistance state is R LRS =1kΩ, the resistance in the high-resistance state is R HRS =100kΩ, resistor R has a resistance of R = 10kΩ, fixed voltage Vread = 0.4V, reference voltage Vreff = 0.2V. At this time, if the memristor used as a voltage divider is in a low-resistance state, the voltage at the inverting input of the comparator is... The comparator outputs a high level. If the memristor used as a voltage divider is in a high-impedance state, the voltage at the inverting input of the comparator is... The comparator outputs a low level. With the above parameter settings, the input signal D can store information in the memristor and make the output level of the voltage comparator COMP opposite to the resistance state of the memristor M3, thus enabling D triggering function to be achieved on both edges.

[0063] In one embodiment, the switching devices TG1 to TG6 are output gates or MOSFETs, or other controllable switches.

[0064] In one embodiment, the fixed voltage Vread and the reference voltage Vreff can be externally connected, or a power supply module can be set inside the dual-edge D flip-flop to provide the fixed voltage Vread and the reference voltage Vreff. Based on the above analysis, the parameter relationship between the power supply module and other components must satisfy:

[0065]

[0066]

[0067]

[0068]

[0069] In one embodiment, the clock signal can be accessed externally or a clock module can be set inside the dual-edge D flip-flop to provide the clock signal.

[0070] Accordingly, the present invention also relates to an electronic product comprising the memristor-based dual-edge D flip-flop described above.

[0071] The above analysis shows that under different clock levels clock = 1 / clock = 0: the auxiliary memristor M2 forms an inverse series structure with memristor M1 / memristor M3 respectively, and stores the input data D in memristor M1 / memristor M3. At the same time, the readout circuit reads out the resistance information of memristor M3 / memristor M1 respectively, thus finally realizing the function of the dual-edge triggered D flip-flop. Figure 5 The simulation results are based on the CR Microelectronics 0.18µm CMOS process, and the simulation environment is Cadence Virtuoso. The memristor Verilog-A model used is configured with set and reset threshold voltages of 0.5V and -0.7V, respectively, based on the DC sweep curve of the actual memristor device. This invention directly implements the function of a dual-edge D flip-flop using a memristor. The circuit is not only non-volatile but also has low power consumption and small circuit area.

[0072] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A dual-edge D flip-flop based on a memristor, characterized in that, include: The components include bipolar memristors M1-M3, switching devices TG1-TG6, voltage comparator COMP, inverter INV1, and fixed resistor R. The upper electrode of memristor M1 is connected to the input signal D via switching device TG1 and to the inverting input terminal of voltage comparator COMP via switching device TG6. The lower electrode of memristor M1 is connected to the lower electrode of memristor M2, and the upper electrode of memristor M2 is connected to the upper electrode of memristor M3. The lower electrode of memristor M3 is connected to the inverting input terminal of voltage comparator COMP via switching device TG3. The inverting input terminal of voltage comparator COMP is also connected to a fixed voltage Vread via a fixed resistor R, the non-inverting input terminal is used to connect to a reference voltage Vreff, and the output terminal serves as the output terminal of a dual-edge D flip-flop. The connection terminal between memristor M1 and memristor M2 is grounded via switching device TG5. The connection terminal between memristor M2 and memristor M3 is grounded via switching device TG2. The input terminal of inverter INV1 is used to connect to the external input signal D, and the output terminal is connected to the lower electrode of memristor M3 via switching device TG4. The control terminals of switching devices TG1 to TG6 are all controlled by the clock signal clock. When the dual-edge D flip-flop is working: if the clock signal clock is in the first level state, then switching devices TG1 to TG3 are turned on, and switching devices TG4 to TG6 are turned off. The output level of voltage comparator COMP is opposite to the resistance state of memristor M3. If the clock signal clock is in the second level state, then switching devices TG1 to TG3 are turned off, and switching devices TG4 to TG6 are turned on. The output level of voltage comparator COMP is opposite to the resistance state of memristor M1.

2. The memristor-based dual-edge D flip-flop as described in claim 1, characterized in that, The resistance of each memristor in the low-resistance state is R. LRS The resistance in the high-resistance state is R. HRS resistance R HRS Compared to the resistance R, which is an order of magnitude larger, the resistance of R is compared to the resistance of R. LRS An order of magnitude larger.

3. The memristor-based dual-edge D flip-flop as described in claim 1, characterized in that, The voltage corresponding to the input signal D being at a high level is V. HD The voltage corresponding to a low level is V. LD The set voltage of each memristor is V. set The reset voltage is V. reset Each voltage satisfies 4. The memristor-based dual-edge D flip-flop as described in claim 1, characterized in that, V HD =|V LD | 5. The memristor-based dual-edge D flip-flop as described in claim 3, characterized in that, V set =0.5V, V reset = -0.5V, V HD =1.6V, V LD = -1.6V, the resistance of each memristor in the low-resistance state is R LRS =1kΩ, the resistance in the high-resistance state is R HRS =100kΩ, the resistance of resistor R is R=10kΩ, the fixed voltage Vread=0.4V, and the reference voltage Vreff=0.2V.

6. The memristor-based dual-edge D flip-flop as described in claim 1, characterized in that, The switching devices TG1 to TG6 are output gates or MOSFETs.

7. The memristor-based dual-edge D flip-flop as described in claim 1, characterized in that, It also includes a power supply module to provide a fixed voltage Vread and a reference voltage Vreff, satisfying: In the formula, R M1.LRS R M3.LRS These are the resistance values ​​of memristors M1 and M3 in their low-resistance state, respectively, R. M1.HRS R M3.HRS These are the resistance values ​​of memristors M1 and M3 in the high-resistivity state, respectively.

8. The memristor-based dual-edge D flip-flop as described in claim 1, characterized in that, It also includes a clock module for providing the clock signal.

9. An electronic product, characterized in that, It includes a memristor-based dual-edge D flip-flop as described in any one of claims 1 to 8.

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