A non-volatile majority gate logic circuit based on memristors and its control method

Abstract

This invention discloses a non-volatile majority gate logic circuit based on memristors and its control method, belonging to the field of microelectronic device technology. It employs n+1 memristors to implement majority gate logic operations with n logic inputs, where one memristor serves as the output memristor and the other n memristors as input memristors. By setting the resistance values ​​of the n input memristors as the n logic input variables of the majority gate, grounding the positive terminals of the n input memristors, and applying a fixed voltage V0 to the positive terminal of the output memristor and the second terminal of the resistor, the result of the majority gate logic operation can be obtained. This invention maintains the written input information values ​​in the input memristor state after the logic calculation is completed, without destructive behavior towards the input information. It realizes a majority gate logic circuit where both input and output variables are memristor resistance values, and the operation process is non-destructive. This circuit has strong data reuse capabilities and can reduce hardware overhead when performing logic cascading.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic device technology, and more specifically, relates to a non-volatile majority gate logic circuit based on memristors and its control method. Background Technology

[0002] Logic optimization involves manipulating logical representation structures to minimize certain objective metrics. Logic optimization methods are closely linked to the data structures that run them, and the logic primitives of Majority-Inverter Graphs (MIGs) themselves demonstrate efficient logic synthesis potential. MIGs are a novel data logic representation structure. Compared to traditional data structures such as Binary Decision Diagrams (BDDs) and And-In-Veter Graphs (AIGs), MIGs often require less logic depth to implement the same complex logic, thus showing better experimental results in terms of propagation delay. MIGs consist of majority gate logic (MAJ) and negation logic. The majority gate logic is a crucial component of MIGs; its logical operation is: the output of the majority logic is true when more than half of the inputs are true, otherwise it is false. Therefore, studying majority gate logic circuits is of great significance for better understanding MIGs.

[0003] Traditional computers employ the von Neumann architecture, where storage and processing units are physically separated. Typically, the processing unit reads data from storage, performs the necessary arithmetic and logical operations, and then writes the data back to storage. This frequent read and write process places a significant burden on the limited-speed bus and consumes a large portion of the power during data processing. The speeds of the processing and storage units are mismatched, and this speed difference is widening year by year. To address the aforementioned "von Neumann bottleneck" and "memory wall" problems, in-memory computing technology, with its advantages of high computational parallelism, low latency, and low power consumption, has been proposed and has gradually become a hot research topic in academia and industry.

[0004] Memristors, as a novel non-volatile memory device, possess advantages such as low power consumption, small size, and compatibility with CMOS processes, making them a strong candidate for in-memory computing architectures. Their high and low voltage configurations can store information, and their non-volatility—maintaining their resistive state even after power is removed—makes them naturally suitable for digital logic computation. By configuring the port voltages of memristors and switching their configurations accordingly, and encoding the voltage and configuration information, specified logical operations or complex arithmetic functions can be performed, thus achieving in-memory computing integration and significantly improving the speed and efficiency of information processing.

[0005] Existing memristor-based majority gate logic circuits, taking a three-input majority gate logic circuit as an example, often employ a single memristor. The input variables are the two port voltages of the memristor and its configuration information. After applying the appropriate port voltages, the logic operation is performed, and the result is the final configuration of the memristor. While this approach offers a simple structure and low hardware overhead when implementing a single majority gate logic, the logic operation result overwrites a previous resistance input variable, which is destructive to the input information. This leads to data non-reusability, requiring additional copying operations to preserve the data in practical applications. Furthermore, since the input variables include both port voltage and resistance values, while the output result only has a resistance value, during logic cascading, it is often necessary to convert the resistance value information of this logic operation result into voltage form for use as the port voltage variable in the next logic operation, introducing additional hardware overhead. Summary of the Invention

[0006] In view of the above-mentioned defects or improvement needs of the prior art, the present invention provides a non-volatile majority gate logic circuit based on memristors and its control method. The purpose is to realize a majority gate logic circuit in which both input and output variables are memristor resistance values ​​and the operation process is non-destructive.

[0007] To achieve the above objectives, in a first aspect, the present invention provides a non-volatile majority gate logic circuit based on memristors for implementing majority gate logic operations with n logic inputs, comprising: a controller, m identical memristors, and resistors; m ≥ n+1;

[0008] The positive terminals of m memristors are connected to the controller, and the negative terminals are all connected to the source line SL. After being led out through the source line SL, they are connected to the first end of the resistor, and the second end of the resistor is connected to the controller.

[0009] When the controller is working, it selects one memristor from m memristors as the output memristor and n memristors as the input memristors; it sets the output memristor to a high impedance state; it sets the n input memristors to the impedance states corresponding to the n logic inputs; it grounds the positive terminals of the n input memristors and applies a voltage V0 to the positive terminal of the output memristor and the second terminal of the resistor. At this time, the impedance state of the output memristor is the result of the majority gate logic operation.

[0010] Where n is an odd number greater than 1; voltage V0 satisfies:

[0011] and

[0012] R is the resistance value; R H R is the high-resistance resistance value of the memristor. LV is the low-resistance value of the memristor; set V is the threshold value for the memristor to transition from a high-resistance state to a low-resistance state. reset The threshold value at which a memristor transitions from a low-resistance state to a high-resistance state.

[0013] More preferably, the above-mentioned non-volatile majority gate logic circuit further includes: m transistors; the gates of the m transistors are connected to the same word line WL, the drains are connected to the negative terminals of the m memristors one by one, and the sources are connected to the source line SL.

[0014] At this point, the negative terminal of the memristor is connected to the aforementioned source line SL via the corresponding transistor;

[0015] The controller is also used to control the on / off state of each transistor. When performing majority gate logic operations, it turns on all n+1 transistors connected to the output memristor and the input memristor.

[0016] More preferably, the resistance value is on the same order of magnitude as the low-resistance resistance value of the memristor.

[0017] More preferably, This ensures that the logic implementation has sufficient voltage margin.

[0018] More preferably, when n = 3, the voltage V0 satisfies: and

[0019] More preferably, the memristor includes a high-resistance state and a low-resistance state; the high-resistance state corresponds to the logic value "0", and the low-resistance state corresponds to the logic value "1".

[0020] Secondly, the present invention provides a control method for the above-mentioned non-volatile majority gate logic circuit, used to implement majority gate logic operations with n logic inputs, including:

[0021] S1. Select one memristor from m memristors as the output memristor and n memristors as the input memristors; set the output memristor to a high impedance state; set the n input memristors to the impedance states corresponding to the n logic inputs respectively;

[0022] S2. Ground the positive terminals of the n input memristors, and apply a voltage V0 to the positive terminal of the output memristor and the second terminal of the resistor. At this time, the resistance state of the output memristor is the result of the majority gate logic operation.

[0023] Where n is an odd number greater than 1; voltage V0 satisfies:

[0024] and

[0025] R is the resistance value; R H R is the high-resistance resistance value of the memristor. L V is the low-resistance value of the memristor; set V is the threshold value for the memristor to transition from a high-resistance state to a low-resistance state. reset The threshold value at which a memristor transitions from a low-resistance state to a high-resistance state.

[0026] Thirdly, the present invention provides a method for cascading majority gate logic circuits based on the above-mentioned non-volatile majority gate logic circuits, comprising:

[0027] After the previous level logic operation is completed, the output memristor in the previous level logic operation is directly used as the input memristor in the current level logic operation to perform the current level logic operation.

[0028] Fourthly, the present invention provides a non-volatile majority gate logic parallel operation circuit, characterized in that it includes a plurality of non-volatile majority gate logic circuits provided in the first aspect of the present invention.

[0029] The positive terminals of memristors at the same location in each non-volatile majority gate logic circuit are connected to each other, so that multiple majority gate logic operations can be implemented in parallel within the same logic calculation pulse cycle.

[0030] Fifthly, the present invention also provides a computer-readable storage medium comprising a stored computer program, wherein, when the computer program is executed by a processor, it controls the device in which the storage medium is located to execute the control method in the non-volatile majority gate logic circuit provided in the second aspect of the present invention and / or the majority gate logic cascading method provided in the third aspect of the present invention.

[0031] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects:

[0032] 1. This invention provides a non-volatile majority gate logic circuit based on memristors. It uses n+1 memristors to implement majority gate logic operations with n logic inputs, where one memristor serves as the output memristor and the other n memristors serve as input memristors. By setting the resistance values ​​of the n input memristors as the n logic input variables of the majority gate, grounding the positive terminals of the n input memristors, and applying a fixed voltage V0 to the positive terminal of the output memristor and the second terminal of the resistor, the result of the majority gate logic operation can be obtained. After the logic calculation is completed, the state of the input memristors remains unchanged. This circuit, which does not destroy input information and is non-volatile, implements a majority gate logic circuit where both input and output variables are memristor resistance values ​​and the operation process is non-destructive. It boasts strong data reusability, eliminating the need for additional copying operations to save data in practical applications. Furthermore, during logic cascading, both input and output variables are represented using memristor configurations, eliminating the need to convert the resistance values ​​of this logic operation into voltage values ​​for use as port voltage variables in the next logic operation. This reduces hardware overhead, and the logic cascading is simple and easy to implement, facilitating the efficient implementation of more complex logic functions.

[0033] 2. Furthermore, the non-volatile majority gate logic circuit based on memristors provided by the present invention also includes transistors to prevent current leakage problems in the circuit.

[0034] 3. Furthermore, the non-volatile majority gate logic circuit based on memristors provided by the present invention, when implementing three-input majority gate logic operations, makes the resistance value of the resistor equal to the low-resistance resistance value of the memristor, so as to obtain a larger voltage margin.

[0035] 4. Furthermore, the non-volatile majority gate logic circuit based on memristors provided by this invention can realize majority gate logic operations with n logic inputs in just two steps, where n is an odd number greater than 1. It is simple, easy to implement, and has strong versatility.

[0036] 5. Furthermore, the non-volatile majority gate logic circuit based on memristors provided by the present invention supports large-scale parallel operation at the array level, and can be mapped in a 1T1R array to perform parallel calculation of multiple bits in one clock cycle in the array, which greatly improves the parallelism and efficiency of the calculation. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the structure of a three-input majority gate logic circuit provided in Embodiment 1 of the present invention;

[0038] Figure 2 This is the truth table for a three-input majority gate logic provided in Embodiment 1 of the present invention;

[0039] Figure 3The simulation waveform diagram with input 2LRS1HRS provided in Embodiment 1 of the present invention;

[0040] Figure 4 The simulation waveform diagram of the input 1LRS2HRS provided in Embodiment 1 of the present invention;

[0041] Figure 5 This is a schematic diagram of a non-volatile multi-gate logic parallel operation circuit provided in Embodiment 4 of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0043] Example 1

[0044] A non-volatile majority gate logic circuit based on memristors is used to implement majority gate logic operations with n logic inputs, where n is an odd number greater than 1;

[0045] Specifically, the aforementioned non-volatile majority gate logic circuit includes: a controller, m identical memristors, and resistors; m ≥ n+1; preferably, m = n+1;

[0046] The positive terminals of m memristors are connected to the controller, and the negative terminals are all connected to the source line SL. After being led out through the source line SL, they are connected to the first end of the resistor, and the second end of the resistor is connected to the controller.

[0047] When the controller is working, it selects one memristor from m memristors as the output memristor and n memristors as the input memristors; it sets the output memristor to a high impedance state; it sets the n input memristors to the impedance states corresponding to the n logic inputs; it grounds the positive terminals of the n input memristors and applies a voltage V0 to the positive terminal of the output memristor and the second terminal of the resistor. At this time, the impedance state of the output memristor is the result of the majority gate logic operation.

[0048] It should be noted that a memristor has two resistive states: a high-resistance state and a low-resistance state. The direction of the applied voltage is defined as from the top electrode to the bottom electrode, and from the bottom electrode to the top electrode, as the negative direction. When the positive voltage applied across the memristor exceeds the threshold voltage V... set When the forward voltage applied across the memristor is less than the threshold voltage V, the memristor transitions from a high-resistance state to a low-resistance state. resetWhen the memristor transitions from a low-resistance state to a high-resistance state, the high-resistance state (HRS) corresponds to the logic value "0" and has a resistance of R. H The low resistance state (LRS) of a memristor corresponds to the logic value "1" and has a resistance of R. L ;R L < <R H .

[0049] Let M be the number of n input memristors. (0,0) M (0,1) M (0,2) M (0,n-1) The output memristor is M (0,n) During the operation, the applied fixed voltage Vo needs to satisfy: Condition (1) When the input memristor M (0,0) M (0,1) M (0,2) ...M (0,n-1) middle When the above memristors are low impedance, M (0,n) Forward voltage is higher than V set The configuration is switched to low impedance "1"; when the input memristor M... (0,0) M (0,1) M (0,2) ...M (0,n-1) middle When one or more memristors are high impedance, M (0,n) Forward voltage is lower than V set The configuration maintains a high impedance of "0", and the logic operation of condition (2) does not affect the configuration of the input memristor.

[0050] Specifically, for condition (1), the key is to distinguish between the following two combinations of inputs:

[0051] 1) Among n input memristors LRS and One HRS;

[0052] 2) Among n input memristors LRS and One HRS;

[0053] For case 1):

[0054] By Kirchhoff's laws:

[0055]

[0056] Solving for:

[0057]

[0058] For case 2):

[0059] By Kirchhoff's laws:

[0060]

[0061] Solving for:

[0062]

[0063] Among them, V x This is the lower electrode voltage of the output memristor.

[0064] For the logic to execute correctly, the following condition must be met: In case 1), the forward voltage across the output memristor is less than V. set Maintain high impedance "0"; in case 2), the forward voltage across the output memristor is greater than V. set Set to low resistance "1", meaning the voltage V0 satisfies:

[0065]

[0066] On the other hand, regarding condition (2), during the logic operation, since the upper electrode of the input memristor is grounded, the forward voltage of the input memristor is less than 0. The destruction of input information only exists when the input memristor is reset in reverse. In order not to destroy the resistance value information of the input memristor, for all possible cases where the input memristor contains low resistance, it is necessary to ensure that the voltage amplitude across the input memristor is less than |V. reset | That is, the voltage V0 needs to further satisfy:

[0067]

[0068] Preferably, in an optional embodiment, the above-mentioned non-volatile majority gate logic circuit further includes: m transistors; the gates of the m transistors are connected to the same word line WL, the drains are connected to the negative terminals of the m memristors one by one, and the sources are connected to the source line SL.

[0069] At this point, the negative terminal of the memristor is connected to the aforementioned source line SL via the corresponding transistor;

[0070] The controller is also used to control the on / off state of each transistor. When performing majority gate logic operations, it turns on all n+1 transistors connected to the output memristor and the input memristor to prevent current leakage in the circuit.

[0071] To further illustrate the non-volatile majority gate logic circuit based on memristors provided by this invention, the following detailed description uses a three-input majority gate logic circuit with n=3 as an example:

[0072] like Figure 1 As shown, this three-input majority gate logic circuit includes: a controller, four identical memristors (M... (0,0) M (0,1) M (0,2) M (0,3) ), four identical transistors (in this embodiment, the transistors are enhancement-mode NMOS transistors), and a resistor R;

[0073] The positive terminals of the four memristors are connected to the controller via corresponding bit lines (BL0, BL1, BL2, BL3), and their negative terminals are connected to the drain terminals of the four transistors respectively. The gates of the four transistors are all connected to the same word line WL, and their sources are all connected to the same source line SL. Each source is led out through the source line SL and connected to the first terminal of resistor R, and the second terminal of resistor R is connected to the controller. One of the memristors, M... (0,3) As the output memristor, the other three memristors M (0,0) M (0,1) M (0,2) As an input memristor;

[0074] The controller is used to output the memristor M before performing most gate logic operations. (0,3) Set to high impedance state; when performing majority gate logic operations, set the three input memristors M (0,0) M (0,1) M (0,2) The three input memristors M are respectively set to the resistance states corresponding to the input logic values ​​a, b, and c, and the three input memristors M are... (0,0) M (0,1) M (0,2) The positive terminal is grounded, in the output memristor M (0,3) A voltage V0 is applied to the positive terminal and the second terminal of the resistor R.

[0075] To enable the output memristor M (0,3) The correct resistance change occurs when the input memristor M... (0,0) M (0,1) M (0,2) When two or more memristors are low impedance, M (0,3) Forward voltage is higher than V set When the configuration is switched to low impedance "1", the input memristor M (0,0) M (0,1) M (0,2) When two or more memristors are high impedance, M (0,3) Forward voltage is lower than V set The configuration maintains a high impedance of "0". The fixed voltage V0 should satisfy:

[0076]

[0077] Furthermore, to ensure that the information in the input memristor is not corrupted during the entire logic operation, the value of Vo should satisfy:

[0078]

[0079] Preferably, in order to ensure that the logic implementation has sufficient voltage margin, When n = 3, the resistance value is equal to the low-resistance state resistance value of the memristor, that is, R = R L And the high and low resistances satisfy R L < <R H The voltage constraint above can be further simplified to:

[0080]

[0081]

[0082] Based on the V of the memristor 1T1R structure set and V reset With voltages of 0.6V and -1V, high resistance RH = 100KΩ, and low resistance RL = 1KΩ, a fixed resistor of R = 1KΩ and V0 = 1.05V are selected. The simulation environment is Cadence Virtuoso, and the transistor selected is mn33 NMOS from the 0.18μm process library.

[0083] In summary, compared with existing logic computation schemes, the input and output variables of this invention are both memristor resistance information. The logic operations are non-volatile and non-destructive, and logic cascading is simple and easy to implement, facilitating the efficient implementation of more complex logic functions. Furthermore, since the excitation at the BL terminal is fixed during computation, and the leakage current problem is solved by employing a 1T1R array structure, this invention supports parallel computation of multiple bits within one clock cycle in the array, significantly improving computational parallelism and efficiency. This invention also possesses high scalability. By expanding the number of input memristors involved in the computation and applying appropriate port voltages, the logic operation principle using this scheme can still achieve majority gate logic with more input variables n (n being an odd number greater than 1) in only two steps.

[0084] Example 2

[0085] The control method for the non-volatile majority gate logic circuit described in Example 1 is used to implement majority gate logic operations with n logic inputs. The logic implementation includes the following two steps:

[0086] S1. Select one memristor from m memristors as the output memristor and n memristors as the input memristors; set the output memristor to a high impedance state; set the n input memristors to the impedance states corresponding to the n logic inputs respectively;

[0087] S2. Ground the positive terminals of the n input memristors, and apply a voltage V0 to the positive terminal of the output memristor and the second terminal of the resistor. At this time, the resistance state of the output memristor is the result of the majority gate logic operation.

[0088] Where n is an odd number greater than 1; voltage V0 satisfies:

[0089] and

[0090] R is the resistance value; R H R is the high-resistance resistance value of the memristor. L V is the low-resistance value of the memristor; set V is the threshold value for the memristor to transition from a high-resistance state to a low-resistance state. reset The threshold value at which a memristor transitions from a low-resistance state to a high-resistance state.

[0091] Similarly, as Figure 1 The control method for the three-input majority gate logic circuit shown is illustrated using the example above. The control method specifically includes the following two steps:

[0092] S1. Write the input variable information a, b, and c into the memristor M respectively. (0,0) M (0,1) M (0,2) ; output memristor M (0,3) Initialization, that is, setting it to a high-impedance state "0";

[0093] S2. Connect the transistor turn-on voltage V to the word line control pin WL0 of the word line WL. G With the transistors turned on, connect BL0, BL1, and BL2 to gnd. Apply a fixed voltage level V0 to the control pin SL0 of BL3 and the source line SL. The logic operation is completed, and the final result is stored in the memristor M. (0,3) middle.

[0094] Specifically, in the first step of the logic operation, the three input messages are written into three memristors M. (0,0) M (0,1) M (0,2) The output memristor M (0,3) Set to "0". In the second step of the logic operation, apply V to the WL0 terminal. G Turn on the transistors, connect BL0, BL1, and BL2 to gnd, and connect BL3 and SL0 to voltage V0 to complete the logic operation. For a combination of three inputs containing at least two low-impedance inputs (input combination: M...),... (0,0) =0, M (0,1) =1, M (0,2) =1; M (0,0) =1, M (0,1) =0, M(0,2) =1; M (0,0) =1, M (0,1) =1, M (0,2) =0;M (0,0) =1, M (0,1) =1, M (0,2) =1), memristor M (0,3) When the forward voltage is greater than Vset, the memristor M (0,3) Set to "1"; for a combination of 3 inputs, at most one low-impedance input (input combination: M) (0,0) =0, M (0,1) =0, M (0,2) =0;M (0,0) =0, M (0,1) =0, M (0,2) =1; M (0,0) =0, M (0,1) =1, M (0,2) =0;M (0,0) =1, M (0,1) =0, M (0,2) =0), memristor M (0,3) Forward voltage less than V set memristor M (0,3) No resistance change occurs, maintaining a high resistance of "0".

[0095] In summary, the three-input majority gate logic is completed in two steps. This scheme implements logic operations based on the voltage divider principle. The key to correct logic execution lies in distinguishing between the two input combinations: "2LRS1HRS" (i.e., the case of two 1s and one 0) and "1LRS2HRS" (i.e., the case of two 0s and one 1). As long as the output result is correct for these two input combinations, the other input combinations will also execute correctly. Figure 2 The truth table shown is output accurately. Furthermore, Figure 3 and Figure 4 The simulation results verify that the output memristor is set to low resistance "1" and maintained at high resistance "0" under the two inputs "2LRS1HRS" and "1LRS2HRS", respectively.

[0096] The relevant technical solutions are the same as in Embodiment 1, and will not be repeated here.

[0097] Example 3

[0098] A method for cascading majority gate logic based on the non-volatile majority gate logic circuit described in Embodiment 1, comprising:

[0099] After the previous level logic operation is completed, the output memristor in the previous level logic operation is directly used as the input memristor in the current level logic operation to perform the current level logic operation.

[0100] In one optional implementation, any input memristor in the previous level logic operation is used as the output memristor in the current level logic operation, and the output memristor in the previous level logic operation is used as a certain input memristor M in the current level logic operation. At the same time, the remaining n-1 input memristors in the previous level logic operation are still used as input memristors in the current level logic operation. The output memristor in the current level logic operation is set to a high impedance state. The remaining n-1 input memristors, except for input memristor M, are respectively set to the impedance states corresponding to the n-1 logic values ​​input to the current level logic operation.

[0101] Ground the positive terminals of the n input memristors in the current logic operation, and apply a voltage V0 to the positive terminal of the output memristor in the current logic operation and the second terminal of the resistor.

[0102] Preferably, based on the above implementation, when selecting an input memristor in the previous logic operation as the output memristor in the current logic operation, the input memristor in the previous logic operation that is in a high-impedance state can be used as the output memristor in the current logic operation, so that it is not necessary to set the output memristor in the current logic operation to a high-impedance state. Furthermore, when setting the remaining n-1 input memristors (excluding input memristor M) to the corresponding resistance states of the n-1 logic values ​​of the current stage logic operation, it is not necessary to re-state them all (input memristors whose resistance states correspond to the same logic values ​​as the current stage logic operation do not need to be re-stated). Instead, the logic values ​​corresponding to the current resistance states of the n-1 input memristors can be compared in random order with the n-1 logic values ​​of the current stage logic operation, and the input memristor with the fewest re-statement steps can be selected for re-statement, so that the resistance states of the n-1 input memristors are the resistance states corresponding to the n-1 logic values ​​of the current stage logic operation.

[0103] Furthermore, when m>n+1, after the previous level logic operation is completed, the output memristor in the previous level logic operation can be directly used as the input memristor in the current level logic operation. At the same time, any n-1 input memristors in the previous level logic operation can still be used as input memristors in the current level logic operation. Then, a new memristor is selected as the output memristor, set to a high impedance state, and the current level logic operation is performed.

[0104] Similarly, as Figure 1 The above cascading method is illustrated using a three-input majority gate logic circuit as an example. It includes storing the output of the previous logic operation in a memristor M in an resistive state. (0,3) In this process, the result of the previous logical calculation is directly used as the input for the next logical operation, that is, the memristor M that stores the calculation result in the previous step... (0,3)The memristor M can be directly regarded as the input memristor for the next logic calculation. (0,0) / M (0,1) / M (0,2) ; and so on, to achieve cascading of multiple logic gates.

[0105] The relevant technical solutions are the same as in Embodiment 1, and will not be repeated here.

[0106] Example 4

[0107] A non-volatile majority gate logic parallel operation circuit, characterized in that it includes a plurality of non-volatile majority gate logic circuits provided in Embodiment 1 of the present invention;

[0108] like Figure 5 As shown, the positive terminals of memristors at the same location in each non-volatile majority gate logic circuit are connected to each other, so as to implement multiple majority gate logic operations in parallel within the same logic calculation pulse cycle.

[0109] In this embodiment, multiple non-volatile majority gate logic circuits share a single controller, enabling simultaneous computation of multiple majority gate logic circuits within the same logic computation pulse cycle in the 1T1R array. By writing different input logic variable information into the memristors of different rows (WL) in the corresponding BL terminals, the output memristors are initialized to a high-impedance state. A fixed voltage V0 is then connected to the positive terminal (BL terminal) of the output memristors and the second terminal (SL terminal) of the resistor. Applying a positive gate voltage to activate the WL of the logic operation completes the parallel operation of large-scale majority gate logic.

[0110] Specifically, taking the three-input majority gate logic circuit with n=3 as an example, we only need to write the input logic variables of different majority gates into the same row of memristors in the corresponding BL terminals. Taking the parallel calculation of two majority gate logics M(a1,b1,c1)=a1·b1+a1·c1+b1·c1 and M(a2,b2,c2)=a2·b2+a2·c2+b2·c2 as an example, the first step is to write the input variables a1, b1, and c1 into the memristor M respectively. (0,0) M (0,1) M (0,2) In the process, input variables a2, b2, and c2 are written into memristor M respectively. (1,0) M (1,1) M (1,2) In the middle, the output memristor M (0,3) and M (1,3)Initialize to a high-impedance state "0"; Second step: Connect ports BL0, BL1, and BL2 to gnd, connect BL3 and SL0 to a fixed level V0, apply a positive gate voltage to WL0 and WL1 to activate the selected WL, and ground the remaining unselected WL. The operating voltage of each terminal is dynamically applied to complete the logic operation. The operation results M(a1,b1,c1) and M(a2,b2,c2) are stored in memristors M in the form of resistors. (0,3) and M (1,3) middle.

[0111] The relevant technical solutions are the same as in Embodiment 1, and will not be repeated here.

[0112] Example 5

[0113] A computer-readable storage medium includes a stored computer program, wherein, when the computer program is executed by a processor, it controls the device where the storage medium is located to execute the control method in the non-volatile majority gate logic circuit provided in Embodiment 2 of the present invention and / or the majority gate logic cascading method provided in Embodiment 3 of the present invention.

[0114] The relevant technical solutions are the same as those in Embodiments 2 and 3, and will not be repeated here.

[0115] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A non-volatile majority gate logic circuit based on memristors, characterized in that, A majority gate logic operation is used to implement n logic inputs, including: a controller, m identical memristors, and resistors; m ≥ n+1; The positive terminals of m memristors are connected to the controller, and the negative terminals are all connected to the source line SL. After being led out through the source line SL, they are connected to the first end of the resistor, and the second end of the resistor is connected to the controller. When the controller is working, it selects one memristor from m memristors as the output memristor and n memristors as the input memristors; it sets the output memristor to a high impedance state; it sets the n input memristors to the impedance states corresponding to the n logic inputs; it grounds the positive terminals of the n input memristors and applies a voltage V0 to the positive terminal of the output memristor and the second terminal of the resistor. At this time, the impedance state of the output memristor is the result of the majority gate logic operation. Where n is an odd number greater than 1; the voltage V0 satisfies: and R is the resistance value of the resistor; R H R is the high-resistance resistance value of the memristor. L V is the low-resistance resistance value of the memristor; set V is the threshold value at which the memristor transitions from a high-resistance state to a low-resistance state. reset The threshold value at which the memristor transitions from a low-resistance state to a high-resistance state is given.

2. The non-volatile majority gate logic circuit according to claim 1, characterized in that, It also includes: m transistors; the gates of the m transistors are connected to the same word line WL, the drains are connected to the negative terminals of the m memristors one by one, and the sources are connected to the source line SL; At this time, the negative terminal of the memristor is connected to the source line SL via the corresponding transistor; The controller is also used to control the on / off state of each transistor. When performing majority gate logic operations, all n+1 transistors connected to the output memristor and the input memristor are turned on.

3. The non-volatile majority gate logic circuit according to claim 1 or 2, characterized in that, The resistance value of the resistor is on the same order of magnitude as the low-resistance resistance value of the memristor.

4. The non-volatile majority gate logic circuit according to claim 3, characterized in that, 5. The non-volatile majority gate logic circuit according to claim 4, characterized in that, When n = 3, the voltage V0 satisfies: and 6. The non-volatile majority gate logic circuit according to claim 1, characterized in that, The memristor includes a high-resistance state and a low-resistance state; the high-resistance state corresponds to the logic value "0", and the low-resistance state corresponds to the logic value "1".

7. The control method for the non-volatile majority gate logic circuit according to any one of claims 1-6, used to implement majority gate logic operations with n logic inputs, characterized in that, include: S1. Select one memristor from m memristors as the output memristor, and n memristors as the input memristors; Set the output memristor to a high impedance state; Set each of the n input memristors to the corresponding resistance state of the n logic inputs; S2. Ground the positive terminals of the n input memristors, and apply a voltage V0 to the positive terminal of the output memristor and the second terminal of the resistor. At this time, the resistance state of the output memristor is the result of the majority gate logic operation. Where n is an odd number greater than 1; the voltage V0 satisfies: and R is the resistance value of the resistor; R H R is the high-resistance resistance value of the memristor. L V is the low-resistance resistance value of the memristor; set V is the threshold value at which the memristor transitions from a high-resistance state to a low-resistance state. reset The threshold value at which the memristor transitions from a low-resistance state to a high-resistance state is given.

8. A method for cascading majority gate logic circuits based on any one of claims 1-6, characterized in that, include: After the previous level logic operation is completed, the output memristor in the previous level logic operation is directly used as the input memristor in the current level logic operation to perform the current level logic operation.

9. A non-volatile multi-gate logic parallel operation circuit, characterized in that, Includes multiple non-volatile majority gate logic circuits as described in any one of claims 1-6; The positive terminals of memristors at the same location in each non-volatile majority gate logic circuit are connected to each other, so that multiple majority gate logic operations can be implemented in parallel within the same logic calculation pulse cycle.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored computer program, wherein, when the computer program is executed by a processor, it controls the device in which the storage medium resides to perform the control method in the non-volatile majority gate logic circuit of claim 7 and / or the majority gate logic cascading method of claim 8.

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