Transmitter and correction method

Abstract

A transmitter and a calibration method are disclosed. The transmitter includes an RF modulator, a filter circuit, a control circuit, and a first DC compensation circuit. During a first calibration period, the control circuit controls the filter circuit to be connected to the RF modulator in a first phase sequence, causing the RF modulator to generate a first RF signal. During a second calibration period, the control circuit controls the filter circuit to be connected to the RF modulator in a second phase sequence, causing the RF modulator to generate a second RF signal, wherein the second phase sequence has a phase opposite to the first phase sequence. The control circuit is further configured to calculate and control the first DC compensation circuit to compensate for a first DC offset of the filter circuit based on the first and second RF signals.

Description

Technical Field

[0001] This disclosure relates to a transmitter. In particular, it relates to a transmitter and a correction method for compensating for DC offset. Background Technology

[0002] In modern wireless communication technology, determining the DC offset of a transmitter is a crucial issue. Furthermore, with the evolution of wireless communication, the DC offset generated by each stage of the transmitter circuitry can cause greater noise in the RF output signal. Therefore, determining the DC offset generated by each stage of the transmitter circuitry is a significant issue in this field. Summary of the Invention

[0003] This disclosure provides a transmitter. The transmitter includes an RF modulator, a filter circuit, a control circuit, and a first DC compensation circuit. The filter circuit is connected to the RF modulator in a phase sequence, causing the RF modulator to generate an RF signal according to the phase sequence. The control circuit is configured to control the filter circuit to be connected to the RF modulator in the first phase sequence during a first correction period, causing the RF modulator to generate a first RF signal. During a second correction period, the filter circuit is controlled to be connected to the RF modulator in a second phase sequence, causing the RF modulator to generate a second RF signal, wherein the second phase sequence has a phase opposite to the first phase sequence. The control circuit is further configured to calculate and control the first DC compensation circuit to compensate for a first DC offset of the filter circuit based on the first RF signal and the second RF signal.

[0004] This disclosure provides a calibration method. The calibration method includes the following steps: During a first calibration period, a control circuit controls a filter circuit to connect to an RF modulator in a first phase sequence, causing the RF modulator to generate a first RF signal. During a second calibration period, the control circuit controls the filter circuit to connect to the RF modulator in a second phase sequence, causing the RF modulator to generate a second RF signal, wherein the second phase sequence has a phase opposite to the first phase sequence. The control circuit calculates and controls a first DC compensation circuit to compensate for a first DC offset of the filter circuit based on the first RF signal and the second RF signal.

[0005] In summary, this disclosure utilizes a switching filter circuit connected to the phase sequence of the radio frequency modulator to generate a first radio frequency signal before phase swapping and a second radio frequency signal after phase swapping. The control circuit calculates the first DC offset of the filter circuit based on the first and second radio frequency signals, thereby compensating for the first DC offset of the filter circuit. Attached Figure Description

[0006] To make the above and other objects, features, advantages and embodiments of this disclosure more apparent and understandable, the accompanying drawings are described below:

[0007] Figure 1This is a schematic diagram of a transmitter according to an embodiment of the present disclosure in standard mode and during a first calibration period.

[0008] Figure 2 This is a schematic diagram of an RF modulator according to an embodiment of the present disclosure in standard mode and during a first correction period.

[0009] Figure 3A This is a flowchart of a correction method according to an embodiment of the present disclosure.

[0010] Figure 3B This is an embodiment of the present disclosure. Figure 3A The flowchart of step S230 in the correction method 200.

[0011] Figure 4 This is a schematic diagram of a transmitter during a second calibration period according to an embodiment of the present disclosure.

[0012] Figure 5 This is a schematic diagram of an RF modulator during the second correction period according to an embodiment of the present disclosure.

[0013] Symbol Explanation

[0014] To make the above and other objects, features, advantages and embodiments of this disclosure more apparent and understandable, the appended symbols are explained as follows:

[0015] 100: Transmitter

[0016] 110: Digital-to-analog conversion circuit

[0017] 120: Filtering circuit

[0018] 122, 124: Filters

[0019] 130: Switching circuit

[0020] 140: Radio Frequency Modulator

[0021] 142, 144: Mixer

[0022] 150: Local Oscillator

[0023] 160: Amplifier Circuit

[0024] 170: Antenna

[0025] 180: Control circuit

[0026] 182: First DC compensation circuit

[0027] 184: Second DC compensation circuit

[0028] 200: Calibration Method

[0029] DSP: Digital Signal Processor

[0030] DACa, DACb: Digital-to-Analog Converters

[0031] I: In-phase digital signal

[0032] Q: Orthogonal digital signals

[0033] BIP, BIN, BQP, BQN: Analog signals

[0034] RF11, RF12, RF1, RF1': First radio frequency signal

[0035] RF21, RF22, RF2, RF2': Second radio frequency signals

[0036] IDACA,IDACB,IDACB_IP,IDACB_IN,IDACB_QP,IDACB_QN: compensation current

[0037] VDD: System voltage terminal

[0038] Z1, Z2: Components

[0039] M1~M12: Transistors

[0040] LO_IP: Positive in-phase local oscillation signal

[0041] LO_IN: Negative In-Phase Local Oscillation Signal

[0042] LO_QP: Positive orthogonal local oscillation signal

[0043] LO_QN: Negative-pole orthogonal local oscillation signal

[0044] IF_IP: Positive in-phase intermediate frequency signal

[0045] IF_IN: Negative in-phase intermediate frequency signal

[0046] IF_QP: Positive quadrature intermediate frequency signal

[0047] IF_QN: Negative quadrature intermediate frequency signal

[0048] S210, S220, S230, S232, S234, S236, S240: Steps Detailed Implementation

[0049] The following detailed description, with reference to the accompanying drawings, illustrates the embodiments of this disclosure to provide a better understanding of its implementation. However, the provided embodiments are not intended to limit the scope of this disclosure, and the description of structural operations is not intended to limit the order of their execution. Any device with equivalent technical effects resulting from the recombination of elements falls within the scope of this disclosure. Furthermore, in accordance with industry standards and common practice, the accompanying drawings are for illustrative purposes only and are not drawn to their original dimensions. In reality, the dimensions of various features may be arbitrarily increased or decreased for ease of explanation. In the following description, the same elements will be labeled with the same symbols for ease of understanding.

[0050] The indexes 1 to n in the component and signal numbers used in this disclosure and accompanying drawings are for convenience of referring to individual components and signals, and are not intended to limit the number of the aforementioned components and signals to a specific number. In this disclosure and accompanying drawings, if a component or signal number is used without specifying its index, it means that the component or signal number refers to any unspecified component or signal within the group of components or signals to which it belongs.

[0051] Furthermore, the terms "comprising," "including," "having," "containing," etc., used in this document are all open-ended terms, meaning "including but not limited to." Additionally, the term "and / or" as used in this document includes any one or more of the related listed items and all combinations thereof.

[0052] In this document, when an element is referred to as a “connection” or “coupled,” it may mean an “electrical connection” or “electrical coupling.” “Connection” or “coupled” can also be used to indicate the operation or interaction between two or more elements. Furthermore, although terms such as “first,” “second,” etc., are used in this document to describe different elements, these terms are only used to distinguish elements or operations described using the same technical terminology.

[0053] Please see Figure 1 , Figure 1 This is a schematic diagram of a transmitter 100 according to an embodiment of the present disclosure in standard mode and during a first calibration. Figure 1 As shown, the transmitter 100 includes a digital signal processor (DSP), a digital-to-analog converter (DAC) circuit 110, a filter circuit 120, a switching circuit 130, an RF modulator 140, an amplifier circuit 160, an antenna 170, a control circuit 180, a first DC compensation circuit 182, and a second DC compensation circuit 184.

[0054] The digital signal processor (DSP) generates in-phase digital signals I and quadrature digital signals Q to the digital-to-analog converters (DACa and DACb) in the digital-to-analog converter circuit 110. The DACa and DACb in the digital-to-analog converter circuit 110 convert the in-phase digital signal I and the quadrature digital signal Q into analog signals BIP, BIN, BQP, and BQN, respectively, and transmit them to filters 122 and 124 in the filter circuit 120.

[0055] Filter 122 generates a positive in-phase intermediate frequency (IF) signal IF_IP based on the analog signal BIP converted from the in-phase digital signal I, and outputs the positive in-phase IF signal IF_IP from the positive in-phase path of filter 122. Furthermore, filter 122 generates a negative in-phase IF signal IF_IN based on the analog signal BIN converted from the in-phase digital signal I in negative phase, and outputs the negative in-phase IF signal IF_IN from the positive quadrature path of filter 122.

[0056] Filter 124 generates a positive quadrature intermediate frequency (IF) signal IF_QP based on the analog signal BQP converted from the quadrature digital signal Q, and outputs the positive quadrature IF signal IF_QP from the positive quadrature path of filter 122. Furthermore, filter 122 generates a negative quadrature IF signal IF_QN based on the analog signal BQN converted from the quadrature digital signal Q in negative phase, and outputs the negative quadrature IF signal IF_QN from the negative quadrature path of filter 122.

[0057] The switching circuit 130 is electrically coupled between the filter circuit 120 and the RF modulator 140. The switching circuit 130 is used to switch the circuit path from the filter circuit 120 to the RF modulator 140, so that the filter circuit 120 is connected to the RF modulator 140 with different phase sequences.

[0058] For example, in Figure 1 In the illustrated embodiment, during the standard mode and the first correction period, the switching circuit 130 connects the positive in-phase path of the filter circuit 120 to the first input terminal of the RF modulator 140 and connects the negative in-phase path of the filter circuit 120 to the second input terminal of the RF modulator 140, so that the mixer 142 uses the in-phase local oscillation signal provided by the local oscillator 150 to mix the positive in-phase intermediate frequency signal IF_IP and the negative in-phase intermediate frequency signal IF_IN.

[0059] Furthermore, the switching circuit 130 connects the positive quadrature path of the filter circuit 120 to the third input terminal of the RF modulator 140, and connects the negative quadrature path of the filter circuit 120 to the fourth input terminal of the RF modulator 140, so that the mixer 144 uses the quadrature local oscillation signal provided by the local oscillator 150 to mix the positive quadrature intermediate frequency signal IF_QP and the negative quadrature intermediate frequency signal IF_QN.

[0060] Therefore, in standard mode and during the first calibration period, the RF modulator 140 receives the positive in-phase intermediate frequency signal IF_IP, the negative in-phase intermediate frequency signal IF_IN, the positive quadrature intermediate frequency signal IF_QP, and the negative quadrature intermediate frequency signal IF_QN according to the first phase sequence of "positive, negative, positive, negative" to generate the first RF signals RF11 and RF12. The first RF signals RF11 and RF12 are superimposed to generate the first RF signal RF1. The first RF signal RF1 is amplified by the amplifier circuit 160 to generate the first RF signal RF1'. The control circuit 180 reads the first RF signal RF1' from the amplifier circuit 160.

[0061] In some embodiments, the control circuit 180 includes a detection circuit (not shown) to detect the first radio frequency signal RF1' using the self-amplifying circuit 160. The control circuit 180 determines a first DC offset of the filter circuit 120 and a second DC offset of the radio frequency modulator 140 based on the outputs (e.g., the first radio frequency signal RF1') generated by the radio frequency modulator 140 under different input phase sequences. How the first DC offset of the filter circuit 120 and the second DC offset of the radio frequency modulator 140 are determined so that the first DC compensation circuit 182 and the second DC compensation circuit 184 generate compensation currents IDACA and IDACB respectively will be described in detail in subsequent embodiments.

[0062] Please see Figure 2 , Figure 2 This is a schematic diagram of an RF modulator 140 according to an embodiment of the present disclosure in standard mode and during a first correction period. Figure 2 As shown, the RF modulator 140 includes elements Z1 and Z2, and mixers 142 and 144. Element Z1 is electrically coupled between the system voltage terminal VDD and the output terminal of the first RF signal RF11. Element Z2 is electrically coupled between the system voltage terminal VDD and the output terminal of the first RF signal RF12. In some embodiments, elements Z1 and Z2 may be implemented by impedances (e.g., resistors or inductors).

[0063] The intermediate frequency input stage of mixer 142 consists of transistors M9 and M10. The radio frequency output stage of mixer 142 consists of transistors M1 to M4. Transistors M1 to M4 are used to receive the positive in-phase local oscillation signal LO_IP, the negative in-phase local oscillation signal LO_IN, the negative in-phase local oscillation signal LO_IN, and the positive in-phase local oscillation signal LO_IP provided by local oscillator 150, respectively.

[0064] Similarly, the intermediate frequency (IF) input stage of mixer 144 consists of transistors M11 and M12. Transistors M11 and M12 are used to receive the positive in-phase IF signal IF_IP and the negative in-phase IF signal IF_IN, respectively. The radio frequency (RF) output stage of mixer 144 consists of transistors M5 to M8. Transistors M5 to M8 are used to receive the positive quadrature local oscillation signals LO_QP, LO_QN, LO_QN, and LO_QP provided by local oscillator 150, respectively.

[0065] For a better understanding, please refer to the following: Figures 1-5 . Figure 3A This is a flowchart of a correction method 200 according to an embodiment of the present disclosure. Figure 3B This is an embodiment of the present disclosure. Figure 3A The flowchart of step S230 in the correction method 200. Figure 4 This is a schematic diagram of a transmitter 100 during a second calibration period according to an embodiment of the present disclosure. Figure 5 This is a schematic diagram of an RF modulator 140 during a second correction period according to an embodiment of this disclosure. Figure 3A As shown, the correction method S200 includes steps S210, S220, S230 and S240.

[0066] In step S210, during the first calibration period, the control circuit controls the filter circuit to connect to the RF modulator in a first phase sequence, causing the RF modulator to generate a first RF signal. Specifically, during the first calibration period, the control circuit 180 controls the switching circuit 130 to connect the positive quadrature path, negative quadrature path, positive in-phase path, and negative in-phase path of the filter circuit 120 sequentially to the first input terminal, second input terminal, third input terminal, and fourth input terminal of the RF modulator 140, so that the filter circuit 120 is connected to the RF modulator 140 in a "positive, negative, positive, negative" phase sequence, such as... Figure 1 As shown.

[0067] During the first correction period, transistor M9 receives the positive in-phase intermediate frequency signal IF_IP, and transistor M10 receives the negative in-phase intermediate frequency signal IF_IN. Transistor M11 receives the positive quadrature intermediate frequency signal IF_QP, and transistor M10 receives the negative quadrature intermediate frequency signal IF_QN. At this time, the first radio frequency signal RF1 generated by superimposing the first radio frequency signals RF11 and RF12 will contain the value of the superposition of the first DC offset of the filter circuit 120 and the second DC offset of the radio frequency modulator 140, such as... Figure 2 As shown. Accordingly, during the first calibration period, the first radio frequency signal RF'1 measured by the control circuit 180 and the amplifier circuit 160 will also contain a first value that is the superposition of the first DC offset of the filter circuit 120 and the second DC offset of the radio frequency modulator 140.

[0068] In step S220, during the second correction period, the control circuit controls the filter circuit to connect to the RF modulator in a second phase sequence, causing the RF modulator to generate a second RF signal. Specifically, during the second correction period, the control circuit 180 controls the switching circuit 130 to connect the positive quadrature path, negative quadrature path, positive in-phase path, and negative in-phase path of the filter circuit 120 sequentially to the second input terminal, first input terminal, fourth input terminal, and third input terminal of the RF modulator 140, so that the filter circuit 120 is connected to the RF modulator 140 in a second phase sequence of "negative, positive, negative, positive". Figure 4 As shown.

[0069] During the second correction period, transistor M9 receives the negative in-phase intermediate frequency (IF) signal IF_IN, and transistor M10 receives the positive in-phase IF signal IF_IP. Transistor M11 receives the negative quadrature IF signal IF_QN, and transistor M10 receives the positive quadrature IF signal IF_QP, as shown below. Figure 5 As shown.

[0070] At this time, the phase of the second phase sequence "negative, positive, negative, positive" is opposite to the phase of the first phase sequence "positive, negative, positive, negative". In other words, since the phases of the positive in-phase intermediate frequency signal IF_IP and the negative in-phase intermediate frequency signal IF_IN are interchanged, and the phases of the positive quadrature intermediate frequency signal IF_QP and the negative quadrature intermediate frequency signal IF_QN are interchanged, the second radio frequency signal RF2 generated by superimposing the second radio frequency signals RF21 and RF22 will contain the superposition of the negative value of the first DC offset of the filter circuit 120 and the value of the second DC offset of the radio frequency modulator 140. That is, the second radio frequency signal RF2 will contain the value of the second DC offset of the radio frequency modulator 140 minus the value of the first DC offset of the filter circuit 120. Correspondingly, during the second correction period, the second radio frequency signal RF2' measured by the detection circuit (not shown) and the amplification circuit 160 in the control circuit 180 will also contain the second value of the first DC offset of the filter circuit 120 minus the value of the first DC offset of the filter circuit 120.

[0071] In step S230, the control circuit calculates the first DC offset of the filter circuit and the second DC offset of the RF modulator based on the first RF signal and the second RF signal. Step S230 also includes steps S232, S234, and S236, as follows: Figure 3B As shown.

[0072] In step S232, the control circuit calculates a first value, which is the superposition of a first DC offset of the filter circuit and a second DC offset of the RF modulator, based on the first RF signal. In some embodiments, the first value, which includes the first DC offset plus the second DC offset, can be derived from the first RF signal RF1 by subtracting the gain of the amplifier circuit 160 from the first RF signal RF1 via the filter circuit 120 and the RF modulator 140.

[0073] In step S234, the control circuit calculates a second value based on the second radio frequency signal, which is the second DC offset of the radio frequency modulator minus the first DC offset of the filter circuit. In some embodiments, the second value of the second radio frequency signal RF2, which includes a negative first DC offset plus a second DC offset, can be derived from the second radio frequency signal RF2' by subtracting the gain of the amplifier circuit 160 and passing through the filter circuit 120 and the radio frequency modulator 140.

[0074] In step S236, the control circuit calculates the first DC offset and the second DC offset based on the first value and the second value. Specifically, the simultaneous equations for the first DC offset of the filter circuit 120 and the second DC offset of the RF modulator 140 can be derived from steps S232 and S234. For example, if the first DC offset of the filter circuit 120 is represented by "A", the second DC offset of the RF modulator 140 is represented by "B", the "first value" is represented by "C", and the "second value" is represented by "D", the following formula can be derived.

[0075] A + B = C

[0076] -A+B=D

[0077] Therefore, the control circuit 180 can solve the first DC offset (A) of the filter circuit 120 and the second DC offset (B) of the radio frequency modulator 140 by solving the above simultaneous equations.

[0078] Thus, step S240 can continue, where the control circuit controls the first DC compensation circuit to compensate for the first DC offset of the filter circuit, and controls the second DC compensation circuit to compensate for the second DC offset of the RF modulator.

[0079] In some embodiments, the control circuit 180 can control the first DC compensation circuit 182 to generate at least one compensation current IDACA based on the first DC offset, and superimpose it with one or more of the positive in-phase intermediate frequency signal IF_IP, the negative in-phase intermediate frequency signal IF_IN, the positive quadrature intermediate frequency signal IF_QP, and the negative quadrature intermediate frequency signal IF_QN, so as to eliminate the first DC offset of the filter circuit 120, thereby compensating for the first DC offset of the filter circuit 120.

[0080] Similarly, control circuit 180 can control second DC compensation circuit 184 to generate at least one compensation current IDACB (e.g., based on the second DC offset) according to the second DC offset. Figure 2 The compensation currents IDACB_IP, IDACB_IN, IDACB_QP, and IDACB_Qn shown are superimposed on the first terminals (e.g., the drain terminals) of transistors M9 to M12 respectively, so as to eliminate the second DC offset of the RF modulator 140, thereby compensating for the second DC offset of the RF modulator 140.

[0081] In summary, this disclosure utilizes the phase sequence switching between the filter circuit 120 and the RF modulator 140 to generate a first RF signal RF1 before phase swapping and a second RF signal RF2 after phase swapping. Based on the first RF signal RF1 and the second RF signal RF2, a system of simultaneous equations is constructed to determine the first DC offset of the filter circuit 120 and the second DC offset of the RF modulator 140. The solution to this system of equations represents the values ​​of the first DC offset of the filter circuit 120 and the second DC offset of the RF modulator 140. Furthermore, based on the solution to the system of equations, DC offset compensation operations are performed on the first DC offset of the filter circuit 120 and the second DC offset of the RF modulator 140. Moreover, this disclosure utilizes the switching of the connection paths (phase sequence) between different stages of the transmitter 100 and detects the signal at the output of the transmitter 100 to determine the DC offset generated by different stages of the circuit, thereby significantly simplifying the detection method or circuit architecture.

[0082] Although this disclosure has been described above with reference to embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make various changes and modifications without departing from the concept and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the claims.

Claims

1. A transmitter comprising: A radio frequency modulator; A filter circuit is connected to the radio frequency modulator in a phase sequence, so that the radio frequency modulator generates a radio frequency signal according to the phase sequence. A control circuit, used to: During a first correction period, the filter circuit is controlled to be connected to the RF modulator in a first phase sequence, causing the RF modulator to generate a first RF signal; and During a second correction period, the filter circuit is controlled to be connected to the RF modulator in a second phase sequence, causing the RF modulator to generate a second RF signal, wherein the second phase sequence has a phase opposite to the first phase sequence; and A first DC compensation circuit, wherein the control circuit is further configured to calculate and control the first DC compensation circuit to compensate for a first DC offset of the filter circuit based on the first radio frequency signal and the second radio frequency signal.

2. The transmitter as claimed in claim 1, wherein: The control circuit calculates a first value based on the first radio frequency signal, which is the superposition of the first DC offset of the filter circuit and a second DC offset of the radio frequency modulator; and The control circuit calculates a second value based on the second radio frequency signal, which is the second DC offset of the radio frequency modulator minus the first DC offset of the filter circuit.

3. The transmitter as claimed in claim 2, wherein the control circuit calculates the first DC offset and the second DC offset based on the first value and the second value.

4. The transmitter as claimed in claim 1, further comprising: A second DC compensation circuit, wherein the control circuit is further configured to calculate and control the second DC compensation circuit to compensate for a second DC offset of the radio frequency modulator based on the first radio frequency signal and the second radio frequency signal.

5. The transmitter as claimed in claim 1, further comprising: A switching circuit is electrically coupled between the RF modulator and the filter circuit, wherein the control circuit controls the switching circuit to: During the first calibration period, the switching circuit is controlled to connect the filter circuit and the RF modulator in the first phase sequence, causing the RF modulator to generate the first RF signal; and During the second correction period, the switching circuit is controlled to connect the filter circuit and the RF modulator in the second phase sequence, so that the RF modulator generates the second RF signal.

6. The transmitter of claim 5, wherein the filter circuit has a positive quadrature path, a negative quadrature path, a positive in-phase path, and a negative in-phase path, and the RF modulator has a first input terminal, a second input terminal, a third input terminal, and a fourth input terminal, wherein the control circuit controls the switching circuit to: During the first calibration period, the positive quadrature path, the negative quadrature path, the positive in-phase path, and the negative in-phase path of the filter circuit are sequentially connected to the first input terminal, the second input terminal, the third input terminal, and the fourth input terminal of the RF modulator; and During the second correction period, the positive quadrature path, the negative quadrature path, the positive in-phase path, and the negative in-phase path of the filter circuit are sequentially connected to the second input terminal, the first input terminal, the fourth input terminal, and the third input terminal of the RF modulator, so that the RF modulator generates the second RF signal.

7. The transmitter of claim 1, further comprising: A digital-to-analog converter circuit is used to generate a positive in-phase analog signal, a negative in-phase analog signal, a positive quadrature analog signal, and a negative quadrature analog signal to the filter circuit.

8. The transmitter of claim 7, further comprising: A digital signal processor is used to generate a co-phase digital signal and a quadrature digital signal to the digital-to-analog converter circuit.

9. The transmitter of claim 1, further comprising: A local oscillator is used to provide quadrature local oscillation signals and in-phase local oscillation signals to the radio frequency modulator.

10. A calibration method, comprising: During a first correction period, a control circuit controls a filter circuit to connect to an RF modulator in a first phase sequence, causing the RF modulator to generate a first RF signal. During a second correction period, the control circuit controls the filter circuit to connect to the RF modulator in a second phase sequence, causing the RF modulator to generate a second RF signal, wherein the second phase sequence has a phase opposite to the first phase sequence; and The control circuit calculates and controls a first DC compensation circuit to compensate for a first DC offset of the filter circuit based on the first radio frequency signal and the second radio frequency signal.

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