Antenna device and beam control method

Abstract

An antenna apparatus includes an antenna array, a beamforming circuit, and a processor. The beamforming circuit is connected to the antenna array, wherein the beamforming circuit is configured to control the antenna array to perform beamforming, wherein the beamforming circuit includes a temporary storage circuit, wherein the temporary storage circuit includes a first-in-first-out storage area that stores a plurality of beam indices. The processor is connected to the beamforming circuit, wherein the processor is configured to control the beamforming circuit via a first processing interface to sequentially read the plurality of beam indices by a first-in-first-out method, and to set a direction of a beam of the antenna array according to the read beam indices, wherein the read beam indices correspond to the direction of the beam of the antenna array. Furthermore, a beam control method is also disclosed.

Description

Technical Field

[0001] This invention relates to 5G new radio (5G NR) technology, and more particularly to an antenna device and a beam control method. Background Technology

[0002] In 5G new radio (5G NR) millimeter-wave (mmWave) antenna arrays, beamforming is often used to transmit various signals. However, whenever the antenna array needs to change its beam direction, the processor often needs to transmit a large amount of beam-related data to the beamforming chip to set the beam direction. Furthermore, in existing technologies, the beam table is often stored in the beamforming chip via a Serial Peripheral Interface (SPI), and the SPI is used to set the switching control of the beams corresponding to the beam table via a General-Purpose Input / Output (GPIO). This requires transmitting the complete beam index to the beamforming chip via the SPI and controlling the beam switching via the GPIO. Therefore, this process of setting the beam direction of the antenna array often takes a significant amount of time. In view of this, how to greatly reduce the time required to set the direction of the antenna array beam is a problem that those skilled in the art urgently want to solve. Summary of the Invention

[0003] This disclosure presents an antenna device including an antenna array, a beamforming circuit, and a processor. The beamforming circuit is connected to the antenna array and is used to control the antenna array for beamforming. The beamforming circuit includes a temporary storage circuit, which includes a first-in-first-out (FIFO) temporary storage area that stores multiple beam indices. The processor is connected to the beamforming circuit and is used to control the beamforming circuit via a first processing interface to sequentially read the multiple beam indices using a FIFO method and set the direction of the antenna array's beam according to the read beam indices, wherein the read beam indices correspond to the direction of the antenna array's beam.

[0004] Another aspect of this disclosure discloses a beam control method, comprising: controlling an antenna array to perform beamforming via a beamforming circuit, wherein the beamforming circuit includes a temporary storage circuit, wherein the temporary storage circuit includes a first-in-first-out (FIFO) temporary storage area, the FIFO temporary storage area storing a plurality of beam indices; controlling the beamforming circuit via a first processing interface to sequentially read the plurality of beam indices using a FIFO method; and setting the direction of the antenna array beam according to the read beam indices during a beam switching time, wherein the beam switching time is less than or equal to the loop start time during the loop start time. Attached Figure Description

[0005] Figure 1 This is a schematic diagram of the antenna device disclosed herein.

[0006] Figure 2A This is a schematic diagram of an antenna device in the initialization phase according to some embodiments of this disclosure.

[0007] Figure 2B This is a schematic diagram of an antenna device in the beamforming stage according to some embodiments of the present disclosure.

[0008] Figure 3 This is a flowchart of the beam control method disclosed herein.

[0009] Figure 4 This is a schematic diagram of beam switching time in prior art.

[0010] Figure 5 This is a schematic diagram of the direction switching of the beam in the prior art.

[0011] Figure 6 This is a schematic diagram of beam switching time according to some embodiments of the present disclosure.

[0012] Figure 7 This is a schematic diagram of an antenna device according to some embodiments of the present disclosure, showing the switching of beam direction.

[0013] The reference numerals in the attached figures are explained as follows: 100, 200, ANT: Antenna devices 110: Processor 111: Initialization Module 112: Scheduling Module 120: Beamforming circuit 121: Temporary storage circuit 122: Beam Selection Module 123: Beam Application Module 130: Antenna Array IF1: First processing interface IF2: Second processing interface BT: Beammeter SPI: Serial Peripheral Interface GPIO: General Purpose Input / Output Interface FIFOR: First-In-First-Out temporary storage area TS(1)~TS(N): Switching signals S210~S230: Steps SSB: Synchronization Signal Cluster SL: Time Slot SMB: symbol CP: Cyclic prefix time A~D: Beam BST: Beam Switching Time UE1~UE4: User Equipment Detailed Implementation

[0014] Reference Figure 1 , Figure 1 This is a schematic diagram of the antenna device 100 disclosed herein. In this embodiment, the antenna device 100 includes a processor 110, a beamforming circuit 120, and an antenna array 130. The processor 110 is connected to the beamforming circuit 120, and the beamforming circuit 120 is connected to the antenna array 130.

[0015] In some embodiments, the processor 110 may be implemented by a processing circuit, a central processing unit, or a computing unit. In some embodiments, the beamforming circuit 120 may be implemented by a commonly used analog beamforming integrated circuit (IC). In some embodiments, the antenna array 130 may include a plurality of antenna elements, wherein the antenna elements may be any type of antenna (e.g., patch antenna or inverted-F antenna, etc.).

[0016] In some embodiments, the processor 110 may control the beamforming circuit 120 via a first processing interface IF1 and a second processing interface IF2. In some embodiments, the first processing interface IF1 may be a general-purpose input / output (GPIO) interface, and the second processing interface IF2 may be a serial peripheral interface (SPI).

[0017] In this embodiment, the beamforming circuit 120 is used to control the antenna array 130 to perform beamforming. Furthermore, the beamforming circuit includes a temporary storage circuit 121.

[0018] In some embodiments, the temporary storage circuit 121 may be a temporary storage memory (Register). In some embodiments, during the initial phase (i.e., system initialization), the processor 110 may store the beam table BT in the temporary storage circuit 121 via the second processing interface IF2. In some embodiments, the beam table BT may include beam parameters of a plurality of candidate beam directions and candidate beam indices corresponding to these candidate beam directions.

[0019] In some embodiments, the beam parameters of the candidate beam direction can be phase control bit strings and amplitude control bit strings (e.g., each consisting of three bit strings) of each antenna element corresponding to the candidate beam direction pointed to by one or more beams, which are determined in advance by simulation. The phase control bit strings of each antenna element can be used to control the phase of each antenna element to adjust the beam direction of the antenna array 130, and the amplitude control bit strings of each antenna element can be used to control the amplitude of each antenna element to adjust the beam width of the antenna array 130.

[0020] In this embodiment, the temporary storage circuit 121 includes a First-in-First-out Region (FIFOR) that stores multiple beam indices. In other words, during the initialization phase, these beam indices are pre-stored into this FIFOR in sequence.

[0021] Furthermore, the processor 110 controls the beamforming circuit 120 via the first processing interface IF1 to sequentially read multiple beam indices using a first-in-first-out method (i.e., the data stored earlier needs to be read first), and sets the beam direction of the antenna array 130 according to the read beam indices, wherein the read beam indices correspond to the beam direction of the antenna array 130.

[0022] In some embodiments, the processor 110 can control the beamforming circuit 120 via the first processing interface IF1 to select beam parameters for the corresponding candidate beam direction from the beam table BT according to the read beam index. In other words, it searches the beam table BT for candidate beam indices with the same beam parameters and selects the beam parameters for the candidate beam direction corresponding to the candidate beam index. Then, the processor 110 can set the beam direction of the antenna array 130 according to the beam parameters of the corresponding candidate beam direction. The following explanation uses practical examples of the first-in-first-out (FIFOR) buffer shown in Table 1 and the beam table BT shown in Table 2.

[0023] Table 1

[0024] Table 2

[0025] As shown in Table 1, the processor 110 controls the beamforming circuit 120 via the first processing interface IF1 to sequentially read these beam indices 0-3 using a first-in-first-out method. Next, as shown in Table 2, the processor 110 selects the beam parameters of the corresponding candidate beam direction from the aforementioned beam table BT based on the read beam index. The beam parameters of the corresponding candidate beam direction may include a set of phase control bit strings and a set of amplitude control bit strings (e.g., a first phase control byte and a first amplitude control byte). In this way, the beamforming circuit 120 can set the direction of the beams (A-D) of the antenna array 130 according to the beam parameters of the corresponding beams (A-D). For example, when the beamforming circuit 120 reads a beam index of 0, the beamforming circuit 120 can adjust the phase of each antenna element in the antenna array 130 according to the first phase control byte to perform phase control, and can adjust the amplitude of each antenna element in the antenna array 130 according to the first amplitude control byte to perform gain control, thereby setting the direction of beam A of the antenna array 130 to -16 degrees. In other words, the processor 110 switches from beam A to beam D sequentially according to beam indices 0 to 3 through the first processing interface IF1.

[0026] It is worth noting that when the first processing interface IF1 is a general purpose input / output interface, the processor 110 only needs to send a switching signal with a small amount of data (e.g., three general purpose input / output clock signals) to the beamforming circuit 120. The beamforming circuit 120 will then sequentially read multiple beam indices from the first-in-first-out (FIFO) buffer and set the direction of the beams (A~D) of the antenna array 130 according to the read beam indices. In this way, the time required to switch the direction of the beams (A~D) of the antenna array 130 will be significantly reduced.

[0027] Refer to together Figure 2A as well as Figure 2B ,in Figure 2A This is a schematic diagram of an antenna device 200 during the initialization phase according to some embodiments of this disclosure, and Figure 2B This is a schematic diagram of an antenna device 200 in the beamforming stage according to some embodiments of this disclosure. Figure 2A as well as Figure 2BAs shown, the antenna device 200 includes a processor 110, a beamforming circuit 120, and an antenna array 130. The processor 110 is connected to the beamforming circuit 120, and the beamforming circuit 120 is connected to the antenna array 130. The beamforming circuit 120 includes a first-in-first-out (FIFO) buffer.

[0028] Furthermore, the processor 110 controls the beamforming circuit 120 to enable the antenna array 130 to perform beamforming via the Serial Peripheral Interface (SPI) and the General Purpose Input / Output Interface (GPIO). The Serial Peripheral Interface (SPI) includes multiple SPI transmission pins, and the General Purpose Input / Output Interface (GPIO) includes multiple GPIO pins.

[0029] In some embodiments, the processor 110 includes an initialization module 111, wherein, as Figure 2A As shown, during the initialization phase, the initialization module 111 stores the beam table BT in the temporary storage circuit 121 via the serial peripheral interface SPI, and sets the switching control of the general input / output interface GPIO on the beam corresponding to the beam table BT in the temporary storage circuit 121 via the general input / output interface GPIO.

[0030] In some embodiments, the beamforming circuit 120 may further include a beam selection module 122 and a beam application module 123. In some embodiments, the processor 110 may further include a scheduling module 112. In some embodiments, such as Figure 2B As shown, during the beamforming stage, the scheduling module 112 can switch the beam generated by the antenna array 130 by simply switching the beam index stored in the first-in-first-out (FIFOR) buffer via the general-purpose input / output interface (GPIO). In some embodiments, during the beamforming stage, the scheduling module 112 can sequentially transmit switching signals TS(1) to TS(N) to the FIFOR buffer via the GPIO buffer, where N is any positive integer. In some embodiments, during the beamforming stage, whenever the scheduling module 112 transmits one of the switching signals TS(1) to TS(N) to the FIFOR buffer via the GPIO buffer, the FIFOR buffer becomes readable, allowing the beam selection module 122 to read a beam index from the FIFOR buffer using the FIFOR method. After reading is completed, the FIFOR buffer can also be switched to an unreadable state based on certain security mechanisms.

[0031] In detail, when the scheduling module 112 transmits the first switching signal TS(1) to the first-in-first-out (FIFO) buffer via the general purpose input / output interface (GPIO), the FIFO buffer becomes readable, allowing the beam selection module 122 to read the earliest stored beam index in the FIFO buffer. Similarly, in response to subsequent sequentially transmitted switching signals TS(2) to TS(N), the beam selection module 122 sequentially reads the other beam indices in the FIFO buffer using the first-in-first-out method.

[0032] In some embodiments, during the beamforming stage, the beam selection module 122 can select the beam parameters of the corresponding candidate beam direction from the beam table BT according to the read beam index, and transmit the beam parameters of the candidate beam direction to the beam application module 123. Then, the beam application module 123 controls the antenna array 130 to perform beamforming according to the beam parameters of the corresponding candidate beam direction.

[0033] It is worth noting that the initialization module 111 and scheduling module 112 mentioned above can be set in the processor 110 in the form of hardware circuits, or they can be stored in the processor 110 in the form of software programs in temporary registers (not shown), or they can be stored in external storage devices (not shown) for the processor 110 to read and execute software programs.

[0034] Refer to together Figure 3 , Figure 3 This is a flowchart of the beam control method disclosed herein. Figure 1 The antenna device 100 shown can be used to perform Figure 3 All steps in the beam control method.

[0035] First, in step S210, the antenna array 130 is controlled by the beamforming circuit 120 to perform beamforming.

[0036] Furthermore, in step S220, the beamforming circuit 120 is controlled via the first processing interface IF1 to sequentially read multiple beam indices using a first-in-first-out method.

[0037] In step S230, the direction of the antenna array 130 beam is set according to the read beam index during the beam switching time, wherein the beam switching time is less than or equal to the loop start time during the loop start time.

[0038] Furthermore, by utilizing the antenna device and beam control method of the present invention, the beam switching time (i.e., the time required to switch the direction of the beam of the antenna array 130) can be set to be less than or equal to the Cyclic Prefix (CP) time. This allows the beam switching time to be set within the CP time, which is located between multiple symbols (SMBs) in the time slot (SL) of the Synchronization Signal Burst (SSB). Consequently, during the beam switching time, the first processing interface IF1 can sequentially switch between the directions of multiple beams corresponding to these beam indices according to multiple beam indices, solving the problem of current techniques that require setting the beam switching time within a time slot for the aforementioned beam switching.

[0039] The following practical examples further illustrate the prior art and the relationship between the beam switching time and the cycle prefix time mentioned above. See also... Figure 4 , Figure 4 This is a schematic diagram of beam switching time (BST) in prior art. For example... Figure 4 As shown, taking the two time slots SL of the synchronization signal cluster SSB as an example, each time slot SL has 14 symbol SMBs. Assuming the subcarrier spacing (SCS) is 120kHz, the time of time slot SL is 125 microseconds, and the time of symbol SMB is 8.93 milliseconds.

[0040] In prior art, since the aforementioned First-In-First-Out (FIFOR) buffer does not exist, the beam index corresponding to a specific beam is transmitted to the beamforming circuit via the sequence peripheral interface. A switching signal is then transmitted to the beamforming circuit via a general-purpose input / output interface, enabling the beamforming circuit to select beam parameters for the candidate beam direction corresponding to this beam index from a pre-stored beam table. In this way, the beamforming circuit can control the antenna array to perform beamforming based on these beam parameters.

[0041] Therefore, beam switching consumes time for the peripheral interface to transmit the beam index corresponding to a specific beam and for the general input / output interface to transmit the switching signal. Assuming one clock cycle is 0.05 microseconds, the peripheral interface needs 72 clock cycles to transmit the beam index corresponding to a specific beam, and the general input / output interface needs 3 clock cycles to transmit the switching signal. In this case, the beam switching time (BST) is 3.75 microseconds.

[0042] Furthermore, assuming the cycle prefix time (CP) is 0.57 microseconds, a relatively long beam switching time (BST) is required at this time, which cannot be incorporated into the cycle prefix time (CP). Therefore, the beamforming circuit 120 can only switch to beam A in the 4th symbol time (i.e., incorporate the beam switching time BST in the 4th symbol time) to transmit or receive data using beam A in the 5th to 12th symbols of the SMB, and switch to beam B in the 16th symbol time (i.e., incorporate the beam switching time BST in the 16th symbol time) to transmit or receive data using beam B in the 17th to 24th symbols of the SMB. In other words, in the prior art, the beamforming circuit 120 can only incorporate the beam switching time BST in the symbol SMB when beam switching is required. This results in only two beams being switched sequentially in the two time slots (SL).

[0043] Refer to together Figure 5 , Figure 5 This is a schematic diagram of the direction switching of the beam in previous technology. For example... Figure 5 As shown, with Figure 4 By inserting the beam switching time BST into the symbol SMB, the prior art antenna device ANT could only generate beams A to B sequentially in two time slots SL to communicate with user equipment UE1 to UE2 respectively.

[0044] Refer to together Figure 6 , Figure 6 This is a schematic diagram of the beam switching time (BST) according to some embodiments of this disclosure. Figure 6 As shown, taking the two time slots SL of the synchronization signal cluster SSB as an example, each time slot SL has 14 symbol SMBs. Assuming the subcarrier spacing is 120kHz, the time of time slot SL is 125 microseconds, and the time of symbol SMB is 8.93 milliseconds.

[0045] In this embodiment, the processor 110 transmits a switching signal to the first-in-first-out (FIFOR) buffer via a general-purpose input / output (GPIO) interface, enabling the beam selection module 122 to read the earliest stored beam index in the FIFOR buffer. This allows the beam selection module 122 to select the beam parameters of the candidate beam direction corresponding to this beam index from the beam table BT. Similarly, in response to subsequent switching signals, the beam selection module 122 sequentially reads other beam indices in the FIFOR buffer using a first-in-first-out method.

[0046] In this way, the beam selection module 122 can select the beam parameters of the candidate beam direction corresponding to the read beam index from the beam table BT, and can transmit the beam parameters to the beam application module 123 to control the antenna array 130 to perform beamforming according to the beam parameters.

[0047] Therefore, beam switching only consumes the time required for the GPIO interface to transmit the switching signal. Assuming one clock cycle is 0.05 microseconds, and the GPIO interface requires 3 clock cycles to transmit the switching signal, the beam switching time BST is 0.15 microseconds.

[0048] Furthermore, assuming the cycle prefix time (CP) is 0.57 microseconds, since only a short beam switching time (BST) (i.e., 0.15 seconds) is required, the beamforming circuit 120 can switch to beam A in the 5th cycle prefix time (CP) to transmit or receive data in the 5th to 8th symbols (SMB), and switch to beam B in the 9th cycle prefix time (CP) to transmit or receive data in the 9th to 12th symbols (SMB). Similarly, the same method can be used to switch from beam B to beam C, and finally from beam C to beam D.

[0049] In other words, by means of the above method, the beamforming circuit 120 can insert a beam switching time BST into the cyclic prefix time CP when beam switching is required. Thus, also within the two time slots SL, the antenna device 100 disclosed herein can sequentially switch from beam A to beam D. Conversely, in the above... Figure 4 In previous technologies, only two beams could be switched sequentially in two time slots (SL).

[0050] Refer to together Figure 7 , Figure 7 This is a schematic diagram of an antenna device 100 switching the direction of a beam according to some embodiments of this disclosure. Figure 7 As shown, with Figure 6 By inserting the beam switching time BST into the cyclic prefix time CP, the antenna device 100 can sequentially generate beams A to D to communicate with user devices UE1 to UE4 respectively. Each time a new beam is generated, only 3 general purpose input / output clock cycles are required, which will greatly reduce the time required to set the beam direction of the antenna array 130.

[0051] In summary, this disclosure allows for the establishment of a first-in-first-out (FIFO) buffer in the beamforming circuit to pre-store all beam indices for the directions of the beams to be generated by the antenna array. This enables rapid switching of the antenna array beams using only a general-purpose input / output interface. Furthermore, the beams of the antenna array can be switched during the beam switching time within the loop header time, significantly reducing the time required to set the direction of the antenna array beams.

[0052] While specific embodiments of the present disclosure have been disclosed in relation to the above embodiments, these embodiments are not intended to limit the present disclosure. Various alternatives and modifications can be made by those skilled in the art without departing from the principles and spirit of the present disclosure. Therefore, the scope of protection of the present disclosure is determined by the appended claims.

Claims

1. An antenna device, comprising: A linear array; A beamforming circuit connected to the antenna array, wherein the beamforming circuit controls the antenna array to perform beamforming, wherein the beamforming circuit includes a temporary storage circuit, wherein the temporary storage circuit includes a first-in-first-out (FIFO) temporary storage area storing multiple beam indices; and A processor is connected to the beamforming circuit, wherein the processor controls the beamforming circuit via a first processing interface to sequentially read the beam indices using a first-in-first-out method and set the direction of the antenna array beam according to the read beam indices, wherein the read beam indices correspond to the direction of the antenna array beam. The processor is further configured to set the direction of the antenna array beam according to the read beam index during a beam switching time, wherein the beam switching time is less than or equal to a cycle start time and is set during the cycle start time. The first processing interface is a general-purpose input / output interface.

2. The antenna device of claim 1, wherein the temporary storage circuit stores a beam table, the beam table including beam parameters of a plurality of candidate beam directions.

3. The antenna device of claim 2, wherein the processor is further configured to: The beamforming circuit is controlled via the first processing interface to select beam parameters for the corresponding candidate beam direction from the beam table based on the read beam index; and The direction of the antenna array's beam is set according to the beam parameters of the corresponding candidate beam direction.

4. The antenna device of claim 2, wherein the processor is further configured to: In an initial phase, the beam table is stored in the temporary storage circuit via a second processing interface.

5. The antenna device of claim 4, wherein the second processing interface is a sequence peripheral interface.

6. The antenna device of claim 5, wherein the beamforming circuit includes a beam selection module and a beam application module, wherein the processor is further configured to: The beam selection module is controlled via the general-purpose input / output interface to read the beam indices in the first-in-first-out (FIFO) buffer using a FIFO method, and then transmits the read beam indices to the beam application module; and The beam application module controls the antenna array to perform beamforming based on the read beam index.

7. A beam control method, comprising: A beamforming circuit controls an antenna array to perform beamforming, wherein the beamforming circuit includes a temporary storage circuit, wherein the temporary storage circuit includes a first-in-first-out temporary storage area, the first-in-first-out temporary storage area storing multiple beam indices. The beamforming circuit is controlled via a first processing interface to sequentially read the beam indices using a first-in-first-out method; and The direction of the antenna array beam is set according to the read beam index during a beam switching time, wherein the beam switching time is less than or equal to a cycle start time and is set in the cycle start time. The first processing interface is a general-purpose input / output interface.

8. The beam control method of claim 7, wherein the temporary storage circuit stores a beam table, the beam table including beam parameters of a plurality of candidate beam directions.

9. The beam control method as described in claim 8, further comprising: The beamforming circuit is controlled via the first processing interface to select beam parameters for the corresponding candidate beam direction from the beam table based on the read beam index. as well as The direction of the antenna array's beam is set according to the beam parameters of the corresponding candidate beam direction.

10. The beam control method as described in claim 8, further comprising: In an initial phase, the beam table is stored in the temporary storage circuit via a second processing interface.

11. The beam control method of claim 10, wherein the second processing interface is a sequence peripheral interface.

12. The beam control method of claim 11, wherein the beamforming circuit includes a beam selection module and a beam application module, and the beam control method further includes: The beam selection module is controlled by the general input / output interface to read the beam indices in the first-in-first-out temporary storage area using the first-in-first-out method, and then transmits the read beam indices to the beam application module. as well as The beam application module controls the antenna array to perform beamforming based on the read beam index.

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