Method of fabricating semiconductor structure with unilateral capacitor

Abstract

A method of fabricating a semiconductor structure is provided. The method includes providing a substrate, sequentially forming a first nitride layer, a first sacrificial layer, a second nitride layer, a second sacrificial layer, and a third nitride layer on the substrate, forming a first opening and a second opening, wherein the first opening exposes a first landing pad in the substrate and the second opening exposes a second landing pad in the substrate, forming a first electrode in the first opening and a second electrode in the second opening, simultaneously removing the first sacrificial layer and the second sacrificial layer, and forming a conductive layer conformal to the first electrode, the second electrode, the first nitride layer, the second nitride layer, and the third nitride layer.

Description

Technical Field

[0001] This application claims priority and benefits to U.S. formal applications No. 17 / 748,201 and 17 / 748,869, filed May 19, 2022, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a method for fabricating a semiconductor structure having a single-sided capacitor. More particularly, it relates to a method for fabricating a semiconductor structure having a single-sided capacitor. Background Technology

[0003] Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor components are typically manufactured by sequentially depositing multiple isolation or dielectric layers, multiple conductive layers, and multiple semiconductor material layers on a semiconductor substrate, and then using photolithography to pattern these material layers to form multiple circuit components and elements. As the semiconductor industry has advanced to more advanced technology process nodes in pursuit of better device density, higher performance, and lower costs, challenges have emerged regarding simpler capacitor structures and better memory cell performance.

[0004] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One embodiment of this disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a first landing pad included therein, and a first capacitor disposed on the substrate. The first capacitor includes a first electrode disposed on the first landing pad and extending vertically away from the first landing pad; a first dielectric layer at least partially surrounding the first electrode, wherein the first electrode is shorter than the first dielectric layer; and a second electrode surrounding the first dielectric layer and the first electrode.

[0006] In some embodiments, the semiconductor structure further includes a first nitride layer disposed on the first electrode and the first dielectric layer.

[0007] In some embodiments, the first nitride layer protrudes toward the first electrode.

[0008] In some embodiments, the second electrode surrounds the first nitride layer.

[0009] In some embodiments, the semiconductor structure further includes a second nitride layer surrounding a middle portion of the first capacitor.

[0010] In some embodiments, the second nitride layer contacts the first dielectric layer.

[0011] In some embodiments, the second nitride layer is surrounded by the second electrode.

[0012] In some embodiments, the first dielectric layer comprises one or more materials with high dielectric constants.

[0013] In some embodiments, the first electrode and the second electrode comprise the same metallic material.

[0014] In some embodiments, the first capacitor covers the entire exposed surface of the first landing pad.

[0015] In some embodiments, the semiconductor structure further includes a second capacitor disposed on the substrate adjacent to the first capacitor, and includes: a third electrode disposed on a second landing pad in the substrate adjacent to the first landing pad and extending vertically away from the second landing pad; a second dielectric layer at least partially surrounding the third electrode, wherein the third electrode is shorter than the second dielectric layer; and a fourth electrode surrounding the second dielectric layer and the third electrode, wherein the fourth electrode is substantially connected to the second electrode.

[0016] Another embodiment of this disclosure provides a semiconductor structure. The semiconductor structure includes a first landing pad and a second landing pad disposed on a substrate; a first conductive layer disposed on the first landing pad and extending vertically away from the first landing pad; a second conductive layer disposed on the second landing pad and extending vertically away from the second landing pad; a first dielectric layer surrounding the first conductive layer; a second dielectric layer surrounding the second conductive layer; a third conductive layer surrounding the first dielectric layer and the second dielectric layer; and a first gap disposed between the first dielectric layer and the second dielectric layer, and at least partially surrounded by the third conductive layer.

[0017] In some embodiments, the semiconductor structure further includes a first nitride layer disposed between each intermediate portion of the first dielectric layer and the second dielectric layer; and a second nitride layer disposed between each upper portion of the first dielectric layer and the second dielectric layer.

[0018] In some embodiments, the first gap is disposed between the first nitride layer and the substrate.

[0019] In some embodiments, the semiconductor structure further includes a second gap disposed on the first gap and between the second nitride layer and the first nitride layer, and at least partially surrounded by the third conductive layer.

[0020] In some embodiments, the first conductive layer is shorter than the first dielectric layer, and a portion of the second nitride layer is surrounded by the first dielectric layer on the first conductive layer.

[0021] In some embodiments, the second conductive layer is shorter than the second dielectric layer, and a portion of the second nitride layer is surrounded by the second dielectric layer on the second conductive layer.

[0022] In some embodiments, the first nitride layer contacts the first dielectric layer and the second dielectric layer, and the second nitride layer contacts the first dielectric layer and the second dielectric layer.

[0023] Another embodiment of this disclosure provides a method for fabricating a semiconductor structure. The method includes providing a substrate; sequentially forming a first nitride layer, a first sacrificial layer, a second nitride layer, a second sacrificial layer, and a third nitride layer on the substrate; forming a first opening and a second opening, wherein the first opening exposes a first landing pad in the substrate, and the second opening exposes a second landing pad in the substrate; forming a first electrode in the first opening and forming a second electrode in the second opening; simultaneously removing the first sacrificial layer and the second sacrificial layer; and forming a conductive layer conformally to the first electrode, the second electrode, the first nitride layer, the second nitride layer, and the third nitride layer.

[0024] In some embodiments, the preparation method further includes removing a portion of the second nitride layer after the second nitride layer is formed, thereby exposing the first sacrificial layer.

[0025] In some embodiments, a portion of the second sacrificial layer contacts the first sacrificial layer.

[0026] In some embodiments, the preparation method further includes removing a portion of the third nitride layer after the third nitride layer is formed, thereby exposing the second sacrificial layer.

[0027] In some embodiments, a wet etching operation is performed to remove both the first sacrificial layer and the second sacrificial layer simultaneously.

[0028] In some embodiments, the first sacrificial layer comprises borosilicate glass (BPSG).

[0029] In some embodiments, the second sacrificial layer comprises silane oxide.

[0030] In some embodiments, the fabrication method further includes forming a high dielectric constant layer before forming the first electrode and the second electrode, thereby lining the sidewalls of the first opening and the second opening.

[0031] In some embodiments, the preparation method further includes removing an upper portion of the first electrode in the first opening and an upper portion of the second electrode in the second opening.

[0032] In some embodiments, the preparation method further includes forming a fourth nitride layer before removing the first sacrificial layer and the second sacrificial layer, thereby filling the first opening on the first electrode and the second opening on the second electrode.

[0033] In some embodiments, the fourth nitride layer is disposed on the third nitride layer.

[0034] In some embodiments, the conductive layer surrounds the fourth nitride layer.

[0035] In some embodiments, after the first sacrificial layer and the second sacrificial layer are removed, a first gap is formed between the first electrode and the second electrode and between the second nitride layer and the third nitride layer.

[0036] In some embodiments, from a cross-sectional view, the conductive layer surrounds the first gap.

[0037] In some embodiments, after the first sacrificial layer and the second sacrificial layer are removed, a second gap is formed between the first electrode and the second electrode and between the first nitride layer and the second nitride layer.

[0038] In some embodiments, the conductive layer at least partially surrounds the second gap.

[0039] In some embodiments, the first opening exposes the entire upper surface of the first landing pad, and the second opening exposes the entire upper surface of the second landing pad.

[0040] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0041] A more complete understanding of this disclosure can be obtained by referring to the detailed description and claims. This disclosure should also be understood to be associated with element numbers in the drawings, which represent similar elements throughout the description.

[0042] Figure 1 This is a cross-sectional schematic diagram illustrating the semiconductor structure of some embodiments of the present disclosure.

[0043] Figure 2 This is a flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments of this disclosure.

[0044] Figures 3 to 7 This is a cross-sectional schematic diagram illustrating several intermediate stages in the formation of a semiconductor structure according to some embodiments of the present disclosure.

[0045] Figure 8 This is a top-view schematic diagram illustrating some embodiments of this disclosure, such as... Figure 7 The intermediate structure shown.

[0046] Figures 9 to 17 This is a cross-sectional schematic diagram illustrating several intermediate stages in the formation of a semiconductor structure according to some embodiments of the present disclosure.

[0047] Figure 18 This is a top-view schematic diagram illustrating some embodiments of this disclosure, such as... Figure 17 The intermediate structure shown.

[0048] Figures 19 to 21 This is a cross-sectional schematic diagram illustrating several intermediate stages in the formation of a semiconductor structure according to some embodiments of the present disclosure.

[0049] Figure 22 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 18 The semiconductor structure shown is defined by the cross-section B-B'.

[0050] Figure 23 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 18 The semiconductor structure shown is defined by the cross-section C-C'.

[0051] Figure 24 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 18 The semiconductor structure shown is defined by the cross-section D-D'.

[0052] The reference numerals in the attached figures are explained as follows:

[0053] 10: Base

[0054] 30: Capacitor

[0055] 30a: First capacitor

[0056] 30b: Second capacitor

[0057] 31a: upper part

[0058] 31b: Upper part

[0059] 32a: Middle part

[0060] 32b: Middle section

[0061] 33a: Lower part

[0062] 33b: Lower part

[0063] 41: First gap

[0064] 42: Second gap

[0065] 102: Landing mat

[0066] 102a: Landing mat

[0067] 102b: Landing pad

[0068] 103: Conductive island

[0069] 104: Isolation layer

[0070] 105: Dielectric layer

[0071] 106: Dielectric layer

[0072] 107: Unit Area

[0073] 108: Surrounding Area

[0074] 201: Nitride layer

[0075] 202: First Sacrifice Layer

[0076] 203: Nitride layer

[0077] 204: Opening

[0078] 205: Second Sacrificial Layer

[0079] 206: Nitride layer

[0080] 207: Nitride layer

[0081] 208: Opening

[0082] 301: Opening

[0083] 301a: First opening

[0084] 301b: Second opening

[0085] 302: Dielectric layer

[0086] 302a: First dielectric layer

[0087] 302b: Second dielectric layer

[0088] 303: Conductive layer

[0089] 303a: First lower electrode

[0090] 303b: Second lower electrode

[0091] 303R: upper part

[0092] 304: Upper electrode

[0093] H1: Height

[0094] H2: Height

[0095] H3: Height

[0096] H4: Height

[0097] S1: Preparation method

[0098] S11: Steps

[0099] S12: Steps

[0100] S13: Steps

[0101] S14: Steps

[0102] S15: Steps

[0103] S16: Steps

[0104] S102: Upper surface

[0105] S102a: Upper surface

[0106] S102b: Upper surface

[0107] S104: Upper surface Detailed Implementation

[0108] The embodiments or examples of this disclosure shown in the accompanying drawings will now be described using specific language. It should be understood that the scope of this disclosure is not intended to be limited thereto. Any modifications or improvements to the described embodiments, and any further applications of the principles described herein, will be considered commonplace by those skilled in the art. Component numbers may be repeated throughout the embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they share the same component numbers.

[0109] It should be understood that while the terms “first,” “second,” “third,” etc., may be used in this text to describe different elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish an element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, the terms “first element,” “component,” “region,” “layer,” or “section” discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of this text.

[0110] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0111] Figure 1 This is a cross-sectional schematic diagram illustrating a semiconductor structure according to some embodiments of the present disclosure. The semiconductor structure has a substrate 10 and a capacitor 30 disposed on the substrate 10. In some embodiments, the substrate 10 includes a plurality of active elements, a plurality of passive elements, and / or a plurality of conductive elements. The active elements may include a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a logic die (e.g., a system-on-a-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a microprocessor, etc.), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), or other active elements. The passive elements may include a capacitor, a resistor, an inductor, a fuse, or other passive elements. These conductive elements may include multiple metal wires, multiple metal islands, multiple conductive vias, multiple contact points, or other conductive elements.

[0112] The active elements, passive elements, and / or conductive elements described above may be formed in and / or on a semiconductor substrate. The semiconductor substrate may be a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The semiconductor substrate may include an elemental semiconductor material having silicon or germanium in a single-crystal, polycrystalline, or amorphous form; a compound semiconductor material having at least one of the following: silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material having at least one of the following: SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a gradient Si:Ge characteristic, wherein the Si to Ge composition changes from one ratio at one location of the gradient SiGe characteristic to another ratio at another location. In other embodiments, the SiGe alloy is formed on a silicon substrate. In some embodiments, a SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy.

[0113] The term "substrate" can be a general term, and substrate 10 may include all layers, elements, and assemblies disposed beneath capacitor 30. For ease of illustration and simplification, only the upper part of substrate 10 is depicted in the figure.

[0114] In some embodiments, the substrate 10 includes a unit region 107 and a surrounding region 108. In some embodiments, the active elements are primarily disposed in the unit region 107. In some embodiments, the surrounding region 108 surrounds the unit region 107. In some embodiments, the substrate 10 has one or more landing pads 102 and an insulating layer 104 that separates the landing pads 102 in the unit region 107. In some embodiments, the landing pads 102 are electrically insulated from each other by the insulating layer 104. In some embodiments, the substrate 10 includes a conductive island 103 located in the surrounding region 108, the height of which is the same as the height of the bonding pads 102 and the insulating layer 104. In some embodiments, the substrate 10 includes a plurality of dielectric layers (e.g., 105 and 106) disposed on the conductive island 103 in the surrounding region 108. In some embodiments, the dielectric layers 105 and 106 are located at a height higher than the landing pads 102.

[0115] In some embodiments, capacitor 30 refers to a single capacitor. In some embodiments, capacitor 30 may be a collective term for all capacitors disposed on the substrate 10 at the same height. In some embodiments, capacitor 30 includes a first capacitor 30a and a second capacitor 30b. The first capacitor 30a and the second capacitor 30b may share a common electrode. In some embodiments, the first capacitor 30a and the second capacitor 30b are structurally similar to each other or are mirror images of each other.

[0116] The first capacitor 30a may include a first lower electrode 303a, a first dielectric layer 302a, and an upper electrode 304. In some embodiments, the first lower electrode 303a serves as an upper electrode, and the electrode 304 serves as a lower electrode of the first capacitor 30a. In some embodiments, the first capacitor 30a is disposed in one of the landing pads 102 and extends vertically away from the one of the landing pads 102. For ease of explanation, the landing pad 102 covered by the first lower electrode 303a... Figure 1 The first dielectric layer 302a is designated as 102a. In some embodiments, the first dielectric layer 302a at least partially surrounds the first lower electrode 303a, wherein the first lower electrode 303a is shorter than the first dielectric layer 302a. In some embodiments, the first dielectric layer 302a may comprise silicon oxide (SiO2). x ), silicon nitride (Si x N y The first dielectric layer 302a may comprise a dielectric material, such as a high dielectric constant dielectric material. In some embodiments, the high dielectric constant dielectric material has a dielectric constant greater than 3.9. The high dielectric constant dielectric material may comprise silicates of one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), ZrO2, HfO2, Al2O3, Y2O3, and La2O3, or aluminates of one or more of ZrO2, HfO2, Al2O3, Y2O3, and La2O3, other applicable materials, or combinations thereof. Other suitable materials are within the scope of this disclosure.

[0117] The second capacitor 30b may include a second lower electrode 303b, a second dielectric layer 302b, and an upper electrode 304. In some embodiments, the second lower electrode 303b serves as an upper electrode, and the upper electrode 304 serves as a lower electrode of the second capacitor 30b. In other words, the first capacitor 30a and the second capacitor 30b share the upper electrode 304. In some embodiments, the upper electrode 304 serves as the lower electrode of both the first capacitor 30a and the second capacitor 30b. In some embodiments, the second capacitor 30b is disposed on one of the landing pads 102 adjacent to the landing pad 102a and extends vertically away from the landing pad 102 adjacent to the landing pad 102a. For ease of explanation, the landing pad 102 covered by the second lower electrode 303b... Figure 1 The first dielectric layer 302a is designated as 102b. In some embodiments, the second dielectric layer 302b at least partially surrounds the second lower electrode 303b, wherein the second lower electrode 303b is shorter than the second dielectric layer 302b. In some embodiments, a material of the second dielectric layer 302b is the same as the material of the first dielectric layer 302a.

[0118] The semiconductor structure may further include a nitride layer 207 disposed on the first lower electrode 303a and the first dielectric layer 302a. In some embodiments, the nitride layer 207 protrudes toward the first lower electrode 303a. In some embodiments, the nitride layer 207 is at least partially surrounded by the first dielectric layer 302a. The nitride layer 207 may also be disposed on the second lower electrode 303b and the second dielectric layer 302b. In some embodiments, the nitride layer 207 protrudes toward the second lower electrode 303b. In some embodiments, the nitride layer 207 is at least partially surrounded by the second dielectric layer 302b. In some embodiments, the nitride layer 207 is surrounded by the upper electrode 304.

[0119] The semiconductor structure may further include a nitride layer 203 surrounding an intermediate portion 32a of a first dielectric layer 302a and an intermediate portion 32b of a second dielectric layer 302b. In some embodiments, the nitride layer 203 contacts the first dielectric layer 302a. In some embodiments, the nitride layer 203 contacts the second dielectric layer 302b. In some embodiments, the intermediate portions 32a and 32b are located at the same height. In some embodiments, the nitride layer 203 is surrounded by an upper electrode 304. In some embodiments, a first gap 41 is defined between a lower portion 33a of the first dielectric layer 302a and a lower portion 33b of the second dielectric layer 302b. In some embodiments, the first gap 41 is disposed between the nitride layer 203 and the substrate 10. In some embodiments, the first gap 41 is surrounded by the upper electrode 304. In some embodiments, a second gap 42 is defined between an upper portion 31a of the first dielectric layer 302a and an upper portion 31b of the second dielectric layer 302b. In some embodiments, the second gap 42 is on the nitride layer 203. In some embodiments, the second gap 42 is partially surrounded by the upper electrode 304.

[0120] Figure 2 This is a schematic flowchart illustrating a method S1 for fabricating a semiconductor structure according to some embodiments of the present disclosure. Method S1 includes multiple steps (S11, S12, S13, S14, S15, and S16), and the description and illustration are not intended to limit the order of these steps. In step S11, a substrate is provided. In step S12, a first nitride layer, a first sacrificial layer, a second nitride layer, a second sacrificial layer, and a third nitride layer are sequentially formed on the substrate. In step S13, a first opening and a second opening are formed, wherein the first opening exposes a first landing pad in the substrate, and the second opening exposes a second landing pad in the substrate. In step S14, a first electrode is formed in the first opening, and a second electrode is formed in the second opening. In step S15, the first sacrificial layer and the second sacrificial layer are simultaneously removed. In step S16, a conductive layer is formed, wherein the conductive layer conformally conforms to the first electrode, the second electrode, the first nitride layer, the second nitride layer, and the third nitride layer. It should be understood that these steps of preparation method S1 can be reconfigured or otherwise modified in various aspects. Additional processes may be provided before, during, and after preparation method S1, and only some other processes may be briefly described herein. Therefore, other implementations are possible within the scope of the aspects described herein.

[0121] To further illustrate the concepts of this disclosure, various embodiments are provided below. For clarity and simplicity, element numbers of elements having the same or similar functions are repeated in different embodiments. However, such use is not intended to limit this disclosure to a particular embodiment or a particular element. Furthermore, the conditions or parameters described in different embodiments may be combined or modified to form different combinations of embodiments, as long as the parameters or conditions used do not conflict.

[0122] Please refer to Figure 3 , Figure 3 This is a cross-sectional schematic view at a stage of fabrication method S1 according to some embodiments of the present disclosure. In step S11, a substrate 10 is provided, formed, or accommodated. The substrate 10 may include multilayers, elements, and assemblies fabricated by conventional semiconductor processes. For ease of illustration and simplification, only the upper portion of the substrate 10 is depicted in the drawings. In some embodiments, the substrate 10 includes one or more landing pads 102 and an isolation layer 104 separating the multiple landing pads 102 in a cell region 107. In some embodiments, the upper surfaces S102 of the landing pads 102 and an upper surface S104 of the isolation layer 104 are exposed.

[0123] In some embodiments, the substrate 10 includes a cell region 107 and a surrounding region 108. In some embodiments, the active elements are primarily disposed in the cell region 107. In some embodiments, the surrounding region 108 surrounding the cell region 107 provides a space for electronic wiring between the electronic elements. In some embodiments, the substrate 10 includes a conductive island 103 in the surrounding region 108, located at the same height as the landing pads 102 and the isolation layer 104. In some embodiments, the substrate 10 includes a plurality of dielectric layers (e.g., 105 and 106) disposed on the conductive island 103 in the surrounding region 108. In some embodiments, the dielectric layers 105 and 106 are located at a height higher than the landing pads 102. In some embodiments, the upper surfaces S102 of the landing pads 102 and the upper surface S104 of the isolation layer 104 are exposed at this stage.

[0124] Please refer to Figure 4 , Figure 4 This is a cross-sectional schematic diagram of a stage in preparation method S1 according to some embodiments of the present disclosure. In step S12, a first nitride layer 201 is formed on the substrate 10. In some embodiments, the first nitride layer 201 is conformally formed to the substrate 10. In some embodiments, the first nitride layer 201 comprises silicon nitride (Si). x N yThe first nitride layer 201 comprises silicon nitride (SiON), a low-dielectric-constant dielectric material, combinations thereof, and / or other suitable materials. The low-dielectric-constant dielectric material may have a dielectric constant (k-value) of less than 3.9. In some embodiments, the first nitride layer 201 comprises silicon nitride. In some embodiments, the fabrication technique of the first nitride layer 201 includes a deposition process. In some embodiments, the deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or combinations thereof. In some embodiments, the first nitride layer 201 is formed in a cell region 107 and a surrounding region 108. In some embodiments, the first nitride layer 201 has a stepped profile, wherein a portion of the first nitride layer 201 in the surrounding region 108 is located at a higher height than a portion of the first nitride layer 201 in the cell region 107.

[0125] Please refer to Figure 5 , Figure 5 This is a cross-sectional schematic diagram of a stage in the preparation method S1 according to some embodiments of the present disclosure. In step S12, a first sacrificial layer 202 is formed on the first nitride layer 201. In some embodiments, the first sacrificial layer 202 is formed only in the cell region 107. In some embodiments, the first sacrificial layer 202 is formed in both the cell region 107 and the surrounding region 108, and for simplicity, a portion of the first sacrificial layer 202 in the surrounding region 108 is omitted in the drawing. In some embodiments, the first sacrificial layer 202 at least covers each of the upper surfaces S102 of the landing pads 102. In some embodiments, the first sacrificial layer 202 comprises silicate glass, silicon oxide, silane oxide, or a combination thereof. In some embodiments, the first sacrificial layer 202 comprises borosilicate glass (BPSG). In some embodiments, for selective etching purposes, the first sacrificial layer 202 comprises a dielectric material different from the first nitride layer 201.

[0126] Please refer to Figure 6 , Figure 6This is a cross-sectional schematic diagram of a stage in the preparation method S1 according to some embodiments of the present disclosure. In step S12, a second nitride layer 203 is formed on the first sacrificial layer 202. In some embodiments, the second nitride layer 203 is formed only in the cell region 107. In some embodiments, the second nitride layer 203 is formed in both the cell region 107 and the surrounding region 108, and for simplicity, a portion of the second nitride layer 203 in the surrounding region 108 is omitted in the drawings. Similarly, multiple elements formed in subsequent processes may be formed only in the cell region 107 or in both the cell region 107 and the surrounding region 108, but for simplicity, only portions in the cell region 107 are shown. The configuration of these elements may be adjusted according to different applications. This will not be repeated in the specification. In some embodiments, the material of the second nitride layer 203 is the same as the material of the first nitride layer 201. In some embodiments, the fabrication technique of the second nitride layer 203 includes a deposition process. In some embodiments, the deposition process includes a chemical vapor deposition (CVD), a physical vapor deposition (PVD), an atomic layer deposition (ALD), a low-pressure chemical vapor deposition (LPCVD), a plasma-enhanced CVD (PECVD), or a combination thereof.

[0127] Please refer to Figure 7 , Figure 7 This is a cross-sectional schematic diagram of a stage in the preparation method S1 according to some embodiments of the present disclosure. In step S12, after the second nitride layer 203 is formed, one or more portions of the second nitride layer 203 are removed, thereby exposing at least a portion of the first sacrificial layer 202. In some embodiments, a plurality of openings 204 are formed on the second nitride layer 203 by an etching process. In some embodiments, the etching process includes a wet etching process, a dry etching process, a directional dry etching process, or a combination thereof. In some embodiments, a portion of the first sacrificial layer 202 is also removed by the etching process.

[0128] Please refer to Figure 8 , Figure 8 Based on some embodiments of this disclosure, such as Figure 7 The diagram shows a top view of the second nitride layer 203 at this stage. In some embodiments, Figure 7 It is along Figure 8 A cross-sectional view along section A-A'. Each opening 204 can be configured as follows: Figure 8 The diagram shows a circle. However, this disclosure is not limited thereto. In other embodiments, an opening 204 may be configured as a square, a rectangle, a triangle, a hexagon, or other polygon. In some embodiments, for the purpose of simplifying manufacturing, from... Figure 8As shown in the top view, all openings 204 are circular. In other embodiments, the different openings 204 have different configurations when viewed from the top view. These openings 204 are formed to simultaneously remove the sacrificial layers above and below the second nitride layer 203 (details provided below), therefore the number and configuration of these openings 204 are not limited as long as the sacrificial layers can be connected. Figure 8 The configuration of the openings 204 shown is only one embodiment and is not intended to limit this disclosure.

[0129] Please refer to Figure 9 , Figure 9 This is a cross-sectional schematic diagram of a stage in preparation method S1 according to some embodiments of the present disclosure. In step S12, after the openings 204 are formed, a second sacrificial layer 205 is formed on the second nitride layer 203. In some embodiments, the second sacrificial layer 205 fills the openings 204 and extends through the second nitride layer 203. In some embodiments, the second sacrificial layer 205 contacts the first sacrificial layer 202. In some embodiments, the second sacrificial layer 205 comprises a dielectric material. The first sacrificial layer 202 and the second sacrificial layer 205 may comprise the same or different materials. In some embodiments, the dielectric material of the second sacrificial layer 205 is the same as a dielectric material of the first sacrificial layer 202. In some embodiments, both the first sacrificial layer 202 and the second sacrificial layer 205 comprise oxides. In some embodiments, the second sacrificial layer 205 comprises silane oxide.

[0130] Please refer to Figure 10 , Figure 10 This is a cross-sectional schematic diagram of a stage in the preparation method S1 according to some embodiments of the present disclosure. In step S12, after forming the second sacrificial layer 205, a third nitride layer 206 is formed on the second sacrificial layer 205. In some embodiments, a material of the third nitride layer 206 is the same as the material of the second nitride layer 203. In some embodiments, the third nitride layer 206 comprises silicon nitride. In some embodiments, the fabrication technique of the third nitride layer 206 includes a deposition process. In some embodiments, the deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or a combination thereof.

[0131] Please refer to Figure 11 , Figure 11This is a cross-sectional schematic diagram of a stage in the fabrication method S1 according to some embodiments of the present disclosure. In step S13, a plurality of openings 301 are formed. In some embodiments, each opening 301 extends through the third nitride layer 206, the second sacrificial layer 205, the second nitride layer 203, the first sacrificial layer 202, and the first nitride layer 201. In some embodiments, the fabrication technique of the openings 301 includes one or more etching processes. In some embodiments, the etching processes include selective wet etching, directional dry etching, ion beam etching, reactive ion etching, or a combination thereof. In some embodiments, each opening 301 is exposed to a landing pad 102 in the substrate 10. Figure 11 As an example embodiment, the openings 301 expose two adjacent landing pads 102, and the openings 301 include a first opening 301a and a second opening 301b. In other embodiments, the number of openings 301 may be greater than two, and the landing pads 102 exposed by the openings 301 may not be adjacent. For illustrative purposes, in the following figures, the landing pad exposed via the first opening 301a is designated as 102a, and the landing pad exposed via the second opening 301b is designated as 102b. In some embodiments, the first opening 301a exposes the entire upper surface S102a of the landing pad 102a. In some embodiments, the second opening 301b exposes the entire upper surface S102b of the landing pad 102b.

[0132] Please refer to Figure 12 , Figure 12 This is a cross-sectional schematic diagram at a stage of preparation method S1 according to some embodiments of the present disclosure. After step S13, a plurality of dielectric layers 302 are formed in each opening 301. In some embodiments, the dielectric layers 302 comprise the same material. In some embodiments, the dielectric layers 302 comprise one or more dielectric materials with high dielectric constants. In some embodiments, the dielectric material with high dielectric constants has a dielectric constant (k value) greater than 3.9. The dielectric material with high dielectric constants may comprise silicates of one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), ZrO2, HfO2, Al2O3, Y2O3, and La2O3, or aluminates of one or more of ZrO2, HfO2, Al2O3, Y2O3, and La2O3, other applicable materials, or combinations thereof. Other suitable materials are within the scope of this disclosure.

[0133] In some embodiments, the dielectric layers 302 include a first dielectric layer 302a lining each sidewall of the first opening 301a and a second dielectric layer 302b lining each sidewall of the second opening 301b. In some embodiments, a portion of the upper surface S102a of the landing pad 102a is exposed via the first dielectric layer 302a. In some embodiments, a portion of the upper surface S102b of the landing pad 102b is exposed via the second dielectric layer 302b. In some embodiments, the entire first dielectric layer 302a is disposed within the first opening 301a. In some embodiments, the entire second dielectric layer 302b is disposed within the second opening 301b.

[0134] Please refer to Figure 13 , Figure 13 This is a cross-sectional schematic diagram at a stage of the preparation method S1 according to some embodiments of the present disclosure. After the dielectric layers 302 are formed, a conductive layer 303 is formed in the openings 301. In some embodiments, the conductive layer 303 fills the openings 301 and covers the third nitride layer 206. In some embodiments, the conductive layer 303 contacts the upper surfaces S102a and S102b of the landing pads 102a and 102b. In some embodiments, the conductive layer 303 comprises a metallic material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium-aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), titanium carbide (TaC), tantalum carbonitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), titanium silicon nitride (TiSiN), or other suitable materials. The fabrication techniques for the conductive layer 303 may include low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), electron beam physical vapor deposition (EBPVD), sputtering, electroplating, screen printing, or other suitable methods.

[0135] Please refer to Figure 14 , Figure 14This is a cross-sectional schematic diagram at a stage of the preparation method S1 according to some embodiments of the present disclosure. After the conductive layer 303 is formed, a portion of the conductive layer 303 is removed. In some embodiments, the portion of the conductive layer 303 disposed on the third nitride layer 206 is removed. In some embodiments, the removal of this portion of the conductive layer 303 includes ion beam etching, directional dry etching, reactive ion etching, solution wet etching, chemical mechanical polishing (CMP), or a combination thereof. In some embodiments, after removal, the portions of the conductive layer 303 in the openings 301 remain in place. In some embodiments, the upper surfaces of the portions of the third nitride layer 206, the dielectric layers 302, and the conductive layer 303 held in the openings 301a and 301b are coplanar.

[0136] Please refer to Figure 15 , Figure 15 This is a cross-sectional schematic diagram of a stage in the preparation method S1 according to some embodiments of the present disclosure. In step S14, the portions of the conductive layer 303 held in the openings 301 are partially removed, thereby forming a first electrode 303a and a second electrode 303b in the first opening 301a and the second opening 301b, respectively. In some embodiments, an etch-back process is performed on the held portions of the conductive layer 303. In some embodiments, the upper portion 303R of the held portions of the conductive layer 303 in the openings 303 is removed. Figure 14 (Indicated by dashed lines), the conductive layer 303 remaining in the openings 301 becomes the first electrode 303a in the first opening 301a and the second electrode 303b in the second opening 301b.

[0137] In some embodiments, a first electrode 303a is disposed on and extends vertically away from the landing pad 102a. In some embodiments, a first dielectric layer 302a surrounds the first electrode 303a in the first opening 301a. In some embodiments, the first electrode 303a is completely located beneath the third nitride layer 206. In some embodiments, a height H3 of the first dielectric layer 302a is greater than a height H1 of the first electrode 303a. In some embodiments, a second electrode 303b is disposed on and extends vertically away from the landing pad 102b. In some embodiments, a second dielectric layer 302b surrounds the second electrode 303b in the second opening 301b. In some embodiments, the second electrode 303b is completely located beneath the third nitride layer 206. In some embodiments, a height H4 of the second dielectric layer 302b is greater than a height H2 of the second electrode 303b.

[0138] Please refer to Figure 16 , Figure 16This is a cross-sectional schematic diagram at a stage of the preparation method S1 according to some embodiments of the present disclosure. After forming the first electrode 303a and the second electrode 303b, a fourth nitride layer 207 is formed on the third nitride layer 206. In some embodiments, the fourth nitride layer 207 comprises the same material as the third nitride layer 206. In some embodiments, an interface between the third nitride layer 206 and the fourth nitride layer 207 may not be observed. In some embodiments, the fourth nitride layer 207 fills the openings 301 on the first electrode 303a and the second electrode 303b. In some embodiments, a portion of the fourth nitride layer 207 is disposed on the third nitride layer 206. In some embodiments, a portion of the fourth nitride layer 207 protrudes toward the first electrode 303a, and this portion of the fourth nitride layer 207 is surrounded by a first dielectric layer 302a. In some embodiments, a portion of the fourth nitride layer 207 protrudes toward the second electrode 303b, and this portion of the fourth nitride layer 207 is surrounded by the second dielectric layer 302b. The fourth nitride layer 207 can serve as an electrical insulator between different electrodes of a capacitor (a detailed description of this configuration is provided later). In some embodiments, the fabrication techniques for the fourth nitride layer 207 include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or combinations thereof.

[0139] Please refer to Figure 17 , Figure 17This is a cross-sectional schematic diagram at a stage of the preparation method S1 according to some embodiments of the present disclosure. After the fourth nitride layer 207 is formed, at least a portion of the second sacrificial layer 205 is exposed. In some embodiments, one or more etching processes are performed to form a plurality of openings 208 that pass through a plurality of portions of the third nitride layer 206 and the fourth nitride layer 207 covering the portion of the second sacrificial layer 205. In some embodiments, some openings 208 are formed between such openings 301. In some embodiments, one or more etching processes are performed on the fourth nitride layer 207 and the third nitride layer 206 to expose the second sacrificial layer 205 at such openings 208. In some embodiments, some portions of the third nitride layer 206 and some portions of the fourth nitride layer 207 are removed by different etching processes. In some embodiments, such portions of the third nitride layer 206 and such portions of the fourth nitride layer 207 are removed simultaneously by a single etching process. In some embodiments, the one or more etching processes include a wet etching process, a dry etching process, a directional dry etching process, or a combination thereof. In some embodiments, the portions of the second sacrificial layer 205 at the openings 208 are also removed by one or more etching processes. In some embodiments, from a top view, a configuration and arrangement of the openings 208 may be similar to or different from the configuration and arrangement of the openings 204.

[0140] Please refer to Figure 18 , Figure 18 Based on some embodiments of this disclosure, such as Figure 17 A top view schematic diagram of the fourth nitride layer 207 at the stage shown. In some embodiments, Figure 17 It is along Figure 18 A cross-sectional view along section A-A'. Each opening 208 can be configured as follows: Figure 18 The diagram shows a circle, but this disclosure is not limited thereto. The openings 208 are formed to expose the second sacrificial layer 205 in a wet etching process (details below), therefore the number and arrangement of the openings 208 are not limited as long as the second sacrificial layer 205 can be exposed.

[0141] Please refer to Figure 19 , Figure 19This is a cross-sectional schematic diagram at a stage of the preparation method S1 according to some embodiments of the present disclosure. In step S15, the first sacrificial layer 202 and the second sacrificial layer 205 are removed simultaneously. In some embodiments, a wet etching process is performed to remove the first sacrificial layer 202 and the second sacrificial layer 205 simultaneously. In some embodiments, an etchant of the wet etching process having a low selectivity between the first sacrificial layer 202 and the second sacrificial layer 205 is used to remove the first sacrificial layer 202 and the second sacrificial layer 205 simultaneously. In some embodiments, the etchant of the wet etching process has a high selectivity between the sacrificial layers (205 and 202) and the nitride layers (201, 203, 206 and 207). In some embodiments, the etchant of the wet etching process has a high selectivity between the sacrificial layers (205 and 202) and the dielectric layers (302). In some embodiments, the etchant has a low removal rate on the nitride layers 201, 203, 206, 207 and the dielectric layers 302. In some embodiments, the removal rate of the etchant on the nitride layers 201, 203, 206, 207 and the dielectric layers 302 is very low and negligible. The nitride layers 201, 203, 206, 207 remain attached to the dielectric layers 302 and the electrodes 303a, 303b and provide support thereto.

[0142] The presence of openings 208 through nitride layers 207 and 206 provides a pathway for the reaction of the etchant with the sacrificial layer 205, while the presence of openings 204 through the second nitride layer 203 provides a pathway for the reaction of the etchant with the first sacrificial layer 202. To effectively remove the sacrificial layers 202 and 205 between openings 301a and 301b, at least some openings 208 and some openings 204 are provided between openings 301a and 301b. Theoretically, a greater number of openings 208 and 204 can provide a better removal rate of the sacrificial layers 202 and 205. However, after removing the second sacrificial layer 205, an excessive number of openings 208 can lead to damage or failure of nitride layers 206 and 207. Similarly, after removing the first sacrificial layer 202, an excessive number of openings 204 can lead to damage or failure of the nitride layer 203. Therefore, the number and configuration of openings 208 and 204 can be adjusted and optimized according to different applications, and are not limited herein.

[0143] Please refer to Figure 20 , Figure 20This is a cross-sectional schematic diagram of a stage in the preparation method S1 according to some embodiments of the present disclosure. In step S16, a conductive layer 304 is formed on the substrate 10. In some embodiments, the conductive layer 304 is conformally formed with the first nitride layer 201, the second nitride layer 203, the third nitride layer 206, the fourth nitride layer 207, and the dielectric layers 302. In some embodiments, the conductive layer 304 surrounds the dielectric layer 302a and the first electrode 303a. In some embodiments, the conductive layer 304 surrounds the dielectric layer 302b and the second electrode 303b. A first gap 41 may be defined between the dielectric layers 302a and 302b and disposed below the second nitride layer 203. A second gap 42 may be defined between the dielectric layers 302a and 302b and disposed above the second nitride layer 203. The fabrication techniques for the conductive layer 304 may include low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), electron beam physical vapor deposition (EBPVD), sputtering, electroplating, screen printing, or other suitable methods.

[0144] Please refer to Figure 21 , Figure 21 This is a cross-sectional schematic diagram at a stage of fabrication method S1 according to some embodiments of the present disclosure. After step S16, a portion of the conductive layer 304 is removed. In some embodiments, a protective layer (not shown) is formed and at least covers the dielectric layers 302. In some embodiments, the protective layer laterally surrounds and vertically covers the dielectric layers 302. In some embodiments, a wet etching is performed to remove the portion of the conductive layer 304 exposed through the protective layer. In some embodiments, the protective layer is removed, and the portion of the conductive layer covered by the protective layer remains in situ. Other known methods may be used to remove this portion of the conductive layer 304, and the method of removal is not limited herein.

[0145] In some embodiments, a holding portion of the conductive layer 304 becomes a third electrode 304. In some embodiments, the first electrode 303a may be an upper electrode of the first capacitor 30a, and the third electrode 304 may be a lower electrode of the first capacitor 30a. In some embodiments, the second electrode 303b may be an upper electrode of the second capacitor 30b, and the third electrode 304 may be a lower electrode of the second capacitor 30b. In some embodiments, the third electrode 304 is a common electrode of the first capacitor 30a and the second capacitor 30b. In other words, the lower electrodes of the first capacitor 30a and the second capacitor 30b are physically connected or form a monolithic structure. In some embodiments, the third electrode 304 surrounds portions of the dielectric layers 302, the first electrode 303a, the second electrode 303b, the nitride layers 206 and 207 perpendicular to portions of the dielectric layers 302 and the electrodes 303a and 303b, and the second nitride layer 203 contacts a portion of the dielectric layers 302. In some embodiments, a third electrode 304 covers a portion of the first nitride layer 201 that contacts the dielectric layers 302. In some embodiments, a first capacitor 30a covers the entire upper surface S102a of the landing pad 102a. In some embodiments, a second capacitor 30b covers the entire upper surface S102b of the landing pad 102b.

[0146] For ease of explanation, the portions of the first capacitor 30a, the first dielectric layer 302a, and the first electrode 303a above the second nitride layer 203 can be referred to as the upper portion 31a of these elements; similarly, the portions of the second capacitor 30b, the second dielectric layer 302b, and the second electrode 303b above the second nitride layer 203 can be referred to as the upper portion 31b of these elements. Furthermore, the portions of the first capacitor 30a, the first dielectric layer 302a, and the first electrode 303a surrounded by the second nitride layer 203 can be referred to as the middle portion 32a of these elements, and the portions of the second capacitor 30b, the second dielectric layer 302b, and the second electrode 303b surrounded by the second nitride layer 203 can be referred to as the middle portion 32b of these elements. Similarly, the portions of the first capacitor 30a, the first dielectric layer 302a, and the first electrode 303a below the second nitride layer 203 can be referred to as the lower portion 33a of these components; the portions of the second capacitor 30b, the second dielectric layer 302b, and the second electrode 303b below the second nitride layer 203 can be referred to as the lower portion 33b of these components. For the sake of brevity and clarity of description, only the upper portions 31a and 31b, the middle portions 32a and 32b, and the lower portions 33a and 33b of the first dielectric layer 302a and the second dielectric layer 302b are shown in the figures, and will be described in the following description.

[0147] In some embodiments, a first gap 41 is disposed between a lower portion 33a of the first dielectric layer 302a and a lower portion 33b of the second dielectric layer 302b. In some embodiments, the first gap 41 is located above the first nitride layer 201 and below the second nitride layer 203. In some embodiments, a second gap 42 is disposed between an upper portion 31a of the first dielectric layer 302a and an upper portion 31b of the second dielectric layer 302b. In some embodiments, the second gap 42 is located above the second nitride layer 203. It should be understood that the positions of gaps 41 and 42 relative to electrodes 303a, 303b or capacitors 30a, 30b may be similar to the positions of gaps 41 and 42 relative to dielectric layers 302a, 302b as described above. Repeated descriptions are omitted herein.

[0148] In some embodiments, the first gap 41 or the second gap 42 is at least partially surrounded by the third electrode 303. However, different cross-sections may have different configurations of the third electrode 303 relative to the first gap 41 and / or the second gap 42. In some embodiments, the first gap 41 is completely surrounded by the third electrode 303. In some embodiments, as in Figure 21 In the cross-sectional view shown, the second gap 42 is an open gap and is partially surrounded by the third electrode 303, which is located along a certain stage of the preparation method S1. Figure 18 A cross-sectional view of section line A-A'.

[0149] Please refer to Figure 22 , Figure 22 Based on some embodiments of this disclosure, in a stage of preparation method S1, along Figure 18 A cross-sectional view along section line B-B'. In some embodiments, the first gap 41 and the second gap 42 are connected. In some embodiments, some openings 204 are formed in, for example... Figure 8 The first dielectric layer 302a and the second dielectric layer 302b are shown. In some embodiments, the portion of the second nitride layer 203 disposed between the first dielectric layer 302a and the second dielectric layer 302b is such that... Figure 22 The cross-sectional view shown is separate. In some embodiments, the second gap 42 is open toward the first gap 41 and the third nitride layer 207.

[0150] Please refer to Figure 23 , Figure 23 Based on some embodiments of this disclosure, in a stage of preparation method S1, along Figure 18 A cross-sectional view along section line C-C'. In some embodiments, as shown... Figure 23In the cross-sectional view shown, both the first gap 41 and the second gap 42 are closed gaps. In some embodiments, the first gap 41 is completely surrounded by the third electrode 303. In some embodiments, the second gap 42 is completely surrounded by the third electrode 303. In some embodiments, the second gap 42 is defined by the dielectric layer 302 and the nitride layers 203 and 206.

[0151] Please refer to Figure 24 , Figure 24 Based on some embodiments of this disclosure, in a stage of preparation method S1, along Figure 18 A cross-sectional view along section line D-D'. In some embodiments, such as Figure 24 In the cross-sectional view shown, the second gap 42 is connected to the first gap 41 and is surrounded by the third electrode 303. In some embodiments, a top of the second gap is covered by nitride layers 206, 207 and the third electrode 303. In some embodiments, the second gap 42 is open toward the first gap 41.

[0152] One embodiment of this disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a first landing pad included therein, and a first capacitor disposed on the substrate. The first capacitor includes a first electrode disposed on the first landing pad and extending vertically away from the first landing pad; a first dielectric layer at least partially surrounding the first electrode, wherein the first electrode is shorter than the first dielectric layer; and a second electrode surrounding the first dielectric layer and the first electrode.

[0153] Another embodiment of this disclosure provides a semiconductor structure. The semiconductor structure includes a first landing pad and a second landing pad disposed on a substrate; a first conductive layer disposed on the first landing pad and extending vertically away from the first landing pad; a second conductive layer disposed on the second landing pad and extending vertically away from the second landing pad; a first dielectric layer surrounding the first conductive layer; a second dielectric layer surrounding the second conductive layer; a third conductive layer surrounding the first dielectric layer and the second dielectric layer; and a first gap disposed between the first dielectric layer and the second dielectric layer, and at least partially surrounded by the third conductive layer.

[0154] Another embodiment of this disclosure provides a method for fabricating a semiconductor structure. The method includes providing a substrate; sequentially forming a first nitride layer, a first sacrificial layer, a second nitride layer, a second sacrificial layer, and a third nitride layer on the substrate; forming a first opening and a second opening, wherein the first opening exposes a first landing pad in the substrate, and the second opening exposes a second landing pad in the substrate; forming a first electrode in the first opening and forming a second electrode in the second opening; simultaneously removing the first sacrificial layer and the second sacrificial layer; and forming a conductive layer conformally to the first electrode, the second electrode, the first nitride layer, the second nitride layer, and the third nitride layer.

[0155] In summary, this application discloses a semiconductor structure comprising one or more capacitors located on one or more landing pads. These capacitors may include multiple upper electrodes on two adjacent landing pads, with one upper electrode formed on one landing pad. This disclosure also provides a method for fabricating the semiconductor structure. This fabrication method provides connections between different sacrificial layers, thus allowing the simultaneous removal of different sacrificial layers. This can reduce the manufacturing cost and complexity of the process. Furthermore, performing an etch-back process on each upper electrode of the capacitors and forming a nitride layer between the upper and lower electrodes prevents short circuits between the upper and lower electrodes. Providing a monolithic lower electrode for adjacent capacitors simplifies the electrical connection to that electrode.

[0156] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0157] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A method for fabricating a semiconductor structure, comprising: Provide a base; A first nitride layer, a first sacrificial layer, a second nitride layer, a second sacrificial layer, and a third nitride layer are sequentially formed on the substrate; A first opening and a second opening are formed, wherein the first opening exposes a first landing pad in the substrate, and the second opening exposes a second landing pad in the substrate; A first electrode is formed in the first opening and a second electrode is formed in the second opening; Simultaneously remove the first sacrificial layer and the second sacrificial layer; A conductive layer is formed conformally to the first electrode, the second electrode, the first nitride layer, the second nitride layer, and the third nitride layer; as well as After the second nitride layer is formed, a portion of the second nitride layer is removed, thereby exposing the first sacrificial layer. The second sacrificial layer contacts the first sacrificial layer.

2. The method for fabricating a semiconductor structure as claimed in claim 1 further includes removing a portion of the third nitride layer after forming the third nitride layer, thereby exposing the second sacrificial layer.

3. The method for fabricating a semiconductor structure as claimed in claim 1, wherein a wet etching operation is performed to simultaneously remove the first sacrificial layer and the second sacrificial layer.

4. The method for preparing a semiconductor structure as described in claim 1, wherein the first sacrificial layer comprises borosilicate glass.

5. The method for fabricating a semiconductor structure as claimed in claim 1, wherein the second sacrificial layer comprises silane oxide.

6. The method for fabricating a semiconductor structure as claimed in claim 1 further includes forming a high dielectric constant layer before forming the first electrode and the second electrode, thereby lining the sidewalls of the first opening and the second opening.

7. The method for fabricating a semiconductor structure as claimed in claim 1, further comprising removing an upper portion of the first electrode in the first opening and an upper portion of the second electrode in the second opening.

8. The method for fabricating a semiconductor structure as claimed in claim 7, further comprising forming a fourth nitride layer before removing the first sacrificial layer and the second sacrificial layer, thereby filling the first opening on the first electrode and the second opening on the second electrode.

9. The method for fabricating a semiconductor structure as described in claim 8, wherein the fourth nitride layer is disposed on the third nitride layer.

10. The method for fabricating a semiconductor structure as claimed in claim 8, wherein the conductive layer surrounds the fourth nitride layer.

11. The method for fabricating a semiconductor structure as claimed in claim 1, wherein after removing the first sacrificial layer and the second sacrificial layer, a first gap is formed between the first electrode and the second electrode and between the second nitride layer and the third nitride layer.

12. The method for fabricating a semiconductor structure as claimed in claim 11, wherein, viewed from a cross-sectional view, the conductive layer surrounds the first gap.

13. The method for fabricating a semiconductor structure as claimed in claim 1, wherein after removing the first sacrificial layer and the second sacrificial layer, a second gap is formed between the first electrode and the second electrode and between the first nitride layer and the second nitride layer.

14. The method for fabricating a semiconductor structure as claimed in claim 13, wherein the conductive layer at least partially surrounds the second gap.

15. The method of fabricating a semiconductor structure as claimed in claim 1, wherein the first opening exposes the entire upper surface of the first landing pad, and the second opening exposes the entire upper surface of the second landing pad.

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