Ferroelectric memory and method of forming the same, electronic device

Abstract

The application provides a ferroelectric memory and a forming method thereof and an electronic device. The ferroelectric memory comprises a substrate and a plurality of memory cells formed on the substrate, each memory cell comprising a ferroelectric capacitor; the ferroelectric capacitor comprises a first electrode and a second electrode stacked, a ferroelectric layer formed between the first electrode and the second electrode as a storage medium; the ferroelectric layer comprises a doping element and a hafnium oxide-based material; the concentration of the doping element presents a preset gradient change along the stacking direction of the first electrode and the second electrode. In this way, the migration channel of oxygen ions can be reduced, the migration of oxygen ions can be inhibited, the generation of oxygen vacancies can be reduced, the polarization fatigue, imprint effect and breakdown phenomenon can be slowed down or even avoided, the ferroelectric capacitor has good durability, and the ferroelectric memory comprising the ferroelectric capacitor has good storage performance.

Description

Technical Field

[0001] This application relates, and more particularly, to the field of semiconductor memory technology, and more particularly to a ferroelectric memory, a method for forming the ferroelectric memory, and an electronic device comprising the ferroelectric memory. Background Technology

[0002] Ferroelectric random access memory (FeRAM) is a type of memory that utilizes the unique non-volatile electrical properties of ferroelectric materials to store data. Generally, the data storage and retrieval function of FeRAM relies on its contained ferroelectric capacitors.

[0003] Figure 1 This is a schematic diagram of the structure of a ferroelectric capacitor. Figure 1 As shown, the ferroelectric capacitor includes a first electrode 01 and a second electrode 02 disposed opposite to each other, and a ferroelectric layer 03 formed between the first electrode 01 and the second electrode 02. A crystal in the ferroelectric phase is formed in the ferroelectric layer. When an electric field is applied to the ferroelectric layer, the central atoms of the crystal remain in a low-energy state along the electric field. When the electric field is reversed and applied to the ferroelectric layer, the central atoms move in the direction of the electric field within the crystal and remain in another low-energy state. A large number of central atoms move and couple within the crystal unit cell to form ferroelectric domains. Under the action of the electric field, these ferroelectric domains form polarization charges. The polarization charges formed before and after the reversal of the electric field have different energies. This binary stable state allows the ferroelectric capacitor to charge and discharge, thus enabling it to be recognized by an external circuit and achieving a "0" or "1" storage state. Ferroelectric film layers used in non-volatile memory must possess stable ferroelectric reversal properties to ensure good durability of the ferroelectric capacitor.

[0004] However, by Figure 1It is known that the ferroelectric layer 03 is in direct contact with the first electrode 01 and the second electrode 02. The first electrode 01 and the second electrode 02 are typically made of a metal-containing material. The metal in the first electrode 01 and the second electrode 02 will remove oxygen from the ferroelectric layer 03, creating oxygen vacancies within the ferroelectric layer 03. The gradual accumulation of oxygen vacancies is detrimental to the durability of the ferroelectric capacitor. For example, on the one hand, it will cause pinning of the domain walls of the ferroelectric domains, resulting in polarization fatigue, which in turn affects the durability of the ferroelectric capacitor; on the other hand, it will cause a change in the symmetry of the hysteresis loop of the ferroelectric layer, i.e., an imprinting effect. Under the influence of the imprinting effect, the polarization reversal of the ferroelectric layer will be hindered, i.e., the ferroelectricity and durability of the ferroelectric capacitor will decrease; furthermore, it will cause the formation of conductive filaments (also called leakage channels) within the ferroelectric layer, leading to breakdown of the ferroelectric capacitor, which in turn affects its durability. Summary of the Invention

[0005] This application provides a ferroelectric memory, a method for forming the same, and an electronic device comprising the ferroelectric memory. The main objective is to provide a ferroelectric capacitor that can suppress oxygen ion migration in the ferroelectric layer, thereby suppressing the generation of oxygen vacancies in the ferroelectric layer, mitigating or even avoiding polarization fatigue, imprinting effects, and breakdown phenomena, thus exhibiting better durability and improving the storage performance of the ferroelectric memory. To achieve the above objective, the embodiments of this application adopt the following technical solutions:

[0006] Firstly, this application provides a ferroelectric memory, which is a ferroelectric random access memory. The ferroelectric memory includes: a substrate and a plurality of memory cells formed on the substrate, each memory cell including a ferroelectric capacitor; the ferroelectric capacitor includes a stacked first electrode and a second electrode, and a ferroelectric layer formed between the first electrode and the second electrode as a storage medium; the ferroelectric layer includes a dopant element and a hafnium oxide-based material; the concentration of the dopant element exhibits a first predetermined gradient change along the stacking direction of the first electrode and the second electrode, and correspondingly, the concentration of the hafnium element exhibits a second predetermined gradient change along the stacking direction of the first electrode and the second electrode, wherein the first predetermined gradient change corresponds to the second predetermined gradient change. This predetermined gradient change allows the ferroelectric phase crystal structure formed in the ferroelectric layer to be continuously distributed between the first and second sides of the ferroelectric layer, exhibiting a distribution effect that is close to penetrating the ferroelectric layer, or in other words, exhibiting a distribution effect that is close to connecting the first electrode and the second electrode. Even if the ferroelectric phase crystal structure contains almost no other phase crystal structures, there is no layered distribution phenomenon between crystal phases, resulting in relatively high integrity. It should be noted that when the concentration of dopants in the ferroelectric layer reaches a certain level, a completely continuous ferroelectric phase crystal structure can be formed in the ferroelectric layer.

[0007] This reduces the migration channels for oxygen ions, inhibits their migration, reduces the generation of oxygen vacancies, and slows down or even avoids polarization fatigue, imprinting effects, and breakdown, resulting in better durability of the ferroelectric capacitor. Furthermore, this distribution of the ferroelectric phase crystal structure indicates a higher initial content of it in the ferroelectric layer, while the initial content of other phase crystal structures (such as antiferroelectric and dielectric phase crystal structures) is correspondingly lower. Since a higher ferroelectric phase crystal structure means a slower increase in the content of the dielectric phase crystal structure during polarization reversal, a slower rate of polarization fatigue, a slower decrease in residual polarization intensity, and after a certain number of reversals, a lower degree of polarization fatigue and a higher residual polarization intensity. Therefore, such a ferroelectric layer exhibits good ferroelectricity.

[0008] In a possible implementation of the first aspect, the concentration of the dopant element exhibits the same gradient change from a predetermined position in the ferroelectric layer towards the first and second sides. Correspondingly, the concentration of hafnium also exhibits the same gradient change from the predetermined position in the ferroelectric layer towards the first and second sides. For example, in a possible implementation, the concentration of the dopant element gradually increases or decreases from the predetermined position in the ferroelectric layer towards the first and second sides. Correspondingly, the concentration of hafnium gradually increases or decreases from the predetermined position in the ferroelectric layer towards the first and second sides. Compared to a ferroelectric layer with a uniform distribution of dopant and hafnium concentrations, the element distribution of this application allows the ferroelectric phase crystal structure formed in the ferroelectric layer to be continuously distributed between the first and second sides of the ferroelectric layer as much as possible, ensuring that the ferroelectric phase crystal structure does not include or includes as few other phase crystal structures as possible.

[0009] In the first possible implementation, the ferroelectric layer is made of zirconium-doped hafnium oxide-based material Hf. 1-x Zr x O2 is formed, where X represents the concentration of zirconium, specifically Hf. 1-x Zr x The number of zirconium atoms in O2 in Hf 1-x Zr x The percentage of zirconium and hafnium atoms in the total number of atoms in O2; the minimum concentration X of zirconium at the preset position when the concentration of zirconium gradually increases from the preset position in the ferroelectric layer towards the first and second sides. min The concentration X is between 0 and 0.50, and the maximum concentration is on both the first and second sides. max Between 0.50 and 0.99; the maximum concentration X of zirconium at the preset position, where the concentration gradually decreases from the preset position towards the first and second sides. max Between 0.50 and 0.99, and the minimum concentration X on both the first and second sides. min Between 0 and 0.50.

[0010] In one possible implementation of the first aspect, the ferroelectric layer comprises a dopant element and a hafnium oxide-based material; the ratio of the concentration of the dopant element to the concentration of the hafnium element exhibits a predetermined gradient change along the stacking direction of the first and second electrodes. Optionally, the ratio of their concentrations exhibits the same gradient change from a predetermined position in the ferroelectric layer towards the first and second sides. For example, the ferroelectric layer uses a zirconium-doped hafnium oxide-based material Hf. 1-x Zr x O2 is formed, where X represents the concentration of zirconium, (1-X) is the concentration of hafnium, and X / (1-X) is the concentration ratio of zirconium to hafnium. The value of X / (1-X) can gradually increase or decrease from a predetermined position in the ferroelectric layer towards the first and second sides.

[0011] In a possible implementation of the first aspect, the ferroelectric layer has a residual polarization intensity greater than a preset value, where the preset value is greater than zero. For the ferroelectric layer in the ferroelectric capacitor of this application, when the applied electric field (i.e., E) is removed from the ferroelectric layer... bias When the polarization is zero, the ferroelectric layer exhibits a high remanent polarization intensity. Furthermore, it retains a high remanent polarization intensity even after a certain number of polarization reversals. Consequently, the ferroelectric memory containing this ferroelectric capacitor possesses robust non-volatility.

[0012] In one possible implementation of the first aspect, the thickness of the ferroelectric layer in the stacking direction of the first and second electrodes is 0.5 nm to 50 nm.

[0013] Secondly, this application provides a method for forming a ferroelectric memory, the method comprising:

[0014] A first electrode and a second electrode are formed on one side of a substrate, and the first electrode and the second electrode are stacked. A ferroelectric layer is formed between the first electrode and the second electrode. The ferroelectric layer includes a dopant element and a hafnium oxide-based material. The concentration of the dopant element varies with a first preset gradient along the stacking direction of the first electrode and the second electrode. Correspondingly, the concentration of the hafnium element varies with a second preset gradient along the stacking direction of the first electrode and the second electrode. The first preset gradient variation corresponds to the second preset gradient variation.

[0015] The method for forming a ferroelectric memory disclosed in this application not only fabricates a first and second electrode for applying voltage and a ferroelectric layer for storing charge, but also ensures that the ferroelectric phase crystal structure formed in the ferroelectric layer is continuously distributed between the first and second sides of the ferroelectric layer, exhibiting a distribution effect that is close to penetrating the ferroelectric layer, or in other words, exhibiting a distribution effect that is close to connecting the first and second electrodes. Even if the ferroelectric phase crystal structure contains almost no other phase crystal structures, there is no layering distribution phenomenon between crystal phases, resulting in relatively high integrity. It should be noted that when the concentration of doping elements in the ferroelectric layer reaches a certain condition, a completely continuous ferroelectric phase crystal structure can be formed in the ferroelectric layer. Such a ferroelectric layer enables the ferroelectric capacitor to have good durability and ferroelectricity. When the thickness of the ferroelectric layer is reduced to 10 nm or less, it also exhibits good ferroelectricity and durability.

[0016] In a possible implementation of the second aspect, forming a ferroelectric layer between the first and second electrodes includes: firstly, depositing a ferroelectric layer on the first or second electrode using a dopant element and a hafnium oxide-based material; and then crystallizing the ferroelectric layer to form a continuous ferroelectric phase crystal structure between the first and second sides within the ferroelectric layer.

[0017] The method for forming a ferroelectric memory disclosed in this application controls the formation of a continuous ferroelectric phase crystal structure in the ferroelectric layer by controlling the concentration distribution of the doping element (or hafnium element) in the ferroelectric layer. For example, the hafnium oxide-based material Hf doped with zirconium described above... 1-x Zr x Taking O2 as an example, the concentration X of zirconium can be controlled to be relatively high first, then the proportion of concentration X can be gradually decreased, and finally the concentration X of zirconium can be gradually increased. In the final ferroelectric layer, the concentration distribution of zirconium shows a gradient change pattern of "first decreasing, then increasing". Alternatively, the concentration X of zirconium can be controlled to be relatively low first, then the proportion of concentration X can be gradually increased, and finally the concentration X of zirconium can be gradually decreased. In the final ferroelectric layer, the concentration distribution of zirconium shows a gradient change pattern of "first increasing, then decreasing".

[0018] In the second possible implementation, ferroelectric layers are deposited using deposition processes such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition. This results in ferroelectric layers that are relatively uniform, have high flatness, and high conformability, meaning that the shape and surface flatness of each layer are basically consistent.

[0019] Thirdly, this application also provides a method for forming a ferroelectric memory, the method comprising:

[0020] A first doped region and a second doped region are formed in a substrate, and a ferroelectric layer and a gate are formed on the substrate. The ferroelectric layer is formed in a channel region between the first doped region and the second doped region, and the gate is formed on the side of the ferroelectric layer away from the substrate. The ferroelectric layer includes doping elements and hafnium oxide-based materials. The gate and the ferroelectric layer are annealed to form a ferroelectric phase crystal structure in the ferroelectric layer. The ferroelectric phase crystal structure is continuously distributed between the first side near the gate and the second side away from the gate.

[0021] The method for forming a ferroelectric memory disclosed in this application not only fabricates a first doped region, a second doped region, and a gate for applying a voltage, as well as a ferroelectric layer for storing charge, but also ensures that the ferroelectric phase crystal structure is continuously distributed between a first side close to the gate and a second side far from the gate in the fabricated ferroelectric layer. This ferroelectric phase crystal structure enables the ferroelectric capacitor to possess good durability and ferroelectricity.

[0022] Fourthly, this application also provides an electronic device, including a processor and a ferroelectric memory as described in any of the first, second, or third aspects above, wherein the processor is electrically connected to the ferroelectric memory.

[0023] The electronic device provided in this application includes the ferroelectric memory of the first aspect embodiment, the second aspect embodiment, or the third aspect embodiment. Therefore, the electronic device provided in this application and the ferroelectric memory of the above technical solutions can solve the same technical problems and achieve the same expected effects. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a ferroelectric capacitor structure;

[0025] Figure 2 for Figure 1 A schematic diagram showing the generation of oxygen vacancies through an oxidation reaction between the ferroelectric layer 03 and the first electrode 01 and the second electrode 02.

[0026] Figure 3 This is a schematic diagram of an imprinting effect caused by oxygen vacancies in a ferroelectric layer.

[0027] Figure 4 This is a schematic diagram of a breakdown phenomenon caused by oxygen vacancies in a ferroelectric layer.

[0028] Figure 5 This is a schematic diagram of another ferroelectric capacitor structure;

[0029] Figure 6 This is a schematic diagram of another type of ferroelectric capacitor structure;

[0030] Figure 7 A circuit diagram of an electronic device provided in an embodiment of this application;

[0031] Figure 8 A circuit diagram of a ferroelectric memory provided in an embodiment of this application;

[0032] Figure 9 A circuit diagram of a storage cell in a ferroelectric memory provided for an embodiment of this application;

[0033] Figure 10 A circuit diagram of a storage array formed by multiple storage cells in a ferroelectric memory provided in an embodiment of this application;

[0034] Figure 11 A circuit diagram of a storage cell in a ferroelectric memory provided for an embodiment of this application;

[0035] Figure 12 A circuit diagram of a storage array formed by multiple storage cells in a ferroelectric memory provided in an embodiment of this application;

[0036] Figure 13 This is a schematic diagram illustrating the positional relationship between a ferroelectric capacitor and a substrate in a ferroelectric memory provided in an embodiment of this application.

[0037] Figure 14 This is a schematic diagram illustrating the positional relationship between a ferroelectric capacitor and a substrate in a ferroelectric memory provided in an embodiment of this application.

[0038] Figure 15 for Figure 14 F-direction view;

[0039] Figure 16 This is a transmission electron microscope (TEM) image of a cross-section of the ferroelectric layer in the stacking direction of the first and second electrodes in the prior art.

[0040] Figure 17 A transmission electron microscope (TEM) image of a cross-section of the ferroelectric layer provided in the embodiment of this application in the stacking direction of the first electrode and the second electrode;

[0041] Figure 18 A schematic diagram showing the relationship between the polarization intensity and the applied electric field of a ferroelectric capacitor provided in an embodiment of this application;

[0042] Figure 19 This is a schematic diagram showing the zirconium concentration X distribution in the ferroelectric layer provided in an embodiment of this application;

[0043] Figure 20 This is a schematic diagram showing the zirconium concentration X distribution in the ferroelectric layer provided in an embodiment of this application;

[0044] Figure 21 A schematic diagram showing the concentration distribution of zirconium and hafnium elements in the ferroelectric layer provided in this embodiment of the application;

[0045] Figure 22A flowchart illustrating the fabrication of ferroelectric capacitors in a ferroelectric memory, provided as an embodiment of this application;

[0046] Figure 23 A process structure diagram of a memory cell in a ferroelectric memory provided in an embodiment of this application;

[0047] Figure 24 A circuit diagram of a storage array formed by multiple storage cells in a ferroelectric memory provided in an embodiment of this application;

[0048] Figure 25 This is a flowchart illustrating the fabrication of a memory cell in a ferroelectric memory, as provided in an embodiment of this application. Detailed Implementation

[0049] Before introducing the embodiments involved in this application, the technical terms involved in this application will be introduced first, as follows:

[0050] A unit cell is a structure composed of a large number of microscopic material units (atoms, ions, molecules, etc.) arranged in an orderly manner according to certain rules.

[0051] Grains: During the growth process, crystalline materials crystallize into granular shapes, which are called grains. The internal unit cells of a grain are generally aligned in direction and position.

[0052] Grain boundary: The contact interface between grains is called a grain boundary.

[0053] Ferroelectric crystals: The structure of the unit cell causes the centers of positive and negative charges to not coincide, resulting in an electric dipole moment. This generates a non-zero polarization intensity, giving the crystal spontaneous polarization. Furthermore, the direction of the electric dipole moment can be changed by an external electric field, exhibiting characteristics similar to ferromagnetic materials.

[0054] Ferroelectric materials are materials that can maintain spontaneous polarization by applying an electric field to align their internal electric dipole moments, even when the externally applied electric field is removed. In other words, ferroelectrics are materials in which the polarization intensity (polarization) value (or electric field) is semi-permanently retained, even after a constant voltage is applied and the voltage is restored to zero volts.

[0055] Ferroelectric memories (FEMs) store data based on the ferroelectric effect of ferroelectric materials. Due to their ultra-high storage density, low power consumption, and high speed, FEMs are expected to become a major competitor to dynamic random access memory (DRAM). A FEM cell contains a ferroelectric capacitor, which consists of two electrodes and a ferroelectric material, such as a ferroelectric layer, disposed between the electrodes. Because of the nonlinear characteristics of ferroelectric materials, their dielectric constant can be adjusted, and the difference before and after the polarization state reversal of the ferroelectric layer is very large. This makes ferroelectric capacitors much smaller than other capacitors; for example, they are much smaller than the capacitors used to store charge in DRAM.

[0056] like Figure 1 As shown, in ferroelectric capacitors, the ferroelectric layer can be formed using common ferroelectric materials. After crystallization, a ferroelectric phase crystal structure can be formed in the ferroelectric layer. When an electric field is applied to the ferroelectric layer, the central atoms in the ferroelectric phase crystal structure remain in a low-energy state along with the electric field. Conversely, when the electric field is reversed and applied to the ferroelectric layer, the central atoms move in the direction of the electric field and remain in another low-energy state. A large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains. These ferroelectric domains form polarization charges under the action of an electric field. The polarization charges formed by the reversal of ferroelectric domains under an electric field are higher, while the polarization charges formed by the absence of reversal of ferroelectric domains under an electric field are lower. This binary stable state of ferroelectric materials makes them suitable for use in memory devices.

[0057] Ferroelectric capacitors used in non-volatile memory must possess stable ferroelectric switching properties in their ferroelectric layers to ensure good durability. Factors affecting the durability of ferroelectric capacitors include, but are not limited to, polarization fatigue, imprinting effect, and breakdown.

[0058] like Figure 1 As shown, since the ferroelectric layer 03 is formed between the first electrode 01 and the second electrode 03, and the first electrode 01 and the second electrode 03 are made of a material containing metal, this ferroelectric capacitor structure can be called a "MIM" (metal-insulation-metal) ferroelectric capacitor structure. During the cyclic switching process of the "MIM" ferroelectric capacitor, the ferroelectric layer 03 acts as an oxygen ion donor, and the first electrode 01 and the second electrode 02 act as oxygen ion acceptors, undergoing an oxidation reaction. Positively charged oxygen ion vacancies (referred to as oxygen vacancies) are generated near the contact surface between the ferroelectric layer 03 and the electrodes and inside the ferroelectric layer 03. Figure 2 for Figure 1 A schematic diagram showing the generation of oxygen vacancies through an oxidation reaction between the ferroelectric layer 03 and the first electrode 01 and the second electrode 02. (See diagram below.) Figure 2As shown, an oxidation reaction occurs between the ferroelectric layer 03 and the first electrode 01 and the second electrode 02. Oxygen ions in the ferroelectric layer 03 migrate to the first electrode 01 and the second electrode 02, forming oxygen vacancies in the ferroelectric layer 03.

[0059] It is worth noting that the gradual accumulation of oxygen vacancies can lead to polarization fatigue, imprinting effect and breakdown, which in turn affects the durability of ferroelectric capacitors.

[0060] Polarization fatigue refers to the phenomenon where the polarization intensity of a ferroelectric material decreases after multiple polarization flips. Ferroelectric memories undergo numerous erase / rewrite operations during information reading and writing, causing the ferroelectric layer to continuously flip its polarization. After repeated cycles, the residual polarization intensity (Pr) of the ferroelectric layer decreases, the coercive field (Ec) increases, and the "0" and "1" states become increasingly indistinguishable. On one hand, charged defects such as oxygen vacancies within the ferroelectric layer pinnate domain walls, leading to polarization fatigue. On the other hand, the ferroelectric layer typically contains randomly distributed ferroelectric, antiferroelectric, and dielectric crystal structures. During polarization flips, the ferroelectric crystal structure transforms into a dielectric crystal structure, meaning that the content of the ferroelectric crystal structure gradually decreases from its initial content, while the content of the dielectric crystal structure gradually increases from its initial content. Since the remanent polarization intensity of the ferroelectric layer is closely related to the content of ferroelectric phase crystals in the ferroelectric layer, a gradual decrease in the content of ferroelectric phase crystal structures will inevitably lead to a decrease in the remanent polarization intensity of the ferroelectric layer, resulting in polarization fatigue. The embodiments of this application involve the initial content of various crystal phase structures, which can be understood as the content of various crystal phase structures before the first polarization reversal of the ferroelectric layer.

[0061] The imprinting effect refers to the phenomenon where the charge injected by the electrode creates a built-in electric field in the ferroelectric layer, hindering the reversal of ferroelectric dipoles. Under the influence of the imprinting effect, the polarization reversal of the ferroelectric layer is impeded, manifesting as a drift in the coercive field and an increase in the ferroelectric reversal time. Simultaneously, the remanent polarization intensity decreases. Once the coercive field drift exceeds the threshold voltages for the "0" and "1" states of the memory, data read / write errors will occur, and the decay of the remanent polarization intensity will weaken the stored signal, increasing the error rate of data readout. Figure 3 A schematic diagram of the imprinting effect caused by oxygen vacancies in a ferroelectric layer is shown. The horizontal axis represents the applied electric field strength E of the ferroelectric layer, and the vertical axis represents the polarization intensity P of the ferroelectric layer. The solid black line represents the hysteresis loop of the ferroelectric layer before oxygen vacancies are generated, and the dashed black line represents the hysteresis loop of the ferroelectric layer after oxygen vacancies are generated. It can be seen that after oxygen vacancies are generated, the symmetry of the hysteresis loop of the ferroelectric layer deteriorates, and the ferroelectricity decreases.

[0062] Breakdown refers to the phenomenon where the charging and discharging voltage of a ferroelectric capacitor causes the dielectric material to break down. Figure 4A schematic diagram of a breakdown phenomenon caused by oxygen vacancies in a ferroelectric layer is shown, where the horizontal axis represents the number of polarization reversals, and the vertical axis corresponds to twice the residual polarization intensity Pr in each reversal process. It can be seen that the gradual accumulation of oxygen vacancies in the ferroelectric layer forms conductive filaments (also called leakage channels) within the ferroelectric layer, leading to breakdown after a certain number of polarization reversals.

[0063] Combination Figure 1 The “MIM” ferroelectric capacitor shown is, for example Figure 5 As shown, in order to suppress the migration of oxygen ions in the ferroelectric layer, the following measures are taken: Figure 1 The ferroelectric layer 03 in the original structure is replaced by a periodic layered structure 04 of HfO2-ZrO2 with a periodic thickness of 1 nm. In this periodic layered structure 04, HfO2 and ZrO2 layers alternate; that is, a ZrO2 layer exists between two adjacent HfO2 layers, and / or an HfO2 layer exists between two adjacent ZrO2 layers. This suppresses oxygen ion migration and oxygen vacancy generation, thereby improving the durability of the ferroelectric capacitor. However, when the HfO2-ZrO2 periodic layered structure is selected as the ferroelectric layer in a "MIM" ferroelectric capacitor, the HfO2 layer itself does not easily crystallize into a ferroelectric phase; it must co-crystallize with the ZrO2 layer. This means that such a HfO2-ZrO2 periodic layered structure is not fundamentally different from Zr-doped HZO. Furthermore, when the ferroelectric layer thickness is small (e.g., <10 nm), the effect of the HfO2-ZrO2 periodic layered structure is very limited.

[0064] Combination Figure 1 The “MIM” ferroelectric capacitor shown is, for example Figure 6 As shown, to suppress the migration of oxygen ions in the ferroelectric layer, an oxygen-rich material layer (e.g., TiO2) is inserted between the ferroelectric layer 03 and the first electrode 01, and between the ferroelectric layer 03 and the second electrode 02, respectively, serving as a transition layer 05 between the electrode and the ferroelectric layer. When an oxidation reaction occurs, the oxygen ions in the transition layer 05 react with the electrode first, thereby slowing down the migration of oxygen ions and the generation of oxygen vacancies, thus suppressing the charge imbalance inside the ferroelectric layer. However, because the coefficient of thermal expansion and crystallization temperature of the newly introduced dielectric layer (i.e., the aforementioned oxygen-rich material transition layer) differ significantly from those of the ferroelectric layer, mismatch strain is easily generated during crystallization, leading to lattice dislocation in the ferroelectric layer and the generation of more defects. Furthermore, the introduction of other non-ferroelectric layers will cause additional voltage division, which may lead to an unnecessary increase in the applied electric field and related power consumption.

[0065] This application provides an electronic device including a ferroelectric memory, which comprises a ferroelectric capacitor. Compared to the above... Figure 5 and Figure 6The ferroelectric capacitor shown in this embodiment not only effectively suppresses ferroelectric polarization fatigue, imprinting effect, and breakdown, thus improving the durability of the ferroelectric capacitor, but also exhibits good ferroelectricity and durability when the thickness of the ferroelectric layer is reduced to 10 nm or less.

[0066] Figure 7 An electronic device 200 is provided in this application embodiment. The electronic device 200 can be a terminal device, such as a mobile phone, tablet computer, or smart bracelet, or a personal computer (PC), server, workstation, etc. The electronic device 200 includes a bus 205, and a system-on-chip (SOC) 210 and a read-only memory (ROM) 220 connected to the bus 205. The SOC 210 can be used to process data, such as processing application data, processing image data, and caching temporary data. The ROM 220 can be used to store non-volatile data, such as audio files, video files, etc. The ROM 220 can be a PROM (programmable read-only memory), an EPROM (erasable programmable read-only memory), flash memory, etc.

[0067] In addition, the electronic device 200 may also include a communication chip 230 and a power management chip 240. The communication chip 230 may be used for protocol stack processing, or for amplifying, filtering, or performing other processing on analog radio frequency signals, or simultaneously performing the above functions. The power management chip 240 may be used to supply power to other chips.

[0068] In one embodiment, SOC 210 may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and random access memory (RAM) 213 for caching data.

[0069] The aforementioned AP211, GPU212, and RAM213 can be integrated into a single die, or integrated into multiple dies and packaged in a single package structure, such as 2.5D, 3D packaging, or other advanced packaging technologies. In one embodiment, the AP211 and GPU212 are integrated into one die, and RAM213 is integrated into another die; these two dies are packaged in a single package structure to achieve faster inter-die data transfer rates and higher data transfer bandwidth.

[0070] Figure 8 This is a schematic diagram of the structure of a ferroelectric memory 300 provided in an embodiment of this application. The ferroelectric memory 300 can be as follows: Figure 7 The RAM 213 shown is a FeRAM. In one embodiment, the ferroelectric memory 300 may also be a RAM disposed outside the SOC 210. This application does not limit the location of the ferroelectric memory 300 in the device or its positional relationship with the SOC 210.

[0071] Continue as Figure 8 The ferroelectric memory 300 includes a memory array 310, a decoder 320, a driver 330, a timing controller 340, a buffer 350, and an input / output driver 360. The memory array 310 includes multiple memory cells 400 arranged in an array, each of which can store 1 bit or more bits of data. The memory array 310 also includes signal lines such as word lines (WL) and bit lines (BL). Each memory cell 400 is electrically connected to a corresponding word line WL or bit line BL. One or more of the aforementioned word lines WL and bit lines BL are used to select the memory cell 400 to be read or written in the memory array by receiving a control level output from a control circuit, thereby changing the polarization direction of the ferroelectric capacitor in the memory cell 400, and thus realizing data read / write operations.

[0072] exist Figure 8In the ferroelectric memory 300 structure shown, decoder 320 decodes the received address to determine the memory cell 400 to be accessed. Driver 330 controls the level of signal lines based on the decoding result generated by decoder 320, thereby enabling access to the specified memory cell 400. Buffer 350 buffers the read data, for example, using a first-in-first-out (FIFO) buffering method. Timing controller 340 controls the timing of buffer 350 and controls driver 330 to drive the signal lines in memory array 310. Input / output driver 360 drives transmission signals, such as driven received data signals and driven data signals to be sent, enabling long-distance transmission of data signals.

[0073] The aforementioned memory array 310, decoder 320, driver 330, timing controller 340, buffer 350 and input / output driver 360 can be integrated into one chip or integrated into multiple chips respectively.

[0074] The ferroelectric memory 300 involved in this application can be a ferroelectric random access memory (FeRAM) or a ferroelectric field-effect transistor (FeFET).

[0075] for example, Figure 9 The circuit structure diagram of one of the memory cells 400 of FeRAM is given, as follows: Figure 9 The memory cell 400 includes at least two ferroelectric capacitors C and one transistor Tr, for example, Figure 9 Three ferroelectric capacitors are given as an example (e.g.) Figure 9 The ferroelectric capacitors C1, C2, and C3 are used to form a 1TnC memory cell. Here, the transistor Tr can be a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0076] In addition, the memory cell 400 also includes word line (WL), bit line (BL), and plate line (PL) signal lines. Within the memory cell 400, the first terminal of transistor Tr is electrically connected to the bit line BL, the control terminal of transistor Tr is electrically connected to the word line WL, the second terminal of transistor Tr is electrically connected to the first electrode of ferroelectric capacitor C, and the second electrode of ferroelectric capacitor C is electrically connected to the plate line PL. One of the drain or source terminals of transistor Tr is called the first terminal, and the other terminal is called the second terminal. The control terminal of transistor Tr is the gate.

[0077] Figure 9 The illustrated memory cell 400 can be used to store multiple bits of data, thereby increasing the storage capacity of each memory cell. In particular, these ferroelectric capacitors C share a single transistor Tr, which further reduces the number of transistors in each memory cell 400, thus increasing storage density.

[0078] The above Figure 9 The storage cells 400 shown can be arranged in an array to form a storage array 310, wherein each storage cell 400 has the same circuit structure, for example, Figure 10 The illustrated storage array 310 exemplarily presents a storage array comprising four storage cells: storage cell 401, storage cell 402, storage cell 403, and storage cell 404. Those skilled in the art can design the arrangement and number of storage cells 400 in the storage array 310 according to the storage capacity requirements of the ferroelectric memory. In one embodiment, the storage array 310 may further include more storage cells 400, and these storage cells 400 may be arranged in mutually perpendicular X, Y, and Z directions to form a three-dimensional storage array.

[0079] Figure 11 A circuit diagram of another FeRAM memory cell 400 is shown. This memory cell 400 includes a first transistor Tr1 and a second transistor Tr2, as well as at least two ferroelectric capacitors, for example... Figure 11 An exemplary storage cell 400 includes two ferroelectric capacitors, namely ferroelectric capacitor C1 and ferroelectric capacitor C2. Ferroelectric capacitor C2 and ferroelectric capacitor C1 have the same structure, both including two electrodes and a ferroelectric layer located between the two electrodes. To facilitate the clear description of the electrical connection relationship between ferroelectric capacitors C2 and C1 and other structures below, one electrode of ferroelectric capacitor C1 can be called the first electrode and the other electrode can be called the second electrode, and one electrode of ferroelectric capacitor C2 can be called the third electrode and the other electrode can be called the fourth electrode.

[0080] Combined Figure 11 The memory cell 400 also includes a word line (WL), a write bit line (WBL), a read bit line (RBL), a source line (SL), and a control line (CL). Specifically, the control terminal of the first transistor Tr1 is electrically connected to the control line CL; the first terminal of the first transistor Tr1 is electrically connected to the first electrode of ferroelectric capacitor C1 and the third electrode of ferroelectric capacitor C2, respectively; the second terminal of the first transistor Tr1 is electrically connected to the write bit line WBL; and the second electrode of ferroelectric capacitor C1 and the fourth electrode of ferroelectric capacitor C2 are electrically connected to the corresponding word line WL.

[0081] For example Figure 11 The first terminal of the second transistor Tr2 is electrically connected to the source line SL, and the second terminal is electrically connected to the read line RBL. The control terminal of the second transistor T2 is electrically connected to the first terminal of the ferroelectric capacitor C1 and the third terminal of the ferroelectric capacitor C2, respectively.

[0082] In one alternative implementation, the above-mentioned Figure 11 The storage cells 400 shown can be obtained by arranging them in an array. Figure 12 The storage array 310 shown, for example, Figure 12 The storage array 310 shown is exemplarily provided as a storage array comprising four storage cells: storage cell 401, storage cell 402, storage cell 403, and storage cell 404.

[0083] exist Figure 12 The given storage array 310 includes two control lines, namely control line CL0 and control line CL1, and each control line extends along the Y direction. When the storage array 310 includes more storage cells, it will also include more control lines CL. These control lines are arranged in parallel along the X direction, which is perpendicular to the Y direction. Furthermore, multiple storage cells arranged along the Y direction can share a single control line. For example, storage cells 401 and 404 share the control line CL0, and storage cells 402 and 403 share the control line CL1.

[0084] Continue to combine Figure 12 The storage array 310 includes two write bit lines, namely write bit line WBL0 and write bit line WBL1, and each write bit line extends along the X direction. When it includes more write bit lines WBL, these write bit lines WBL are arranged in parallel along the Y direction perpendicular to the X direction. In addition, multiple storage cells arranged along the X direction can share a single write bit line WBL. For example, storage cells 401 and 402 share write bit line WBL1, and storage cells 403 and 404 share write bit line WBL0.

[0085] Similarly, the settings for the read bit line RBL and the write bit line WBL are the same, and will not be repeated here.

[0086] It is important to note that the source lines SL in this memory array are shared not only by multiple memory cells arranged along the X direction, but also by multiple memory cells arranged along the Y direction. For example, the source line SL of memory cell 401 is shared with the source line SL of memory cell 404, and the source line SL of memory cell 401 is also shared with the source line SL of memory cell 402. That is, the source lines SL of memory cells 401, 402, 403, and 404 are interconnected. In feasible process structures, a source line SL layer structure parallel to the substrate can be formed to electrically connect the source lines parallel to the substrate.

[0087] Furthermore, it's important to note that the word lines WL in this memory array are shared not only by multiple memory cells arranged along the X direction but also by multiple memory cells arranged along the Y direction. For example, the word line WL0 connected to the ferroelectric capacitor C0 of memory cell 401 is shared with the word line WL0 connected to the ferroelectric capacitor C0 of memory cell 402, and the word line WL0 connected to the ferroelectric capacitor C0 of memory cell 401 is also shared with the word line WL0 connected to the ferroelectric capacitor C0 of memory cell 404. In other words, the word lines WL0 of the four ferroelectric capacitors C0 of memory cells 401, 402, 403, and 404 are interconnected, and the WL1 of the four ferroelectric capacitors C1 of memory cells 401, 402, 403, and 404 are interconnected. Similarly, in feasible process structures, a word line layer structure parallel to the substrate can be provided to interconnect word lines located on the same layer.

[0088] In the above Figures 9 to 12 In the FeRAM storage cell 400 shown, the overall structure of the ferroelectric capacitor can be as follows: Figure 1 The “MIM” structure shown includes a stacked first electrode 01 and a second electrode 02, and a ferroelectric layer 03 formed between the first electrode 01 and the second electrode 02.

[0089] In some implementations, the first electrode 01, the ferroelectric layer 03, and the second electrode 02 are disposed on the substrate 100 in the following ways: Figure 13 As shown, the first electrode 01, the ferroelectric layer 03, and the second electrode 02 are stacked in a direction perpendicular to the substrate 100. That is, each of the three layers of the first electrode 01, the ferroelectric layer 03, and the second electrode 02 is arranged parallel to the substrate 100. Such a ferroelectric capacitor can be called a planar ferroelectric capacitor structure.

[0090] In other implementations, the first electrode 01, the ferroelectric layer 03, and the second electrode 02 are disposed on the substrate 100 in the following manner: Figure 14 As shown, the first electrode 01, the ferroelectric layer 03, and the second electrode 02 are stacked along a direction parallel to the substrate 100. Such a ferroelectric capacitor can be called a vertical capacitor structure. Using a vertical capacitor structure allows for three-dimensional stacking, thereby increasing storage density and capacity.

[0091] Figure 15 One feasible structure for a vertical ferroelectric capacitor is presented, and Figure 15 yes Figure 14 The image shows a view from direction F. Specifically, the first electrode 01 extends in a direction perpendicular to the substrate 100, and the ferroelectric layer 03 and the second electrode 02 sequentially surround the first electrode 01 in a direction parallel to the substrate 100. This forms a cylindrical ferroelectric capacitor. The cross-section of the cylindrical ferroelectric capacitor can be... Figure 15 The shape shown can be a circle, a rectangle, or any other shape.

[0092] The following embodiments use a planar ferroelectric capacitor structure (such as the "MIM" structure mentioned above) as an example to illustrate the technical solution of this application.

[0093] The first electrode 01 and the second electrode 02 described above can be made of metal-containing materials, such as metals, metal nitrides, metal carbides, conductive metal nitrides, conductive metal oxides, or combinations thereof. For example, the first electrode 01 may include, for example, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), iridium oxide (IrO2), niobium nitride (NbN), molybdenum nitride (MoN), or combinations thereof. The second electrode 02 may include, for example, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium carbonitride (TiCN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), niobium nitride (NbN), molybdenum nitride (MoN), iridium oxide (IrO2), silicon (Si), germanium (Ge), germanium-silicon (SiGe), or combinations thereof. Furthermore, the materials of the first electrode 01 and the second electrode 02 can be the same or different.

[0094] In some designs, the thickness of the first electrode 01 and the second electrode 02 along the stacking direction can be, but is not limited to, 1 nm to 100 nm. Furthermore, the thickness of the first electrode 01 and the thickness of the second electrode 02 can be equal or unequal.

[0095] The aforementioned ferroelectric layer 03 exhibits ferroelectricity, thus possessing spontaneous polarization within a certain temperature range, and its spontaneous polarization direction can be reversed by the reversal of the direction of the external electric field. In this way, when its polarization orientation is reversed, the ferroelectric capacitor will charge and discharge, which can then be recognized by the external circuit to achieve a "0" or "1" storage state.

[0096] The aforementioned ferroelectric layer 03 can be fabricated using hafnium oxide-based materials. Compared to other ferroelectric materials, the thickness of hafnium oxide-based ferroelectric capacitors can be miniaturized to tens of nanometers or even sub-tens of nanometers. This enables high-density integration and even three-dimensional integration, offering significant advantages in constructing ultra-high-density memory chips. Furthermore, the fabrication process of hafnium oxide-based ferroelectric capacitors is highly compatible with silicon-based semiconductor processes, allowing for the use of mature manufacturing techniques without increasing manufacturing costs.

[0097] The aforementioned hafnium oxide-based materials refer to ferroelectric materials based on hafnium oxide material systems. For example, they can be zirconium (Zr)-doped hafnium dioxide (HfO2), silicon (Si)-doped HfO2, aluminum (Al)-doped HfO2, lanthanum (La)-doped HfO2, yttrium (Y)-doped HfO2, gadolinium (Gd)-doped HfO2, strontium (Sr)-doped HfO2, etc.; or they can be hafnium-zirconium oxide (HZO) systems, such as lanthanum (La)-doped HZO, yttrium (Y)-doped HZO, strontium (Sr)-doped HZO, gadolinium (Gd)-doped HZO, gadolinium-lanthanum (Gd / La) co-doped HZO, etc. The doping element can also be one or more of nitrogen, iron, lutetium, praseodymium, germanium, scandium, cerium, neodymium, magnesium, barium, indium, gallium, calcium, and carbon.

[0098] In some scenarios, titanium nitride (TiN) can be selected to prepare the first electrode 01 and the second electrode 02, and zirconium (Zr)-doped hafnium dioxide (HZO) can be used to prepare the ferroelectric layer 03. This fully utilizes the tensile stress provided by the HZO layer, which is conducive to the formation of the ferroelectric phase, as well as the compatibility of TiN material with semiconductor CMOS processes.

[0099] In this embodiment, the migration of oxygen ions in the ferroelectric layer 03 is effectively suppressed, thereby mitigating or even avoiding the aforementioned polarization fatigue, imprinting effect, and breakdown phenomena, resulting in better durability performance of the ferroelectric capacitor. The technical solution of this application is described below from the perspectives of crystal phase distribution in the ferroelectric layer 03 and element concentration distribution in the ferroelectric layer.

[0100] In this embodiment, a continuous ferroelectric phase crystal structure is formed in the ferroelectric layer 03. This continuous ferroelectric phase crystal structure extends from the side of the ferroelectric layer 03 near the first electrode 01 to the side of the ferroelectric layer 03 near the second electrode 02. For ease of explanation, in this embodiment, the side of the ferroelectric layer 03 near the first electrode 01 is referred to as the first side, and the side of the ferroelectric layer 03 near the second electrode 02 is referred to as the second side.

[0101] Here, a continuous ferroelectric phase crystal structure can be understood as a ferroelectric phase crystal structure continuously distributed between the first and second sides of the ferroelectric layer, exhibiting a distribution effect that nearly penetrates the ferroelectric layer, or in other words, exhibiting a distribution effect that nearly connects the first and second electrodes. A continuous ferroelectric phase crystal structure can be further understood as a ferroelectric phase crystal structure that contains almost no other phase crystal structures and does not exhibit layered distribution between crystal phases, possessing relatively high integrity.

[0102] In the above Figure 6 The ferroelectric layer shown contains randomly distributed ferroelectric, antiferroelectric, and dielectric crystal structures. Due to the high randomness of these distributions, the ferroelectric layer as a whole contains numerous grain boundaries of different crystal phases. Since these grain boundaries provide pathways for oxygen ion migration, they exacerbate this migration, leading to more oxygen vacancies. This, in turn, intensifies polarization fatigue, imprinting effects, and breakdown phenomena, negatively impacting the durability of the ferroelectric capacitor.

[0103] Furthermore, the above Figure 6 In the ferroelectric layer shown, the initial content of antiferroelectric and dielectric phase crystal structures is relatively high, while the initial content of ferroelectric phase crystal structure is relatively low. This is one of the reasons for the random distribution of ferroelectric, antiferroelectric, and dielectric phase crystal structures in the ferroelectric layer, and also one of the reasons for the poor flipping properties of the ferroelectric layer. It should be noted that "the initial content of antiferroelectric and dielectric phase crystal structures is relatively high, while the initial content of ferroelectric phase crystal structure is relatively low" does not mean that the initial content of antiferroelectric and dielectric phase crystal structures is greater than the initial content of ferroelectric phase crystal structure, but rather that, relative to the ferroelectric layer provided in this application, the initial content of antiferroelectric and dielectric phase crystal structures is higher, while the initial content of ferroelectric phase crystal structure is lower.

[0104] Figure 16 This is a transmission electron microscope (TEM) image of a cross-section of a ferroelectric layer in the prior art. The TEM image shows the cross-sectional structure of the ferroelectric layer along the stacking direction of the first and second electrodes. This ferroelectric layer is fabricated using zirconium-doped hafnium oxide (HZO)-based material. Figure 16As shown, the ferroelectric layer contains both ferroelectric (O phase) and dielectric (M phase) crystal structures, with distinct grain boundaries. Alternatively, it can be understood that the ferroelectric phase crystal structure is not continuously distributed between the first and second electrodes within the ferroelectric layer.

[0105] Figure 17 This is a transmission electron microscope (TEM) image of the cross-section of the ferroelectric layer in an embodiment of this application. The ferroelectric layer is made of zirconium-doped hafnium oxide-based material (Hf). 1-x Zr x The ferroelectric layer was prepared using O2. The transmission electron microscope image shows the cross-sectional structure of the ferroelectric layer along the stacking direction of the first and second electrodes. (See image for details.) Figure 17 As shown, unlike Figure 16 The ferroelectric layer shown in the figure has a continuous ferroelectric phase crystal structure formed in the embodiment of this application. The continuous ferroelectric phase crystal structure extends from the first side to the second side of the ferroelectric layer. There are no grain boundaries between different crystal phases in the ferroelectric phase crystal structure, and there is no layered distribution phenomenon between crystal phases, that is, it has high continuity and integrity.

[0106] For example Figure 17 The ferroelectric layer shown has the following characteristics: Firstly, a continuous and complete ferroelectric phase crystal structure is formed between the first and second sides. This ferroelectric phase crystal structure does not have grain boundaries between different crystal phases, nor does it exhibit layered distribution between crystal phases. This effectively reduces the migration channels of oxygen ions, thereby suppressing oxygen ion migration, reducing the generation of oxygen vacancies, and thus mitigating or even avoiding the aforementioned polarization fatigue, imprinting effect, and breakdown phenomenon, resulting in ferroelectric capacitors having better durability.

[0107] On the other hand, the continuous distribution of the ferroelectric phase crystal structure between the first and second sides of the ferroelectric layer indicates a high initial content of the ferroelectric phase crystal structure, while other phase crystal structures (such as antiferroelectric and dielectric phase crystal structures) have lower initial contents. The higher the initial content of the ferroelectric phase crystal structure in the ferroelectric layer, the better the ferroelectricity of the layer. Alternatively, it can be understood that a higher initial content of the ferroelectric phase crystal structure means a slower increase in the content of the dielectric phase crystal structure during polarization reversal, a slower rate of polarization fatigue, a slower decrease in remanent polarization intensity, and ultimately, a lower degree of polarization fatigue and a higher remanent polarization intensity after a certain number of reversals.

[0108] Figure 18 This is a schematic diagram illustrating the relationship between the polarization intensity and the applied electric field of a ferroelectric capacitor provided in an embodiment of this application. Figure 18As shown, when the applied electric field to the ferroelectric layer is removed, the ferroelectric layer exhibits a high remanent polarization intensity. Furthermore, it retains a high remanent polarization intensity even after a certain number of polarization reversals. Therefore, the ferroelectric memory containing this ferroelectric capacitor can possess robust non-volatility.

[0109] Generally, ferroelectric layers can be formed using element-doped hafnium oxide-based materials. Figure 6 In the ferroelectric layer shown, the concentration of dopants is uniform throughout the ferroelectric layer. Correspondingly, the concentration of hafnium is also uniform throughout the ferroelectric layer. However, such a concentration distribution of dopants (and hafnium) typically results in a random distribution of ferroelectric, antiferroelectric, and dielectric crystal structures formed within the ferroelectric layer.

[0110] In this embodiment, the ferroelectric layer includes a dopant element and a hafnium oxide-based material. The concentration of the dopant element exhibits a first predetermined gradient change along the stacking direction of the first and second electrodes, and correspondingly, the concentration of the hafnium element exhibits a second predetermined gradient change along the same direction. The first and second predetermined gradient changes correspond to each other. For example, if the concentration of the dopant element gradually increases, the concentration of the hafnium element gradually decreases; conversely, if the concentration of the dopant element gradually decreases, the concentration of the hafnium element gradually increases. This predetermined gradient change ensures that the ferroelectric phase crystal structure formed in the ferroelectric layer is continuously distributed between the first and second sides of the ferroelectric layer, even if the ferroelectric phase crystal structure contains almost no other phase crystal structures, and there is no layering distribution between crystal phases. It should be noted that when the concentration of the dopant element in the ferroelectric layer reaches a certain condition, a completely continuous ferroelectric phase crystal structure can be formed in the ferroelectric layer.

[0111] This can be understood as follows: In the embodiments of this application, during the formation of the ferroelectric layer, the concentration distribution of doping elements or hafnium elements in the thickness direction of the ferroelectric layer is controlled to control the crystallization of a continuous ferroelectric phase crystal structure within the ferroelectric layer. For example... Figure 17 The ferroelectric phase crystal structure is shown. (Regarding...) Figure 1 The “MIM” ferroelectric capacitor shown here has the ferroelectric layer thickness direction being the stacking direction of the first and second electrodes. It should be understood that for non-“MIM” ferroelectric capacitors, the ferroelectric layer thickness direction may be other directions.

[0112] In some embodiments, the concentration of the dopant element exhibits the same gradient change from a predetermined position in the ferroelectric layer towards the first and second sides. Correspondingly, the concentration of hafnium also exhibits the same gradient change from the predetermined position in the ferroelectric layer towards the first and second sides. For example, in possible implementations, the concentration of the dopant element gradually increases or decreases from the predetermined position in the ferroelectric layer towards the first and second sides. Correspondingly, the concentration of hafnium also gradually increases or decreases from the predetermined position in the ferroelectric layer towards the first and second sides. Here, the predetermined position refers to a position between the first and second sides. For example, if the distance between the predetermined position and the first electrode in the thickness direction of the ferroelectric layer is called the first distance, and the distance between the predetermined position and the second electrode in the thickness direction of the ferroelectric layer is called the second distance, then the predetermined position can be a position where the first distance and the second distance are equal. Simply put, the predetermined position can be the "midpoint" of the ferroelectric layer in the thickness direction. Based on this, the aforementioned first preset gradient change can be: in the thickness direction of the ferroelectric layer, the concentration of the dopant element gradually increases from the "midpoint position" towards the first side of the ferroelectric layer, and also gradually increases from the "midpoint position" towards the second side of the ferroelectric layer; or, in the thickness direction of the ferroelectric layer, the concentration of the dopant element gradually decreases from the "midpoint position" towards the first side of the ferroelectric layer, and also gradually decreases from the "midpoint position" towards the second side of the ferroelectric layer. Compared to a ferroelectric layer with a uniform distribution of dopant and hafnium concentrations, the element distribution of this application allows the ferroelectric phase crystal structure formed in the ferroelectric layer to be continuously distributed between the first and second sides of the ferroelectric layer as much as possible, so that the ferroelectric phase crystal structure hardly includes other phase crystal structures and does not produce a layered distribution phenomenon between crystal phases.

[0113] In the first possible implementation, the ferroelectric layer is made of zirconium-doped hafnium oxide-based material Hf. 1-x Zr x O2 is formed, where X represents the concentration of zirconium, specifically Hf. 1-x Zr x The number of zirconium atoms in O2 in Hf 1-x Zr x The percentage of zirconium and hafnium atoms in the total number of atoms in O2. Figure 19 The distribution of zirconium element concentration X in the ferroelectric layer is illustrated as an example. Figure 19 It can be visually observed that, along the thickness direction of the ferroelectric layer, the zirconium content gradually decreases from the preset position A towards the first side B of the ferroelectric layer, and from the preset position A towards the second side C of the ferroelectric layer, exhibiting a "downward-opening" curve. In other words, in the region of the ferroelectric layer near the two electrodes, the zirconium content is lower and the hafnium content is higher; in the region of the ferroelectric layer near the center, the zirconium content is higher and the hafnium content is lower.

[0114] exist Figure 19In the implementation shown, the maximum concentration X of zirconium at the preset position is... max The concentration can be between 0.50 and 0.99, and the minimum concentration X on both the first and second sides. min It can be between 0 and 0.50.

[0115] Figure 20 This example illustrates another distribution of zirconium concentration in the ferroelectric layer. (By...) Figure 20 It can be visually observed that, along the thickness direction of the ferroelectric layer, the zirconium content gradually increases from the predetermined position A towards the first side B of the ferroelectric layer, and from the predetermined position A towards the second side B of the ferroelectric layer, exhibiting an upward-opening curve. In other words, in the region of the ferroelectric layer near the two electrodes, the zirconium content is higher and the hafnium content is lower; in the region of the ferroelectric layer near the center, the zirconium content is lower and the hafnium content is higher.

[0116] exist Figure 20 In the implementation shown, the minimum concentration X of zirconium at the preset position is... min The concentration X is between 0 and 0.50, and the maximum concentration is on both the first and second sides. max Between 0.50 and 0.99.

[0117] It should be noted that the above Figure 19 and Figure 20 The zirconium concentration distribution pattern shown is a specific implementation and does not constitute a limitation on the scope of the embodiments of this application. For example, the concentration change of zirconium in the ferroelectric layer along its thickness direction can also be: first increase, then decrease, then increase again, then decrease again, or it can be: first decrease, then increase, then decrease again, then increase again. Furthermore, the concentration change of zirconium in the ferroelectric layer along its thickness direction may not be as shown in the example. Figure 19 and Figure 20 The smooth curves shown are completely consistent. In other words, in specific implementations, the zirconium concentration in the ferroelectric layer can exhibit an overall "opening upward" or "opening downward" curve variation, allowing for a certain degree of concentration fluctuation within a small range. Those skilled in the art can easily conceive of other implementations based on the inventive concept of "controlling the distribution of the ferroelectric phase crystal structure in the ferroelectric layer by controlling the concentration distribution of doping elements in the thickness direction of the ferroelectric layer," without requiring inventive effort. These implementations all fall within the protection scope of this application.

[0118] It should also be noted that, based on the above inventive concept, those skilled in the art will readily conceive of "controlling the distribution of the ferroelectric phase crystal structure in the ferroelectric layer by controlling the concentration distribution of dopant elements in other directions." For example, "other directions" here can be directions perpendicular to the stacking direction of the first and second electrodes. Embodiments derived from such a concept also fall within the protection scope of this application.

[0119] In other embodiments, the ratio of dopant concentration to hafnium concentration exhibits a predetermined gradient along the thickness direction of the ferroelectric layer. More specifically, in the thickness direction of the ferroelectric layer, the ratio of dopant concentration to hafnium concentration exhibits the same gradient from a predetermined position towards both the first and second sides of the ferroelectric layer. For example, the ratio gradually increases from the predetermined position towards the first side of the ferroelectric layer, and also gradually increases from the predetermined position towards the first side of the ferroelectric layer; or, the ratio gradually decreases from the predetermined position towards the first side of the ferroelectric layer, and also gradually decreases from the predetermined position towards the first side of the ferroelectric layer. Unlike the embodiments described above, in these embodiments, the distribution of the ferroelectric phase crystal structure in the ferroelectric layer is controlled by controlling the concentration distribution of the ratio of dopant concentration to hafnium concentration along the thickness direction of the ferroelectric layer.

[0120] Figure 21 This diagram illustrates a concentration distribution of zirconium and hafnium in the ferroelectric layer of this application, obtained using X-ray energy dispersive spectroscopy (EDS). See also... Figure 21 Figure a shows the variation of zirconium concentration X from the first side A to the second side B of the ferroelectric layer, and the variation of hafnium concentration (1-X) from the first side A to the second side B of the ferroelectric layer. It can be seen that, along the thickness direction of the ferroelectric layer, the zirconium concentration X generally exhibits a pattern of first increasing, then decreasing, then increasing again, and finally decreasing again, while the hafnium concentration (1-X) generally exhibits a pattern of first increasing and then decreasing. Furthermore, the concentration variation curves of both zirconium and hafnium are not perfectly smooth; "sawtooth" patterns exist in some local intervals, meaning that a certain degree of concentration fluctuation is permissible within a small range. Figure 21 Figure b shows the variation of the zirconium to hafnium concentration ratio along the thickness of the ferroelectric layer. It can be seen that the ratio initially increases, then decreases, then increases again, and finally decreases again. Ferroelectric layer embodiments based on this variation in the hafnium to zirconium concentration ratio also fall within the scope of this application.

[0121] In this embodiment, the thickness of the first and second electrodes of the ferroelectric layer in the stacking direction is 0.5 nm to 50 nm.

[0122] In summary, this application controls the formation of a ferroelectric phase crystal structure continuously distributed between the first and second sides of the ferroelectric layer by distributing the concentrations of doping elements, hafnium elements, and / or the ratio of their concentrations along the thickness direction or other directions of the ferroelectric layer. This reduces the grain boundary content and the layering phenomenon between crystal phases in the ferroelectric layer, thereby reducing oxygen ion migration channels, suppressing oxygen ion migration, and reducing the generation of oxygen vacancies. This mitigates or even avoids the aforementioned polarization fatigue, imprinting effect, and breakdown phenomena, resulting in better durability of the ferroelectric capacitor. Furthermore, compared to… Figure 5 Regarding the ferroelectric capacitors shown, the ferroelectric capacitors of this application do not have the problem of difficulty in ferroelectric crystallization, and when the thickness of the ferroelectric layer is reduced to 10nm or less, the ferroelectric capacitors can also exhibit good durability and ferroelectricity.

[0123] On the other hand, embodiments of this application provide a method for forming the above-mentioned ferroelectric capacitor. Figure 22 A flowchart illustrating one possible implementation of this formation method is provided. The specific steps are as follows:

[0124] Step S01: A first electrode and a second electrode are formed on one side of the substrate, and the first electrode and the second electrode are stacked.

[0125] Step S02: A ferroelectric layer is formed between the first electrode and the second electrode. The ferroelectric layer includes a dopant element and a hafnium oxide-based material. The concentration of the dopant element varies with a predetermined gradient along the stacking direction of the first and second electrodes. It should be noted that steps S01 and S02 do not limit the order in which the first electrode, the second electrode, and the ferroelectric layer are formed. For example, when fabricating a planar ferroelectric capacitor structure on a substrate, the first electrode, the ferroelectric layer, and the second electrode can be sequentially fabricated on one side of the substrate in a direction perpendicular to the substrate.

[0126] Regarding the materials that can be selected for the first electrode, the ferroelectric layer, and the second electrode during the manufacturing process, please refer to the above description of the structure of the ferroelectric capacitor in this application, which will not be repeated here.

[0127] The method for forming a ferroelectric memory disclosed in this application not only fabricates a first and second electrode for applying voltage and a ferroelectric layer for storing charge, but also ensures that the ferroelectric phase crystal structure formed in the ferroelectric layer is continuously distributed between the first and second sides of the ferroelectric layer, exhibiting a distribution effect that is close to penetrating the ferroelectric layer, or in other words, exhibiting a distribution effect that is close to connecting the first and second electrodes. Even if the ferroelectric phase crystal structure contains almost no other phase crystal structures, there is no layering distribution phenomenon between crystal phases, resulting in relatively high integrity. It should be noted that when the concentration of doping elements in the ferroelectric layer reaches a certain condition, a completely continuous ferroelectric phase crystal structure can be formed in the ferroelectric layer. Such a ferroelectric layer enables the ferroelectric capacitor to have good durability and ferroelectricity. When the thickness of the ferroelectric layer is reduced to 10 nm or less, it also exhibits good ferroelectricity and durability.

[0128] When fabricating the first electrode, second electrode, or ferroelectric layer, magnetron sputtering or thin-film deposition methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) can be used. This ensures that the fabricated first electrode, second electrode, or ferroelectric layer is relatively uniform, has high flatness, and excellent conformability; that is, the shape and surface flatness of each layer are essentially consistent.

[0129] In one implementation, the specific steps for forming the ferroelectric layer are as follows:

[0130] Step S021: Using doped elements and hafnium oxide-based materials, a ferroelectric layer is deposited on the first or second electrode.

[0131] In this process, the concentration of dopants in the ferroelectric layer exhibits a first predetermined gradient change along the stacking direction of the first and second electrodes. Correspondingly, the concentration of hafnium exhibits a second predetermined gradient change along the stacking direction of the first and second electrodes, wherein the first predetermined gradient change corresponds to the second predetermined gradient change.

[0132] During the manufacturing process, the gradient variation of the concentration of doped elements in the ferroelectric layer along the stacking direction of the first and second electrodes can be found in the above description of the ferroelectric capacitor of this application, and will not be repeated here.

[0133] Step S022: The ferroelectric layer deposited in step S021 is crystallized to form a continuous ferroelectric phase crystal structure between the first and second sides of the ferroelectric layer.

[0134] The method for forming a ferroelectric memory disclosed in this application involves controlling the concentration distribution of dopant elements (or hafnium) in the ferroelectric layer. This ensures that the ferroelectric phase crystal structure formed in the ferroelectric layer is continuously distributed between the first and second sides of the ferroelectric layer, resulting in a ferroelectric phase crystal structure that contains almost no other phase crystal structures and avoids the phenomenon of layered distribution between crystal phases. It should be noted that when the concentration distribution of dopant elements in the ferroelectric layer reaches certain conditions, a completely continuous ferroelectric phase crystal structure can be formed in the ferroelectric layer.

[0135] The above-mentioned zirconium-doped hafnium oxide-based material Hf 1-x Zr x Taking O2 as an example, when depositing a ferroelectric layer using CVD, PVD, or ALD deposition methods, the zirconium concentration X can be initially controlled to be high. Then, the concentration X is gradually reduced, and finally, the zirconium concentration X is gradually increased. The final zirconium concentration distribution in the resulting ferroelectric layer is as follows: Figure 20 As shown. Alternatively, the zirconium concentration X is first controlled to be low, then the proportion of concentration X is increased by gradient control, and finally the zirconium concentration X is decreased by gradient control. The final zirconium concentration distribution in the resulting ferroelectric layer is as shown. Figure 19 As shown.

[0136] For example, the ferroelectric layer deposited in step S021 can be crystallized by high-temperature annealing.

[0137] The ferroelectric layer formed by the method provided in this application exhibits a near-through-the-layer distribution of the ferroelectric phase crystal structure, or a near-connection of the first and second electrodes. This can be further understood as the ferroelectric phase crystal structure containing almost no other phase crystal structures and exhibiting no layered distribution between phases, thus possessing relatively high integrity. This reduces oxygen ion migration channels, inhibits oxygen ion migration, reduces oxygen vacancy generation, and mitigates or even avoids polarization fatigue, imprinting effects, and breakdown, resulting in better durability of the ferroelectric capacitor. Furthermore, this distribution of the ferroelectric phase crystal structure implies a higher initial content in the ferroelectric layer, correspondingly lower initial contents of other phase crystal structures (such as antiferroelectric and dielectric phase crystal structures). The higher the content of the ferroelectric phase crystal structure, the slower the increase in dielectric phase crystal structure content during polarization reversal, the slower the rate of polarization fatigue, the slower the decrease in residual polarization intensity, and the lower the degree of polarization fatigue and the greater the residual polarization intensity after a certain number of reversals. Therefore, such a ferroelectric layer has good ferroelectric properties.

[0138] In summary, the ferroelectric capacitor formed using the above method exhibits high capacitance upon removal of the applied electric field (E) on the ferroelectric layer.bias When the polarization is zero, the ferroelectric layer exhibits a high remanent polarization intensity. Even after a certain number of polarization reversals, it still maintains a high remanent polarization intensity. Therefore, the ferroelectric memory containing this ferroelectric capacitor can possess robust non-volatility.

[0139] In some alternative implementations, Figure 22 The ferroelectric capacitor shown can be fabricated using a back-end of line (BEOL) process. Therefore, the control circuit used to control the ferroelectric capacitor can be fabricated on the substrate using a front-end of line (FEOL) process. In other words, the control circuit is first formed on the substrate using a front-end of line process, and then fabricated on the substrate using a back-end of line (BEOL) process. Figure 22 Ferroelectric capacitors are prepared using the method shown.

[0140] Figure 23 A process structure diagram of a memory cell in a ferroelectric field-effect transistor (FeFET) memory is given. The memory cell includes a first doped region 100a and a second doped region 100b formed in a substrate 100, a channel region 100c located between the first doped region 100a and the second doped region 100b, a ferroelectric layer 03 formed on the channel region 100c, and a gate 06 formed on the side of the ferroelectric layer 03 away from the substrate 100.

[0141] In some alternative implementations, substrate 100 may be a semiconductor substrate, such as a P-type silicon substrate.

[0142] In the substrate 100, a first doped region 100a and a second doped region 100b of the same doping type can be formed by a doping process. For example, the first doped region 100a and the second doped region 100b can both be N-type. One of the first doped regions 100a and the second doped region 100b forms the source, and the other doped region forms the drain.

[0143] Figure 23 The material of the ferroelectric layer 03, the crystal phase distribution and elemental distribution in the ferroelectric layer 03 can be found in the above description of the structure of the ferroelectric capacitor of this application, and will not be repeated here.

[0144] In some designs, gate 06 can be made of poly-Si (p-Si, polycrystalline silicon) or a metallic material. When gate 06 is made of a metallic material, Figure 23The structure shown can be called a metal-passivation-ferroelectric-passivation-semiconductor (MPFPS) memory cell structure.

[0145] exist Figure 23 The memory cell shown also includes a word line WL, a bit line BL, and a source line SL. The gate 06 is electrically connected to the word line WL, the first doped region 100a is electrically connected to the bit line BL, and the second doped region 100b is electrically connected to the source line SL.

[0146] Figure 24 It provides the following: Figure 23 The circuit diagram of the memory array 310 shown is shown, and... Figure 23 The memory array 310 shown exemplarily provides four memory cells: memory cell 401, memory cell 402, memory cell 403, and memory cell 404. A word line WL extends along the X direction, and the gates of the plurality of memory cells arranged along the X direction are electrically connected to the same word line WL. A bit line BL extends along the Y direction, perpendicular to the X direction, so that the first doped region 100a of the plurality of memory cells arranged along the Y direction is electrically connected to the same bit line BL. A source line SL extends along the Y direction, perpendicular to the X direction, and the second doped region 100b of the plurality of memory cells arranged along the Y direction is electrically connected to the same source line SL.

[0147] This application also provides a method for forming the above. Figure 23 The method for forming the storage cell shown. Figure 25 A flowchart illustrating one possible implementation of this formation method is provided. The specific steps are as follows:

[0148] Step S11: A first doped region and a second doped region are formed in the substrate, and a ferroelectric layer and a gate are formed on the substrate. The ferroelectric layer is formed on the channel region between the first doped region and the second doped region, and the gate is formed on the side of the ferroelectric layer away from the substrate. The ferroelectric layer includes doping elements and hafnium oxide-based materials.

[0149] Regarding the materials that can be selected for the ferroelectric layer during the manufacturing process, please refer to the above description of the structure of the ferroelectric capacitor in this application, which will not be repeated here.

[0150] During the process, the concentration of dopant elements is controlled to exhibit a predetermined gradient change along the stacking direction of the ferroelectric layer and the gate. For example, the concentration of dopant elements is controlled to exhibit the same gradient change from a predetermined position to a first side closer to the gate and a second side farther away from the gate, where the predetermined position is a location within the ferroelectric layer.

[0151] When forming the gate or ferroelectric layer, magnetron sputtering or thin film deposition methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) can be used.

[0152] Step S12: Anneal the gate and the ferroelectric layer to form a ferroelectric phase crystal structure in the ferroelectric layer, which is continuously distributed between the first side near the gate and the second side away from the gate.

[0153] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0154] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A ferroelectric memory, characterized in that, include: Substrate; Multiple memory cells are formed on the substrate, and each memory cell includes a ferroelectric capacitor; The ferroelectric capacitor includes: Stacked first and second electrodes; A ferroelectric layer is formed between the first electrode and the second electrode, including a first side near the first electrode and a second side near the second electrode; The ferroelectric layer includes doping elements and hafnium oxide-based materials; the concentration of the doping elements varies with a preset gradient along the stacking direction of the first electrode and the second electrode; based on the preset gradient variation, a continuous ferroelectric phase crystal structure is formed in the ferroelectric layer, and the continuous ferroelectric phase crystal structure extends from the first side to the second side.

2. The ferroelectric memory according to claim 1, characterized in that, The preset gradient change includes: the concentration of the doped element exhibits the same gradient change from a preset position in the ferroelectric layer to the first side and the second side.

3. The ferroelectric memory according to claim 2, characterized in that, The preset gradient change includes: the concentration of the dopant element gradually increases or gradually decreases from the preset position toward the first side and the second side.

4. The ferroelectric memory according to claim 2, characterized in that, The ferroelectric layer is made of zirconium-doped hafnium oxide-based material Hf. 1-x Zr x O2 is formed, wherein X represents the concentration of the zirconium element; When the concentration of zirconium gradually increases from a predetermined position in the ferroelectric layer towards the first and second sides, the minimum concentration X of zirconium at the predetermined position is... min The concentration X is between 0 and 0.50, and is the maximum concentration on both the first and second sides. max Between 0.50 and 0.99; When the concentration of zirconium gradually decreases from the preset position towards the first side and the second side, the maximum concentration X of zirconium at the preset position is... max The minimum concentration X is between 0.50 and 0.99 on both the first and second sides. min Between 0 and 0.

50.

5. The ferroelectric memory according to claim 1, characterized in that, The ferroelectric layer includes doping elements and hafnium oxide-based materials; the ratio of the concentration of the doping elements to the concentration of hafnium elements exhibits a predetermined gradient change along the stacking direction of the first electrode and the second electrode.

6. The ferroelectric memory according to any one of claims 1-5, characterized in that, The ferroelectric layer has a residual polarization intensity greater than a preset value, where the preset value is greater than zero.

7. The ferroelectric memory according to any one of claims 1-5, characterized in that, The thickness of the ferroelectric layer in the stacking direction of the first electrode and the second electrode is 0.5 nm-50 nm.

8. A method for forming a ferroelectric memory, characterized in that, include: A first electrode and a second electrode are formed on one side of the substrate, and the first electrode and the second electrode are stacked. A ferroelectric layer is formed between the first electrode and the second electrode. The ferroelectric layer includes a dopant element and a hafnium oxide-based material. The ferroelectric layer includes a first side near the first electrode and a second side near the second electrode. The concentration of the dopant element exhibits a predetermined gradient change in the stacking direction of the first electrode and the second electrode. Based on the preset gradient change, a continuous ferroelectric phase crystal structure is formed in the ferroelectric layer, and the continuous ferroelectric phase crystal structure extends from the first side to the second side.

9. The method for forming a ferroelectric memory according to claim 8, characterized in that, Forming a ferroelectric layer between the first electrode and the second electrode includes: A ferroelectric layer is deposited on the first electrode or the second electrode using doped elements and hafnium oxide-based materials; The ferroelectric layer is subjected to crystallization treatment.

10. An electronic device, characterized in that, include: processor; and The ferroelectric memory as described in any one of claims 1-7 or the ferroelectric memory as described in any one of claims 8-9, is obtained by the method of forming the ferroelectric memory. The processor and the ferroelectric memory are electrically connected.

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