A matrix bus-based cable network insulation withstand voltage detection method and device

Abstract

The application discloses a kind of cable network insulation withstand voltage detection method and device based on matrix bus, the method comprises: any multicore connector is connected distribution in a m*n matrix, each core point is configured two switches, and it is switched to be connected to row bus Ym and column bus Xn;Each superimposes an auxiliary matrix on the matrix row and column, and connects the bus core point to insulation withstand voltage test equipment;The row direction and column direction of m*n matrix are respectively divided by dichotomy multiple times, and the insulation withstand voltage between row bus matrix and row bus matrix core point is tested, and the insulation withstand voltage between column bus matrix and column bus matrix core point is tested.The purpose of the application is to complete the insulation withstand voltage of multicore cable network fast detection, can eliminate heavy manual test work, improve detection efficiency, shorten test time.

Description

Technical Field

[0001] This invention relates to the field of insulation testing technology, and in particular to a method and apparatus for testing the insulation withstand voltage of cable networks based on a matrix bus. Background Technology

[0002] With the continuous development of rocket control theory and technology, the scale and complexity of its electrical system have also increased. As an important component, the onboard and ground cable network is responsible for transmitting control signals, data and energy. Its effectiveness and reliability directly determine whether the entire system can operate stably. Therefore, insulation withstand voltage tests are required for the cable network.

[0003] Current testing methods mainly involve manual point-by-point testing, which is suitable for cables with simple connections, but it is time-consuming, labor-intensive, and carries the risk of electric shock when testing cable networks with large electrical systems and hundreds of connector points. Summary of the Invention

[0004] This invention provides a method for testing the insulation withstand voltage of a cable network based on a matrix bus, comprising:

[0005] Assign any multi-core connector connection to an m*n matrix, with each core configured with two switches to switch it to the row bus Ym and column bus Xn;

[0006] An auxiliary matrix is ​​superimposed on each of the matrix rows and columns to connect the bus core points to the insulation withstand voltage test equipment;

[0007] For an m*n matrix, perform multiple bisections along both the row and column directions using the bisection method, and then test. Row bus matrix and Insulation withstand voltage between row bus matrix cores, and testing Column bus matrix and Insulation withstand voltage between core points of the column bus matrix;

[0008] If all tests pass, the test is considered complete; if all tests fail, the results are recorded; if either the row insulation withstand voltage or the column insulation withstand voltage fails, the insulation withstand voltage between any row or column core wires is tested to find the non-conforming core wire.

[0009] The above-described method for testing the insulation withstand voltage of a cable network based on a matrix bus includes a distribution of core points that is either full rows and columns, full rows but not full columns, or full columns but not full rows.

[0010] The above-described method for testing the insulation withstand voltage of cable networks based on a matrix bus includes an auxiliary matrix that connects single-row, multi-row, single-column, or multi-column bus cores to the insulation withstand voltage testing equipment.

[0011] The above-mentioned insulation withstand voltage testing method for cable networks based on matrix buses, wherein the row direction and the column direction of the m*n matrix are respectively subjected to multiple bisection operations through a dichotomy, and the total number of times required for the matrix to be bisected into a single row and a single column is accumulated, which is the number of insulation withstand voltage tests required to complete the insulation withstand voltage test of the connector.

[0012] The above-mentioned insulation withstand voltage testing method for cable networks based on matrix buses, wherein the rapid insulation withstand voltage testing method specifically includes the following sub-steps:

[0013] A. Testing the insulation withstand voltage between the core points of the row bus matrix and the core points of the row bus matrix;

[0014] B. Testing the insulation withstand voltage between the core points of the column bus matrix and the core points of the column bus matrix;

[0015] C. Performing test analysis according to the test results.

[0016] The above-mentioned insulation withstand voltage testing method for cable networks based on matrix buses, wherein if both the tests of A and B are passed, the test result is qualified.

[0017] The above-mentioned insulation withstand voltage testing method for cable networks based on matrix buses, wherein if the test A is passed and the test B is not passed, the insulation withstand voltage between any two column bus core wires is additionally tested. When the test of the XM column and the XN column fails, the insulation withstand voltage test is performed between the j-th core wire in the XM column and the j-th core wire in the XN column, where j=1, 2, 3...n, to find the unqualified core wire.

[0018] The above-mentioned insulation withstand voltage testing method for cable networks based on matrix buses, wherein if the test A is not passed and the test B is passed, the insulation withstand voltage between any two row bus core wires is additionally tested. When the test of the YJ row and the YK row fails, the insulation withstand voltage test is performed between the i-th core wire in the YJ row and the i-th core wire in the YK row, where i=1, 2, 3...n, to find the unqualified core wire.

[0019] The above-mentioned insulation withstand voltage testing method for cable networks based on matrix buses, wherein if both the tests of A and B are not passed, the insulation withstand voltage between any two column bus core wires is additionally tested, and the insulation withstand voltage between any two row bus core wires is additionally tested. If the test of the YJ row and the YK row fails and the test of the XM column and the XN column fails, the insulation withstand voltage test is performed between the core wire at the M-th column of the YJ row and the core wire at the N-th column of the YK row, as well as between the core wire at the N-th column of the YJ row and the core wire at the M-th column of the YK row, where M≠N, to find the unqualified core wire.

[0020] The present invention also provides a cable network insulation withstand voltage testing device based on a matrix bus, comprising: the testing device being connected to any multi-core connector, and the testing device performing a cable network insulation withstand voltage testing method based on a matrix bus as described above.

[0021] The beneficial effects achieved by this invention are as follows: The purpose of this invention is to propose a rapid testing method for the insulation withstand voltage of cable networks based on matrix bus technology, which can complete the rapid testing of the insulation withstand voltage of multi-core cable networks, eliminate the heavy manual testing work, improve testing efficiency, and shorten testing time. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0023] Figure 1 This is a flowchart of a rapid test method for cable network insulation withstand voltage based on matrix bus technology provided in Embodiment 1 of the present invention;

[0024] Figure 2 This is a schematic diagram of the matrix bus distribution;

[0025] Figure 3 This is a flowchart of a rapid insulation withstand voltage testing method;

[0026] Figure 4 This example demonstrates how 64-pin connector cores are distributed in an 8x8 matrix. Row bus matrix and A schematic diagram illustrating the selection of the row bus matrix;

[0027] Figure 5 It corresponds Figure 4 Schematic diagram of insulation withstand voltage test analysis;

[0028] Figure 6 This example demonstrates how 64-pin connector cores are distributed in an 8x8 matrix. Column bus matrix and A schematic diagram illustrating the selection of the column bus matrix;

[0029] Figure 7 It corresponds Figure 6 A schematic diagram of the insulation withstand voltage test analysis. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] Example 1

[0032] like Figure 1 As shown, Embodiment 1 of the present invention provides a rapid testing method for cable network insulation withstand voltage based on matrix bus technology. Based on rapid testing, most inter-core insulation is found to be good. The method includes:

[0033] Step 110: Assign any multi-core connector connection to an m*n matrix, configuring two switches for each core point, and switching them to connect to the row bus Y. m and column bus X n superior.

[0034] The multi-core connectors are connected and distributed in an m*n matrix, and the matrix bus is distributed as follows: Figure 2 As shown, the distribution of the core points can be either full rows but not full columns or full columns but not full rows, which does not affect the test results.

[0035] Step 120: Overlay an auxiliary matrix on each of the matrix rows and columns, and connect the bus core point to the insulation withstand voltage test equipment.

[0036] In this embodiment, the auxiliary matrix can connect single-row, multi-row, single-column, or multi-column bus core points to the insulation withstand voltage test equipment.

[0037] Step 130: For an m*n matrix, perform multiple bisections along both the row and column directions using the bisection method, and test the results. Row bus matrix and Insulation withstand voltage between row bus matrix cores, and testing Column bus matrix and Insulation withstand voltage between core points of the column bus matrix.

[0038] The m*n matrix is ​​bisected multiple times in both the row and column directions using the bisection method. The total number of times the matrix is ​​bisected into a single row and a single column is accumulated to determine the number of insulation withstand voltage tests required to complete the insulation withstand voltage test of the connector.

[0039] Step 140: If all tests pass, the test is considered complete; if all tests fail, a record is made; if either the row insulation withstand voltage or the column insulation withstand voltage fails, the insulation withstand voltage between any row or column core wires is tested to find the unqualified core wire.

[0040] Specifically, such as Figure 3 As shown, the rapid insulation withstand voltage testing method specifically includes the following sub-steps:

[0041] Step 310, Test Row bus matrix and Insulation withstand voltage between the core points of the row bus matrix;

[0042] Step 320, Test Column bus matrix and Insulation withstand voltage between core points of the column bus matrix;

[0043] in, Row bus matrix and Selection principle of row bus matrix: Randomly select one row of bus core points from each of the two matrices mentioned above, and perform insulation withstand voltage test between each pair of rows of buses; Column bus matrix and Selection principle of column bus matrix: Randomly select one column of bus core points from each of the two matrices mentioned above, and perform insulation withstand voltage test between each pair of bus columns.

[0044] Step 330: Analyze the test results.

[0045] If both steps 310 and 320 pass the test, then the test result is qualified.

[0046] If test 310 passes but test 320 fails, then an additional insulation withstand voltage test is performed between any two columns of bus cores. When X M Columns and X N If the column test fails, then X... M The j-th core and X in the column N Insulation withstand voltage test is performed between the j-th core wires in the column, j = 1, 2, 3...n, to find the unqualified core wires;

[0047] If test 310 fails but test 320 passes, then an additional insulation withstand voltage test is performed between any two rows of bus core wires. J line and Y K If the test fails, then for Y... J The i-th core line and Y in the row K Insulation withstand voltage test is performed between the i-th core wires in the row, i = 1, 2, 3...n, to find the unqualified core wires;

[0048] If both tests in steps 310 and 320 fail, additional tests are performed on the insulation withstand voltage between any two columns of bus core wires and between any two rows of bus core wires. If Y J line and Y K The test failed and X M Columns and XN If the column test fails, then for Y... J The core wire in the Mth column and Y K The core wire in the Nth column and Y J The core wire in the Nth column and Y K Perform an insulation withstand voltage test between the core wires in row M and column M, where M ≠ N, and identify any unqualified core wires.

[0049] The following uses the insulation withstand voltage test of a 64-core connector cable network as an example to illustrate the test method of this invention:

[0050] Conventional testing of a 64-core connector requires 2080 tests. In the testing method of this invention, the core wires of the 64-core connector can be distributed in an 8×8 matrix. Dividing the 8 rows into a single row requires 3 tests, and dividing the 8 columns into a single column requires 3 tests. That is, three row-to-row insulation withstand voltage tests and three column-to-column insulation withstand voltage tests are performed.

[0051] The specific testing process is as follows:

[0052] A. Test Row bus matrix and If the insulation withstand voltage test between the core points of the row bus matrix fails, it should be recorded.

[0053] Figure 4 The 64-core connector cores are distributed in an 8*8 matrix, with row numbers Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 and column numbers X1, X2, X3, X4, X5, X6, X7, X8. Row bus matrix and The row bus matrix is ​​selected as follows:

[0054] First group of tests: selected The row bus matrix has row indices Y1, Y2, Y3, and Y4, and the selected... The row bus matrix has row indices Y5, Y6, Y7, and Y8;

[0055] Second group of tests: selected The row bus matrix has row indices Y1, Y2, Y5, and Y6, and the selected... The row bus matrix has row indices Y3, Y4, Y7, and Y8;

[0056] Third group of tests: selected The row bus matrix has row indices Y1, Y3, Y5, and Y7, and the selected... The row bus matrix has row indices Y2, Y4, Y6, and Y8.

[0057] Only three row tests are needed to cover the insulation withstand voltage test of any two rows of core wires, and the analysis can be performed as follows: Figure 5As shown in the figure, the solid lines connect the test cases between each pair of the 8 rows, which can all be covered, while the dashed lines connect the repeated tests, which do not affect the test results.

[0058] B. Test Column bus matrix and If the insulation withstand voltage test between the core points of the column bus matrix fails, it should be recorded.

[0059] Column bus matrix and The selection of the column bus matrix is ​​as follows: Figure 6 As shown (n=8, k=4):

[0060] First group of tests: selected The column bus matrix is ​​defined by column indices X1, X2, X3, and X4. The column bus matrix has row indices X5, X6, X7, and X8;

[0061] Second group of tests: selected The column bus matrix is ​​defined by column indices X1, X2, X5, and X6. The column bus matrix has row indices X3, X4, X7, and X8;

[0062] Third group of tests: selected The column bus matrix has column indices X1, X3, X5, and X7, and the selected... The column bus matrix has matrix row indices X2, X3, X4, and X8.

[0063] Only three column tests are needed to cover the insulation withstand voltage test of any two columns of core wires, and the analysis can be performed as follows: Figure 7 As shown in the figure, the solid lines connect the test cases between each pair of the 8 columns, which can all be covered, while the dashed lines connect the repeated tests, which do not affect the test results.

[0064] If steps A and B pass the test, only six insulation withstand voltage tests are needed to complete the insulation withstand voltage test of the 64-pin connector, which greatly improves the testing efficiency and shortens the testing time.

[0065] If step A fails but step B succeeds, it indicates that there is a fault point between rows. Then, step C is added to test and locate the faulty row accurately. If it is determined that the tests of rows Y1 and Y2 fail, an insulation withstand voltage test is performed between the i-th core wire in row Y1 and the i-th core wire in row Y2, i = 1, 2, 3... n, to find the unqualified core wire.

[0066] If step A passes but step B fails, it indicates that there is a fault point between columns. Then, step D is added to test and locate the faulty column. If it is determined that the tests of columns X2 and X3 fail, an insulation withstand voltage test is performed between the j-th core wire in column X2 and the j-th core wire in column X3, j = 1, 2, 3...n, to find the unqualified core wire.

[0067] If steps A and B fail, it indicates a fault exists between diagonal points in the rows and columns. Steps C and D are then added. If it is determined that the tests for rows Y1 and Y4 fail and the tests for columns X2 and X3 fail, insulation withstand voltage tests are then performed between the core wires in the second column of row Y1 and the third column of row Y4, as well as between the core wires in the third column of row Y1 and the second column of row Y4, to identify the unqualified core wires.

[0068] Corresponding to the above embodiments, this embodiment of the invention provides a cable network insulation withstand voltage testing device based on a matrix bus, comprising: at least one memory and at least one processor;

[0069] The memory is used to store one or more program instructions;

[0070] A processor is used to run one or more program instructions to execute a matrix bus-based cable network insulation withstand voltage testing method.

[0071] Corresponding to the above embodiments, this embodiment of the invention provides a computer-readable storage medium containing one or more program instructions, which are executed by a processor to provide a method for testing the insulation withstand voltage of a cable network based on a matrix bus.

[0072] The embodiments disclosed in this invention provide a computer-readable storage medium storing computer program instructions. When the computer program instructions are executed on a computer, the computer performs the above-described method for testing the insulation withstand voltage of a cable network based on a matrix bus.

[0073] In this embodiment of the invention, the processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0074] The various methods, steps, and logic diagrams disclosed in the embodiments of this invention can be implemented or executed. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this invention can be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The processor reads information from the storage medium and, in conjunction with its hardware, completes the steps of the above methods.

[0075] The storage medium can be memory, such as volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.

[0076] Among them, non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory.

[0077] Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (Synchlink DRAM, SLDRAM), and direct memory bus RAM (DRRAM).

[0078] The storage media described in the embodiments of the present invention are intended to include, but are not limited to, these and any other suitable types of memory.

[0079] Those skilled in the art will recognize that, in one or more of the examples above, the functions described in this invention can be implemented using a combination of hardware and software. When applied as software, the corresponding functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transmission of computer programs from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0080] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for testing the insulation withstand voltage of a cable network based on a matrix bus, characterized in that, include: Assign any multi-core connector connection to one m n In the matrix, the core points are distributed as full rows and columns, full rows but not full columns, or full columns but not full rows, and each core point is configured with two switches to connect it to the row bus. Y m and column bus X n superior; An auxiliary matrix is ​​superimposed on each of the rows and columns of the matrix. The auxiliary matrix connects the single-row, multi-row, single-column, or multi-column bus core points to the insulation withstand voltage test equipment. for m n The matrix is ​​processed by the bisection method. m n The matrix is ​​subjected to multiple binary divisions along both the row and column directions. The total number of binary divisions required for each row and column is summed to determine the number of insulation withstand voltage tests required to complete the insulation withstand voltage test for this connector. Row bus matrix and Insulation withstand voltage between row bus matrix cores, and testing Column bus matrix and Insulation withstand voltage between core points of the column bus matrix; If all tests pass, the test is considered complete. If all tests fail, record the failure. If either the row insulation withstand voltage or the column insulation withstand voltage fails, perform insulation withstand voltage tests on the core wires of any row or column to find the non-conforming core wire.

2. The cable network insulation withstand voltage testing method based on matrix bus as described in claim 1, characterized in that, The rapid insulation withstand voltage test method includes the following sub-steps: A. Test Row bus matrix and Insulation withstand voltage between the core points of the row bus matrix; B. Test Column bus matrix and Insulation withstand voltage between core points of the column bus matrix; C. Conduct test analysis based on the test results.

3. The cable network insulation withstand voltage testing method based on a matrix bus as described in claim 2, characterized in that, If both A and B pass the tests, then the test result is acceptable.

4. The cable network insulation withstand voltage testing method based on a matrix bus as described in claim 2, characterized in that, If test A passes and test B fails, then an additional test is performed on the insulation withstand voltage between any two columns of bus cores. When X M Columns and X N If the column test fails, then X... M The j-th core and X in the column N Insulation withstand voltage test is performed between the j-th core wires in the column, j=1,2,3……n, to find the unqualified core wires.

5. The cable network insulation withstand voltage testing method based on a matrix bus as described in claim 2, characterized in that, If test A fails but test B passes, then an additional test is performed on the insulation withstand voltage between any two rows of bus conductors. Y J lines and Y K If the test fails, then... Y J In the middle of the line i Core wire and Y K In the middle of the line i Insulation withstand voltage tests are performed between the core wires, i=1,2,3……n, to identify unqualified core wires.

6. The cable network insulation withstand voltage testing method based on matrix bus as described in claim 2, characterized in that, If tests A and B both fail, then additional tests will be conducted on the insulation withstand voltage between any two columns of bus core wires, and additional tests will be conducted on the insulation withstand voltage between any two rows of bus core wires. Y J lines and Y K The test failed and X M column sum X N If the column test fails, then... Y J Line 1 M Core wire and Y K Line 1 N Core wire and Y J Line 1 N Core wire and Y K Line 1 M Insulation withstand voltage test is performed between the core wires. M ≠ N They searched for substandard core wires.

7. A cable network insulation withstand voltage testing device based on a matrix bus, characterized in that, include: The testing device is connected to any multi-core connector, and the testing device performs a cable network insulation withstand voltage testing method based on a matrix bus as described in any one of claims 1-6.

Images