Forward-based high-fidelity extended target real-time simulation method and system
By employing a forwarding method and multi-channel parallel processing technology, the problems of insufficient realism and real-time performance in radar target echo simulation are solved, achieving extended target echo simulation with high realism and real-time performance. This method is applicable to radar system research, development, debugging, and electronic countermeasures.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HANGZHOU DIANZI UNIV
- Filing Date
- 2023-06-21
- Publication Date
- 2026-06-30
AI Technical Summary
Existing radar target echo simulation technologies suffer from low fidelity and poor real-time performance, making it difficult to achieve real-time simulation of highly realistic extended targets.
The method employs a repeater approach, which involves receiving, down-converting, high-speed acquisition, FPGA signal processing, digital-to-analog conversion, and up-conversion. It utilizes multi-channel parallel processing to detect radar signals and extend the amplitude, Doppler frequency, and delay modulation of target echo signals. In particular, it employs a multi-channel parallel convolution structure for high-speed convolution operations.
It achieves extended target echo simulation with higher fidelity and better real-time performance, and can clearly distinguish targets as small as 0.125m after pulse compression, shortening the R&D cycle and saving costs.
Smart Images
Figure CN117111001B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of radar target echo simulation technology, and specifically relates to a transponder-based high-fidelity extended target real-time simulation method and system. Background Technology
[0002] With the rapid development of radar theory and technology and the continuous improvement of radar resolution, radar target echo simulation technology has gradually evolved from "point" target echo simulation technology to extended target echo simulation technology. Extended target echo simulation technology is a technique that considers the target echo as the sum of echoes from some scattered points, thus more closely resembling the real radar target echo.
[0003] Extended target echo simulation technology plays an irreplaceable role in radar system testing and electronic warfare. In radar system testing, it is primarily used for research, development, debugging, and verification, saving development costs and shortening the development cycle. In electronic warfare, it simulates various characteristics of extended targets, generating realistic false targets or clusters of false targets by intercepting and modulating radar transmission signals, thus deceiving enemy radar. However, extended target echo simulation is more complex than traditional point target echo simulation, and its real-time performance and realism are not particularly ideal.
[0004] Therefore, how to achieve a high-fidelity real-time simulation system for extended targets has become an urgent problem to be solved in this field. Summary of the Invention
[0005] To address the aforementioned problems, this invention provides a forward-relay high-fidelity extended target real-time simulation method and system to overcome the issues of low fidelity and poor real-time performance in existing radar target echo simulation technologies.
[0006] To achieve the above objectives, the present invention adopts the following technical solution:
[0007] A forward-redirecting, high-fidelity, real-time simulation method for extended targets includes the following steps:
[0008] S1. The receiving antenna receives the radar transmitted signal, and then the radio frequency down-conversion module converts the received radar transmitted signal into an intermediate frequency signal.
[0009] S2, the high-speed signal acquisition module performs high-speed acquisition of the intermediate frequency signal after RF downconversion, realizing the conversion from analog signal to digital signal, and the digital signal is converted from serial to parallel to obtain 8 parallel digital signal outputs;
[0010] S3, the FPGA signal processing module detects, stores, and modulates 8 parallel digital signals to obtain the extended target echo signal;
[0011] S4. The high-speed digital-to-analog converter module performs parallel-to-serial conversion on the extended target echo signal, changing it from 8-channel signal to 1-channel signal, and then converts it from digital signal to analog signal through digital-to-analog conversion.
[0012] S5. The radio frequency upconversion module upconverts the analog signal after digital-to-analog conversion to convert it from an intermediate frequency signal to a radio frequency signal, which is then transmitted through the transmitting antenna.
[0013] As a preferred embodiment, step S3 specifically includes:
[0014] (1) 8-channel parallel Hilbert transform: The digital signal after high-speed signal acquisition is transformed into a complex signal by performing an 8-channel parallel Hilbert transform.
[0015] (2) Envelope detection and setting pulse flag: First, calculate the envelope of the complex signal. Then, reduce the influence of noise by using the sliding window averaging method of the parallel structure. Then, obtain the changing characteristics of the rising and falling edges of the radar pulse signal by the first and second difference methods of the parallel structure. Finally, set the pulse flag by using the changing characteristics of the rising and falling edges of the radar pulse signal, so as to achieve the purpose of storing a complete radar pulse signal.
[0016] (3) The digital memory stores the delayed complex signal according to the pulse flag bit, and then performs 8-channel delay modulation. That is, after the set time is reached, the stored signal is read out, thereby realizing the delay modulation of the signal.
[0017] (4) 8-channel parallel Doppler frequency modulation: The complex signal and the complex Doppler frequency signal are multiplied in 8-channel parallel complex multiplication by a complex multiplier to realize the Doppler frequency modulation of the signal.
[0018] (5) The 8-channel parallel convolution modulation operation performs 8-channel parallel convolution on the sum of the signal after delay and Doppler frequency modulation and the impulse response function containing amplitude information and distance information between scattering points to obtain the extended target echo signal.
[0019] As a preferred embodiment, the specific process in step (1) is as follows: The filter coefficients of the Hilbert transform filter are obtained through simulation. The Hilbert transform filter is essentially an all-pass filter with an amplitude-frequency characteristic of 1, and its frequency response is:
[0020]
[0021] In the formula, ω represents the frequency; verify whether the Hilbert transform filter in the simulation is consistent with the set function. If it meets the requirements, the filter coefficients are exported, quantized and loaded into the FIR filter. The FIR filter after loading the filter coefficients will transform the real signal into a complex signal.
[0022] As a preferred embodiment, the specific process in step (2) is as follows: calculate the envelope B(n) of the complex signal output by the Hilbert transform filter, that is, perform modulo operation on the complex signal; obtain the smoothed sample points by means of the sliding window averaging method. Assuming the sliding window length is L and the total number of sample points in the envelope is N, then the i-th sample sequence can be written as:
[0023]
[0024] The i-th envelope-smoothed sample value for:
[0025]
[0026] The obtained N envelope smoothed sample values are used to replace the N envelope sample values without sliding window. Then, a difference processing C1(n) = A(n+1) - A(n) and a difference processing C2(n) = C1(n+1) - C1(n) are performed on the N envelope smoothed sample values. The characteristics of the rising and falling edges of the pulse signal are obtained. Since the radar signal is transmitted in 8 parallel channels, the calculation of the radar signal envelope, the sliding window averaging method, the first difference method, and the second difference method are all in parallel. Finally, the pulse flag is set according to the changes of the rising and falling edges of the radar pulse signal.
[0027] As a preferred embodiment, the specific process in step (3) is as follows: delay the complex signal until it is aligned with the pulse flag bit, and store the delayed complex signal in the digital memory according to the pulse flag bit; calculate the corresponding delay of the signal in the digital memory according to the radial distance between the target and the radar, and then convert the delay into the required number of clock cycles according to the FPGA system clock; if the radial distance between the target and the radar is R, and the FPGA system clock frequency is f s Then the data rate after M signals are parallelized is M×f s The corresponding clock cycle count is
[0028] In a further preferred embodiment, the number of parallel channels used is M=8. After the clock cycle counts to the required number, the signal in the digital memory is read out in parallel through 8 channels, thereby realizing the delay modulation of the signal.
[0029] As a preferred embodiment, the specific process in step (4) is as follows: calculate the corresponding frequency control word K based on the Doppler frequency, assuming the bit width of the phase accumulator is P and the Doppler frequency is f. d The data rate after M signals are parallelized is M×f s Then the formula for calculating the frequency control word is K = (f d / (M×fs ))×2 P Complex Doppler frequency signals are generated by a direct digital frequency synthesizer (DDS) with a frequency control word.
[0030] In a further preferred embodiment, the number of parallel paths is M=8, and the complex Doppler frequency signal and the complex signal are subjected to 8-way parallel complex multiplication operations to realize the Doppler frequency modulation of the signal.
[0031] As a preferred option, the specific process in step (5) is as follows: each scattering point corresponds to an impulse response function containing amplitude information and distance information between scattering points. The impulse response functions corresponding to all scattering points of the extended target to be simulated are added together. The signal after delay and Doppler frequency modulation is combined with the sum of the impulse response functions and then subjected to 8-way parallel convolution operation. The result of the operation is the extended target echo signal.
[0032] This invention also discloses a forwarding-based high-fidelity extended target real-time simulation system, comprising the following modules:
[0033] The radio frequency downconversion module receives radar transmitted signals through a receiving antenna, converts the received radar transmitted signals into intermediate frequency signals, and sends them to the high-speed signal acquisition module.
[0034] The high-speed signal acquisition module acquires intermediate frequency signals at high speed, converts analog signals into digital signals, and then performs serial-to-parallel conversion on the digital signals to obtain 8 parallel digital signal outputs.
[0035] The FPGA signal processing module detects, stores, and modulates the eight parallel digital signals input to obtain the extended target echo signal, which is then input into the high-speed digital-to-analog converter module.
[0036] The high-speed digital-to-analog converter module first converts the extended target echo signal from parallel to serial to meet the requirements of high-speed digital-to-analog conversion, and then performs digital-to-analog conversion to convert the digital signal into an analog signal.
[0037] The radio frequency upconversion module upconverts the analog signal obtained from the high-speed digital-to-analog converter module, converting the intermediate frequency signal into a radio frequency signal, which is then transmitted through the transmitting antenna.
[0038] Preferably, the FPGA signal processing module specifically includes the following sub-modules:
[0039] 8-channel parallel Hilbert transform submodule: Performs 8-channel parallel Hilbert transform on the digital signal after high-speed signal acquisition, transforming the real signal into a complex signal;
[0040] Digital envelope detection and pulse flag setting submodule: Envelope detection and pulse flag setting first calculates the envelope of the complex signal, weakens the influence of noise by using the sliding window averaging method of parallel structure, and then obtains the changing characteristics of the rising and falling edges of the radar pulse signal by the first and second difference methods of parallel structure. Finally, the pulse flag is set by the changing characteristics of the rising and falling edges of the radar pulse signal, thereby achieving the purpose of storing a complete radar pulse signal.
[0041] Digital memory signal storage and delay submodule: The digital memory stores the complex signal that has been delayed to the alignment with the flag bit according to the pulse flag bit, and then performs 8-channel delay modulation. That is, after the set time is reached, the stored signal is read out, thereby realizing the delay modulation of the signal.
[0042] 8-channel parallel Doppler frequency modulation submodule: The 8-channel parallel Doppler frequency modulation uses a complex multiplier to perform 8-channel parallel complex multiplication of the complex signal and the complex Doppler frequency signal to achieve Doppler frequency modulation of the signal.
[0043] The 8-channel parallel convolution operation submodule: The 8-channel parallel convolution modulation operation performs 8-channel parallel convolution operations on the signal after delay and Doppler frequency modulation and the sum of the impulse response functions corresponding to multiple scattering points containing amplitude information and distance information between scattering points, to obtain the extended target echo signal.
[0044] This invention provides a high-fidelity real-time simulation system for extended targets using a repeater-based approach. Compared to traditional radar target echo simulation systems, this invention leverages the principle of "trading area for speed" by employing a multi-path parallel processing approach to detect radar signals and perform amplitude modulation, Doppler frequency modulation, and delay modulation of the extended target echo signal. The most critical step in the modulation process of the extended target echo signal is the convolution operation. This invention utilizes a multi-path parallel convolution structure to achieve high-speed convolution of the delayed, Doppler frequency modulated signal with the total impulse response function at high data rates.
[0045] In a preferred embodiment of the present invention, the FPGA system clock frequency is 300MHz, and the 8-channel signal merging enables a real-time target simulation algorithm with a data rate of up to 2.4GHz, allowing the extended target echo signal to clearly distinguish two targets at a distance of 0.125m in the pulse-compressed one-dimensional range image. Therefore, the system using the present invention can achieve extended target echo simulation with better real-time performance and higher fidelity. Attached Figure Description
[0046] To illustrate the technical solutions of this invention more intuitively and clearly, the accompanying drawings used in the embodiments will be briefly introduced below.
[0047] Figure 1 This is a block diagram illustrating the principle of the forwarding-type high-fidelity extended target real-time simulation system of the present invention.
[0048] Figure 2 This is a block diagram of the FPGA signal processing module in the forward-redirecting high-fidelity extended target real-time simulation system of the present invention.
[0049] Figure 3 This is the time-domain implementation structure of the 8-channel parallel convolution operation in the FPGA signal processing module of the present invention. Detailed Implementation
[0050] To better understand the technical content of this invention, the invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
[0051] Please see Figure 1 The diagram shown is an overall flowchart of the forwarding-based high-fidelity extended target real-time simulation system in this embodiment.
[0052] This embodiment of the forwarding-type high-fidelity extended target real-time simulation system includes the following modules:
[0053] The radio frequency downconversion module receives radar transmitted signals through a receiving antenna, converts the received radar transmitted signals into intermediate frequency signals, and sends them to the high-speed signal acquisition module.
[0054] The high-speed signal acquisition module acquires intermediate frequency signals at high speed, converts analog signals into digital signals, and then performs serial-to-parallel conversion on the digital signals to obtain 8 parallel digital signal outputs.
[0055] The FPGA signal processing module detects, stores, and modulates the eight parallel digital signals input to obtain the extended target echo signal, which is then input into the high-speed digital-to-analog converter module.
[0056] The high-speed digital-to-analog converter module first converts the extended target echo signal from parallel to serial to meet the requirements of high-speed digital-to-analog conversion, and then performs digital-to-analog conversion to convert the digital signal into an analog signal.
[0057] The radio frequency upconversion module upconverts the analog signal obtained from the high-speed digital-to-analog converter module, converting the intermediate frequency signal into a radio frequency signal, which is then transmitted through the transmitting antenna.
[0058] In this embodiment, the FPGA signal processing module specifically includes the following sub-modules:
[0059] 8-channel parallel Hilbert transform submodule: Performs 8-channel parallel Hilbert transform on the digital signal after high-speed signal acquisition, transforming the real signal into a complex signal;
[0060] Digital envelope detection and pulse flag setting submodule: Envelope detection and pulse flag setting first calculates the envelope of the complex signal, weakens the influence of noise by using the sliding window averaging method of parallel structure, and then obtains the changing characteristics of the rising and falling edges of the radar pulse signal by the first and second difference methods of parallel structure. Finally, the pulse flag is set by the changing characteristics of the rising and falling edges of the radar pulse signal, thereby achieving the purpose of storing a complete radar pulse signal.
[0061] Digital memory signal storage and delay submodule: The digital memory stores the complex signal that has been delayed to the alignment with the flag bit according to the pulse flag bit, and then performs 8-channel delay modulation. That is, after the set time is reached, the stored signal is read out, thereby realizing the delay modulation of the signal.
[0062] 8-channel parallel Doppler frequency modulation submodule: The 8-channel parallel Doppler frequency modulation uses a complex multiplier to perform 8-channel parallel complex multiplication of the complex signal and the complex Doppler frequency signal to achieve Doppler frequency modulation of the signal.
[0063] The 8-channel parallel convolution operation submodule: The 8-channel parallel convolution modulation operation performs 8-channel parallel convolution operations on the signal after delay and Doppler frequency modulation and the sum of the impulse response functions corresponding to multiple scattering points containing amplitude information and distance information between scattering points, to obtain the extended target echo signal.
[0064] Based on the above-described forwarding-based high-fidelity extended target real-time simulation system, this embodiment discloses a forwarding-based high-fidelity extended target real-time simulation method, including the following steps:
[0065] A. The receiving antenna receives the radar transmitted signal, and then the received radar transmitted signal is converted into an intermediate frequency signal by radio frequency downconversion; Step A specifically involves: receiving the radar transmitted signal by the receiving antenna, and then downconverting it to an intermediate frequency signal with a center frequency of 1.8 GHz.
[0066] B. High-speed signal acquisition: The intermediate frequency signal after RF downconversion is acquired at high speed to convert it from analog signal to digital signal. After serial-to-parallel conversion, the digital signal is output as 8 parallel digital signals. Specifically, step B is: high-speed signal acquisition of the intermediate frequency signal at a data rate of 2.4 GHz, and output as 8 parallel digital signals through serial-to-parallel conversion.
[0067] C. The FPGA signal processing module detects and stores the 8 parallel digital signals, and then performs delay, Doppler frequency, and amplitude modulation to obtain the extended target echo signal. Specifically, step C is as follows: the 8 parallel digital signals are detected and stored, and then the extended target echo signal is obtained by performing 8 parallel delay modulation, 8 parallel Doppler frequency modulation, and 8 parallel convolution modulation.
[0068] D. The high-speed digital-to-analog converter performs parallel-to-serial conversion on the extended target echo signal, and then performs digital-to-analog conversion to realize the conversion from 8 parallel digital signals to 1 serial analog signal; Step D is specifically as follows: the extended target echo signal is first subjected to parallel-to-serial conversion to merge the 8 signals into 1 signal, and after merging, it is converted into an analog signal through a high-speed digital-to-analog converter with a data rate of 2.4GHz.
[0069] E. The radio frequency upconversion upconverts the analog signal and then transmits it through the transmitting antenna; step E specifically involves upconverting the analog signal to a radio frequency signal and then transmitting it through the transmitting antenna.
[0070] For more specific details, see step C. Figure 2 The diagram shown is a block diagram of the FPGA signal processing module in the real-time simulation method for high-fidelity extended targets in this embodiment. The steps of the FPGA signal processing module in this real-time simulation method for high-fidelity extended targets include:
[0071] 1. The filter coefficients of the required Hilbert transform filter are obtained by simulation using the FilterDesigner function in Matlab software. The Hilbert transform filter is essentially an all-pass filter with an amplitude-frequency characteristic of 1, and its frequency response is:
[0072]
[0073] In the formula, ω represents frequency; therefore, the passband frequency of the normalized frequency corresponding to the designed Hilbert transform filter is [0.05, 0.95]; its impulse response function is odd-symmetric about the zeros, and the zero and non-zero values alternate. Verify whether the function of the Hilbert transform filter is consistent with the design. If it meets the requirements, derive the filter coefficients, quantize them in 16 bits, and load them into the FIR filter; the FIR filter with the loaded filter coefficients performs 8-channel parallel filtering on the real signal to output a complex signal.
[0074] 2. Calculate the envelope B(n) of the complex signal output by the Hilbert transform filter, and obtain the smoothed sample points using the sliding window averaging method. Assuming the sliding window length is L and the total number of sample points in the envelope is N, the i-th sample sequence can be written as:
[0075]
[0076] The i-th envelope-smoothed sample value for:
[0077]
[0078] At this point, the N envelope-smoothed sample values are used to replace the N envelope sample values without the sliding window. The envelope-smoothed sample points are then subjected to a first difference processing C1(n) = A(n+1) - A(n) and a second difference processing C2(n) = C1(n+1) - C1(n) to obtain the characteristics of the rising and falling edges of the pulse signal. Since the radar signal is transmitted in 8 parallel channels, the calculation of the radar signal envelope, the sliding window averaging method, the first difference method, and the second difference method all employ parallel computation. Finally, the pulse flag is set based on the changes in the rising and falling edges of the radar pulse signal.
[0079] 3. Delay the complex signal until it aligns with the pulse flag bit, and store the delayed complex signal in the digital memory according to the pulse flag bit. Calculate the corresponding delay of the signal in the digital memory using the radial distance between the target and the radar, and then convert the delay into the required number of clock cycles based on the FPGA system clock. If the radial distance between the target and the radar is R, and the FPGA system clock frequency is f... s Then the data rate after M signals are parallelized is M×f s The corresponding clock cycle count is In this embodiment, the number of parallel paths used is M=8. After the clock cycle counts to the required number, the signal in the digital memory is read out in parallel through 8 paths, thereby realizing the delay modulation of the signal.
[0080] 4. Calculate the corresponding frequency control word K based on the Doppler frequency. Assume the bit width of the phase accumulator is P and the Doppler frequency is f. d The data rate after M signals are parallelized is M×f s Then the formula for calculating the frequency control word is K = (f d / (M×f s ))×2 P The complex Doppler frequency signal is generated by the DDS with the frequency control word set. In this embodiment, the number of parallel paths is M=8. The complex Doppler frequency signal and the complex signal are multiplied by 8 parallel paths to realize the Doppler frequency modulation of the signal.
[0081] 5. Convolve the delayed, Doppler-modulated signal with the impulse response function to output the extended target echo signal. The impulse response function contains the amplitude information of the scattering points and the distance information between the scattering points. Add the impulse response functions corresponding to all scattering points of the target to be simulated to obtain the total impulse response function h(n). Then, perform an 8-channel parallel convolution operation with the Doppler-modulated, delayed signal to output the extended target echo simulation signal.
[0082] Please see Figure 3The diagram shows the time-domain implementation structure of the 8-channel parallel convolution operation in the FPGA signal processing module of this embodiment.
[0083] Convolution is the most critical step in the extended target echo simulation algorithm. Since the data rate of the intermediate frequency (IF) signal after down-conversion is still very high, and the convolution operation speed is limited by the FPGA system clock, the direct convolution operation structure needs to be redesigned to match the convolution operation speed with the IF signal data rate. Based on the principle of parallel computing, the IF signal and system function can be first decomposed into M parallel paths, and then M parallel convolution operations can be performed. Assume the IF signal data rate is f... data Then, the data rate of the intermediate frequency signal after conversion to parallel form is reduced to f. data / M, enabling high-speed to low-speed conversion, significantly reduces the clock frequency requirements of the FPGA system. After multi-channel parallel convolution, the data rate of the intermediate frequency signal can be increased from f to f using parallel-to-serial conversion. data / M becomes the original f data This enables low-speed to high-speed conversion, thereby meeting the requirements of convolution operations at high data rates. Figure 3 This describes the implementation structure for parallel convolution operations when the number of parallel paths M is 8. The specific steps are as follows:
[0084] 1. The intermediate frequency signal x(n) after Doppler frequency and time delay modulation is split into 8 parallel data streams x(8n′), x(8n′+1), x(8n′+2)…x(8n′+7);
[0085] 2. Add the impulse response functions containing amplitude information and distance information between scattering points corresponding to each scattering point to obtain h(n), and then split h(n) into 8 parallel data streams h(8n′), h(8n′+1), h(8n′+2)...h(8n′+7);
[0086] 3. The intermediate frequency signals and impulse response functions in the form of 8 parallel data streams are processed according to... Figure 3 The structures shown are convolved, delayed, and summed to obtain extended target echo signal outputs y(8n′), y(8n′+1), y(8n′+2)…y(8n′+7) in the form of 8 parallel data streams.
[0087] This invention overcomes the problems of poor real-time performance and low fidelity in existing extended target echo simulations by employing eight-channel parallel signal processing at a high data rate of 2.4 GHz. This invention can be used in the research, development, debugging, and verification of radar systems, as well as in the field of electronic countermeasures, shortening the R&D cycle and saving R&D costs, thus possessing significant application value.
[0088] The above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.
Claims
1. A method for real-time simulation of a high-fidelity extended target in a repeater mode, characterized in that, Includes the following steps: S1. The receiving antenna receives the radar transmitted signal and converts the received radar transmitted signal into an intermediate frequency signal through the radio frequency down-conversion module. S2, the high-speed signal acquisition module acquires the intermediate frequency signal after RF downconversion at high speed, converts the analog signal into a digital signal, and after serial-to-parallel conversion of the digital signal, obtains 8 parallel digital signal outputs. The S3 FPGA signal processing module detects, stores, and modulates eight parallel digital signals to obtain the extended target echo signal. S4. The high-speed digital-to-analog conversion module first converts the extended target echo signal from parallel to serial to meet the requirements of high-speed digital-to-analog conversion, and then performs digital-to-analog conversion to convert the digital signal into an analog signal. S5. The radio frequency upconversion module upconverts the analog signal obtained in step S4, converting the intermediate frequency signal into a radio frequency signal, which is then transmitted through the transmitting antenna. Step S3 is as follows: (1) The digital signal after high-speed signal acquisition is transformed into a complex signal by performing an 8-channel parallel Hilbert transform. (2) Envelope detection and setting pulse flag: First, calculate the envelope of the complex signal. Then, reduce the influence of noise by using the sliding window averaging method of the parallel structure. Next, obtain the changing characteristics of the rising and falling edges of the radar pulse signal through the first and second difference methods of the parallel structure. Finally, set the pulse flag by using the changing characteristics of the rising and falling edges of the radar pulse signal, so as to achieve the purpose of storing a complete radar pulse signal. (3) The digital memory stores the complex signal that has been delayed to the alignment with the flag bit according to the pulse flag bit, and then performs 8-channel delay modulation. That is, after the set time is reached, the stored signal is read out to realize the delay modulation of the signal. (4) 8-channel parallel Doppler frequency modulation: The complex signal and the complex Doppler frequency signal are multiplied in 8-channel parallel process by a complex multiplier to achieve Doppler frequency modulation of the signal. (5) The 8-channel parallel convolution modulation operation performs an 8-channel parallel convolution operation on the signal after delay and Doppler frequency modulation and the sum of the impulse response functions corresponding to multiple scattering points containing amplitude information and distance information between scattering points, to obtain the extended target echo signal.
2. The method of claim 1, wherein, The specific process of step (1) is as follows: Simulation is used to obtain the filter coefficients of the Hilbert transform filter. The Hilbert transform filter is an all-pass filter with an amplitude-frequency characteristic of 1, and its frequency response is: In the formula, The frequency is represented; the Hilbert transform filter in the simulation is verified to be consistent with the required function. If it meets the requirements, the filter coefficients are exported, quantized and put into the FIR filter, and the real signal is transformed into a complex signal through the FIR filter.
3. The forwarding-based high-fidelity extended target real-time simulation method according to claim 1, characterized in that, The specific process of step (2) is as follows: calculate the envelope B(n) of the complex signal output by the Hilbert transform filter, and obtain the smoothed sample points by using the sliding window averaging method. Let the sliding window length be L and the total number of sample points in the envelope be N, then the i-th sample sequence can be written as: The i-th envelope-smoothed sample value for: Replace the N unsmoothed envelope sample values with the obtained N smoothed envelope sample values; perform a difference operation on the smoothed envelope sample values. and two difference processing The characteristics of the rising and falling edges of the pulse signal are then obtained. Since the radar signal is transmitted in 8 parallel channels, the calculation of the radar signal envelope, the sliding window averaging method, the first differential method, and the second differential method are all in parallel. Finally, the pulse flag is set according to the changes in the rising and falling edges of the radar pulse signal.
4. The forwarding-based high-fidelity extended target real-time simulation method according to claim 1, characterized in that, The specific process of step (3) is as follows: delay the complex signal until it is aligned with the pulse flag bit, and store the delayed complex signal in the digital memory according to the pulse flag bit; calculate the corresponding delay of the signal in the digital memory according to the radial distance between the target and the radar, and then convert the delay into the required number of clock cycles according to the FPGA system clock; if the radial distance between the target and the radar is R, and the FPGA system clock frequency is Then the data rate after M signals are parallelized is The corresponding clock cycle count is .
5. The forwarding-based high-fidelity extended target real-time simulation method according to claim 1, characterized in that, The specific process of step (4) is as follows: Calculate the corresponding frequency control word K based on the Doppler frequency, and set the bit width of the phase accumulator to P and the Doppler frequency to be 1. The data rate after M signals are parallelized is Then the formula for calculating the frequency control word is: The complex Doppler frequency signal is generated by a digital frequency synthesizer (DDS) with a frequency control word, and then the complex Doppler frequency signal is multiplied by the complex signal.
6. The forwarding-based high-fidelity extended target real-time simulation method according to claim 1, characterized in that, The specific process of step (5) is as follows: Each scattering point corresponds to an impulse response function containing amplitude information and distance information between scattering points. The impulse response functions corresponding to all scattering points of the extended target to be simulated are added together. The signal after delay and Doppler frequency modulation is combined with the sum of the impulse response functions and then subjected to 8-way parallel convolution operation. The result of the operation is the extended target echo signal.
7. A forward-type high-fidelity extended target real-time simulation system, characterized in that, Includes the following modules: The radio frequency downconversion module receives radar transmitted signals through a receiving antenna, converts the received radar transmitted signals into intermediate frequency signals, and sends them to the high-speed signal acquisition module. The high-speed signal acquisition module acquires intermediate frequency signals at high speed, converts analog signals into digital signals, and then performs serial-to-parallel conversion on the digital signals to obtain 8 parallel digital signal outputs. The FPGA signal processing module detects, stores, and modulates the eight parallel digital signals input to obtain the extended target echo signal, which is then input into the high-speed digital-to-analog converter module. The high-speed digital-to-analog converter module first converts the extended target echo signal from parallel to serial to meet the requirements of high-speed digital-to-analog conversion, and then performs digital-to-analog conversion to convert the digital signal into an analog signal. The radio frequency upconversion module upconverts the analog signal obtained from the high-speed digital-to-analog converter module, converting the intermediate frequency signal into a radio frequency signal, which is then transmitted through the transmitting antenna. The FPGA signal processing module specifically includes the following sub-modules: 8-channel parallel Hilbert transform submodule: Performs 8-channel parallel Hilbert transform on the digital signal after high-speed signal acquisition, transforming the real signal into a complex signal; Digital envelope detection and pulse flag setting submodule: Envelope detection and pulse flag setting first calculates the envelope of the complex signal, weakens the influence of noise by using the sliding window averaging method of parallel structure, and then obtains the changing characteristics of the rising and falling edges of the radar pulse signal by the first and second difference methods of parallel structure. Finally, the pulse flag is set by the changing characteristics of the rising and falling edges of the radar pulse signal, thereby achieving the purpose of storing a complete radar pulse signal. Digital memory signal storage and delay submodule: The digital memory stores the complex signal that has been delayed to the alignment with the flag bit according to the pulse flag bit, and then performs 8-channel delay modulation. That is, after the set time is reached, the stored signal is read out to realize the delay modulation of the signal. 8-channel parallel Doppler frequency modulation submodule: The 8-channel parallel Doppler frequency modulation uses a complex multiplier to perform 8-channel parallel complex multiplication of the complex signal and the complex Doppler frequency signal to achieve Doppler frequency modulation of the signal. The 8-channel parallel convolution operation submodule: The 8-channel parallel convolution modulation operation performs 8-channel parallel convolution operations on the signal after delay and Doppler frequency modulation and the sum of the impulse response functions corresponding to multiple scattering points containing amplitude information and distance information between scattering points, to obtain the extended target echo signal.