A time-to-digital conversion circuit and a time-to-digital conversion method
By combining a parallel sampling loop oscillator and a time-to-digital converter circuit with multiple trigger sampling, high-resolution and wide dynamic range time-to-digital conversion is achieved with low power consumption, solving the problems of high power consumption and nonlinearity in existing technologies, and improving measurement accuracy and linearity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUHU RES INST OF XIAN UNIV OF ELECTRONIC SCI & TECH
- Filing Date
- 2023-09-08
- Publication Date
- 2026-07-21
AI Technical Summary
Existing time-to-digital converters struggle to achieve high resolution and wide dynamic range under low power conditions, and suffer from problems such as limited dynamic range, high power consumption, and complex decoding.
A time-to-digital converter circuit based on a parallel sampling ring oscillator and multiple trigger sampling is adopted. By combining a ring differential delay oscillator, an asynchronous counter, multiple digital delay generators and trigger groups, dynamic component matching is achieved, reducing power consumption and improving resolution and linearity.
It achieves high resolution and wide dynamic range with low power consumption, reduces counter latching errors, improves measurement accuracy and linearity, and solves the nonlinearity problem caused by delay unit mismatch in the prior art.
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Figure CN117111435B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of mixed-signal integrated circuit technology, and in particular to a time-to-digital conversion circuit and a time-to-digital conversion method. Background Technology
[0002] High-performance time-to-digital converters (TDCs) are becoming increasingly important in all applications, including analog and digital phase-locked loops, analog-to-digital converters (ADCs), time-of-flight (TOF) measurements, and instrumentation. Especially in lidar time-of-flight measurement applications, high-performance TDCs are indispensable. As lidar demands for ranging accuracy continue to increase, the precision requirements for TDC circuits have reached the picosecond level. However, simultaneously meeting the requirements of low power consumption, high linearity, fine resolution, large dynamic range, and compactness is very challenging.
[0003] The most traditional time-delay oscillator (TDC) uses inverters or buffer delay units to quantize time and can achieve a resolution of 15-30 ps in CMOS technology. However, inverters or buffer delay units have a minimum delay limit and cannot be used in higher-performance TDCs. Subsequent TDCs using vernier structures suffer from cell mismatch issues. TDCs based on buffer delay chains or vernier delay chains have very limited dynamic ranges. Various TDCs based on time amplifiers have limited detection ranges and high power consumption. TDCs based on vernier ring differential delay oscillators, developed to achieve wide dynamic range and high resolution, have complex decoding and high power consumption.
[0004] Therefore, providing a time-to-digital converter that can achieve high resolution and wide dynamic range with low power consumption has become an urgent problem to be solved. Summary of the Invention
[0005] Therefore, in order to solve the above-mentioned problems in the prior art, this application provides a time data conversion circuit based on a parallel sampling loop oscillator and multi-trigger sampling, which can realize dynamic component matching and thus achieve high resolution and large dynamic range under low power consumption, as well as a time data conversion method corresponding to the time data conversion circuit.
[0006] According to a first aspect, the present invention provides a time-to-digital conversion circuit, comprising:
[0007] A signal generator is used to receive a first input signal and a second input signal, and to generate an enable signal based on the first input signal and the second input signal, and to generate a sampling signal based on the second input signal; and to generate a disable signal after a preset time difference has elapsed since the second input signal was received.
[0008] A ring differential delay oscillator is used to generate differential delay pulses under the control of an enable signal; the ring differential delay oscillator stops oscillating under the control of a disable signal, and starts oscillating from the disable position at the start of the next time interval quantization.
[0009] Two asynchronous counters are used to count the delay units of the differential delay pulses to obtain the first counting result;
[0010] Multiple digital delay generators are used to delay the sampled signal to generate multiple first delayed sampled signals; the delay of the multiple first delayed sampled signals relative to the sampled signal increases progressively with a preset delay difference;
[0011] Multiple first trigger groups are configured corresponding to multiple digital delay generators. Each first trigger group is used to acquire the phase state of the ring differential delay oscillator under the triggering of the corresponding first delay sampling signal.
[0012] The vibration damping delay device is used to delay the disable signal and generate a second delayed sampling signal;
[0013] The second trigger group is used to acquire the phase state of the ring differential delay oscillator when it is disabled, triggered by the second delayed sampling signal.
[0014] The phase decoder is used to generate a second counting result based on the phase states acquired by multiple first trigger groups; it is also used to generate a start position marker for the next time interval quantization based on the phase states of the ring differential delay oscillator when it is disabled, acquired by the second trigger group.
[0015] The output calculator is used to output the quantization result of the time interval between the first input signal and the second input signal based on the first count result, the second count result, and the starting position mark.
[0016] In an optional implementation, the ring differential delay oscillator includes:
[0017] Multiple delay units are connected in sequence. The positive output of a first-level delay unit is connected to the positive input of the next-level delay unit, and the negative output is connected to the negative input of the next-level delay unit. The positive output of the last-level delay unit is connected to the negative input of the first-level delay unit, and the negative output of the last-level delay unit is connected to the positive input of the first-level delay unit. The delay unit includes a differential delay module, a control module, and a latch module. The differential delay module is connected to the control module, and the latch module is connected to the differential delay module. The control module is used to receive enable and disable signals. The differential delay module is used to receive differential input voltage and generate differential output voltage under the control of the enable signal. The latch module is used to latch the level state of the differential delay module.
[0018] In an optional implementation, the ring differential delay oscillator includes:
[0019] The sources of the first PMOS transistor and the first NMOS transistor are respectively connected to the high-level output terminal and the low-level output terminal of the driving power supply.
[0020] The gates of the second PMOS transistor and the second NMOS transistor are connected to each other and connected to the first differential input voltage. The drains of the two transistors are connected to each other and connected to the first differential voltage output terminal. The source of the second PMOS transistor is connected to the drain of the first PMOS transistor, and the source of the second NMOS transistor is connected to the drain of the first NMOS transistor.
[0021] The gates of the third PMOS transistor and the third NMOS transistor are connected to each other and connected to the second differential input voltage. The drains of the two transistors are connected to each other and connected to the second differential voltage output terminal. The source of the third PMOS transistor is connected to the drain of the first PMOS transistor, and the source of the third NMOS transistor is connected to the drain of the first NMOS transistor.
[0022] The fourth PMOS transistor and the fourth NMOS transistor have their sources connected to the high-level output terminal and the low-level output terminal of the driving power supply, respectively. Their drains are connected to each other and connected to the first differential voltage output terminal. Their gates are connected to each other and connected to the second differential voltage output terminal.
[0023] The fifth PMOS transistor and the fifth NMOS transistor have their sources connected to the high-level output terminal and the low-level output terminal of the driving power supply, respectively. Their drains are connected to each other and connected to the second differential voltage output terminal. Their gates are connected to each other and connected to the first differential voltage output terminal.
[0024] In an optional implementation, the flip-flops in the first and second flip-flop groups are both D flip-flops based on a sense amplifier.
[0025] In an optional implementation, the time-to-digital conversion circuit further includes:
[0026] A digital delay controller, positioned between the phase decoder and the digital delay generators, adjusts the delays of the multiple digital delay generators based on the phase states acquired by multiple first trigger groups, until a preset delay difference is achieved, progressively increasing between the multiple digital delay generators. Where N refers to the number of digital delay generators. It refers to the delay of a delay unit in a ring differential delay oscillator.
[0027] In an optional implementation, the digital delay generator includes:
[0028] A binary code to thermometer code converter is used to receive control signals from a digital delay controller and convert the control signals into thermometer code output.
[0029] The PMOS load array has the source of each PMOS load shorted to its own drain, and the source of each PMOS load is connected to the respective output terminal of the binary code to thermometer code converter.
[0030] An input inverter is used, with its input terminal receiving a sampling signal and its output terminal connected to the input terminals of a first buffer inverter group, a second buffer inverter group, and a third buffer inverter group. The first buffer inverter group includes one buffer inverter, the second buffer inverter group includes two buffer inverters, and the third buffer inverter group includes four buffer inverters.
[0031] The first output inverter has its gates of each PMOS load in the PMOS load array and the output of the first buffer inverter group connected to the input of the first output inverter. The output of the second buffer inverter group after passing through the first selection control switch and the output of the third buffer inverter group after passing through the second selection control switch are also connected to the input of the first output inverter.
[0032] The second output inverter has its input connected to the output of the first output inverter, and its output output is the first delayed sampling signal.
[0033] According to a second aspect, the present invention also provides a time-to-digital conversion method, comprising the following steps:
[0034] The first time signal and the second time signal are input into the time-to-digital conversion circuit in any of the above-described first-side embodiments to obtain the time interval quantization result between the first time signal and the second time signal.
[0035] According to a third aspect, the present invention also provides a time-to-digital conversion method, comprising the following steps:
[0036] By repeatedly inputting the first time signal and the second time signal into the time-to-digital conversion circuit in any of the above-described first-side embodiments, multiple preliminary time interval quantization results between the first time signal and the second time signal are obtained.
[0037] The average value of multiple preliminary time interval quantization results is calculated to obtain the time interval quantization result between the first time signal and the second time signal.
[0038] The technical solution provided by this invention has the following advantages:
[0039] 1. The time-to-digital converter circuit provided by this invention, by correspondingly setting multiple digital delay generators and multiple first trigger groups, performs multiple delay samplings on the phase state of the ring differential delay oscillator, which can improve the time resolution of the time-to-digital converter circuit to one-Nth of the resolution in the ring differential delay oscillator (N is the number of digital delay generators). Moreover, the power consumed by the digital delay generators and trigger groups is much lower than the power consumed by the core ring oscillator and counter. Therefore, high resolution can be achieved with low power consumption. By setting the oscillator to a ring differential delay oscillator and correspondingly setting two asynchronous counters, the possibility of error in the first counting result latched by the counter can be greatly reduced. By setting the ring differential delay oscillator to be disabled after the circuit receives the second input signal for a period of time (correspondingly, the two asynchronous counters also do not work), and starting oscillation from the previously stopped position when the next time interval quantization begins (that is, the ring differential delay oscillator can start oscillating from any delay unit), dynamic component matching can be achieved while reducing circuit power consumption. Randomizing the linear error generated by the mismatch of buffer components solves the problem of high integral nonlinearity caused by the mismatch of a large number of delay units in the prior art, so that the digital converter circuit has good linearity and wide dynamic range.
[0040] 2. The time-to-digital conversion circuit provided by the present invention, by setting the flip-flops in the first and second flip-flop groups to be D flip-flops (SAFFs) based on sense amplifiers, can minimize the metastability generated by the sampled data when the ring differential delay oscillator occurs near the rising edge of the clock, and can further improve the quantization data accuracy of the time-to-digital conversion circuit.
[0041] 3. The time-to-digital conversion method provided by this invention can reduce the output variation and further improve the accuracy of the final time interval quantization result by averaging the quantization results of multiple preliminary time intervals, since different delay units mismatch leads to different measurement results. Attached Figure Description
[0042] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0043] Figure 1 This is a schematic diagram of the time-to-digital conversion circuit provided in Embodiment 1 of the present invention;
[0044] Figure 2 This is a schematic diagram of a ring differential delay oscillator provided in Embodiment 1 of the present invention;
[0045] Figure 3 for Figure 2 A schematic diagram of the delay shift of the ring differential delay oscillator in the diagram;
[0046] Figure 4 This is a schematic diagram of the specific structure of a delay unit provided in Embodiment 1 of the present invention;
[0047] Figure 5 This is a schematic diagram of the specific structure of a D flip-flop based on a sense amplifier provided in Embodiment 1 of the present invention;
[0048] Figure 6 This is a schematic diagram of the specific structure of a digital delay generator provided in Embodiment 1 of the present invention;
[0049] Figure 7 This is a flowchart of a time-to-digital conversion circuit method provided in Embodiment 2 of the present invention;
[0050] Figure 8 A flowchart of another time-to-digital conversion circuit method provided in Embodiment 2 of the present invention. Detailed Implementation
[0051] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0052] In the description of this invention, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0053] Example 1
[0054] Figure 1 A schematic diagram of the time-to-digital conversion circuit in one embodiment of this invention is shown. Figure 1 As shown, the time-to-digital conversion circuit includes: a signal generator, a ring differential delay oscillator, two asynchronous counters, multiple digital delay generators, multiple first flip-flop groups, an anti-oscillation delay unit, a second flip-flop group, a phase decoder, and an output calculator.
[0055] The signal generator is used to receive a first input signal In_A (i.e., a first time signal) and a second input signal In_B (i.e., a second time signal), and to generate an enable signal EN based on the first input signal In_A and the second input signal In_B, and to generate a sampling signal Clk0 based on the second input signal; and the signal generator is used to generate a disable signal ENB after a preset time difference has elapsed after receiving the second input signal In_B.
[0056] In this embodiment, in order to prevent the disabling of the ring differential delay oscillator from affecting the sampling of the first and second trigger groups, the disable signal ENB is generated after the sampling of the last stage first trigger group is completed. That is, the preset time difference is greater than the delay amount of the last stage digital delay generator.
[0057] A ring differential delay oscillator is used to generate differential delay pulses under the control of an enable signal; the ring differential delay oscillator stops oscillating under the control of a disable signal, and starts oscillating from the disable position at the start of the next time interval quantization.
[0058] In this embodiment, as Figure 2 As shown, a ring differential delay oscillator has multiple delay units connected in sequence. The positive output of the first-stage delay unit is connected to the positive input of the next-stage delay unit, and the negative output is connected to the negative input of the next-stage delay unit. The positive output of the last-stage delay unit is connected to the negative input of the first-stage delay unit, and the negative output of the last-stage delay unit is connected to the positive input of the first-stage delay unit, forming a ring structure. Figure 2 The example shown is a ring differential delay oscillator with eight delay units that can provide 16-phase output.
[0059] In this embodiment, since the ring differential delay oscillator starts oscillating from its previously stopped position, it can start from any delay unit during a time interval quantization process; for example... Figure 3 As shown, taking the above-mentioned ring differential delay oscillator with 8 delay units as an example, if the input pulse width (that is, the pulse width between the first input signal and the second input signal) is about three buffer delays, then in the first quantization, the oscillation propagates from delay 1 to delay 3, in the second quantization, the oscillation propagates from delay 4 to delay 6, in the third measurement, the oscillation propagates from delay 7 to delay 1, and in the fourth measurement, the oscillation propagates from delay 2 to delay 4.
[0060] In this embodiment, different delay unit mismatches lead to different measurement results, thereby achieving dynamic element matching. This dynamic element matching can randomize the linear error caused by buffer element mismatch, improving the spurious-free dynamic range. Simultaneously, since the random error is distributed at its noise floor, its signal-to-noise ratio and distortion ratio are not increased. Furthermore, the random error may manifest as changes in the output code during single-shot accuracy testing, but these changes can be reduced by averaging several samples. Existing architectures without dynamic element matching (e.g., vernier chain-based TDC), while achieving excellent single-shot measurement accuracy in terms of output code variation, suffer from poor integral nonlinearity (INL) performance because the input pulse always passes through the same delay unit sequence, resulting in a large deviation of the output code from the ideal value. Moreover, since this architecture exhibits the same error for the same input time width, the error caused by its poor integral nonlinearity cannot be reduced by averaging. Therefore, in summary, compared to existing architectures, the time-to-digital converter circuit in this embodiment, after adjustment and measurement with dynamic element matching, shows a significant improvement in both measurement accuracy and linearity.
[0061] In one specific embodiment of this example, the delay unit may include a differential delay module, a control module, and a latch module. The differential delay module is connected to the control module, and the latch module is connected to the differential delay module. The control module is used to receive an enable signal EN and a disable signal ENB. The differential delay module is used to receive differential input voltages vin+ and vin- under the control of the enable signal and generate differential output voltages vo+ and vo-. The latch module is used to latch the level state of the differential delay module.
[0062] In one specific implementation of this embodiment, such as Figure 4As shown, the delay unit can be a transistor delay unit. Specifically, the delay unit may include: a first PMOS transistor MP1 and a first NMOS transistor MN1 (i.e., the control module), whose sources are respectively connected to the high-level output terminal VDD and the low-level output terminal VSS of the driving power supply; a second PMOS transistor MP2 and a second NMOS transistor MN2, whose gates are interconnected and connected to the first differential input voltage vin+ (i.e., the non-inverting input voltage), and whose drains are interconnected and connected to the first differential voltage output terminal vo- (i.e., the output terminal of the inverting output voltage). The source of the second PMOS transistor MP2 is connected to the drain of the first PMOS transistor MP1, and the source of the second NMOS transistor MN2 is connected to the drain of the first NMOS transistor MN1; a third PMOS transistor MP3 and a third NMOS transistor MN3 (MP2, MN2, MP3, and MN3 constitute the differential delay module), whose gates are interconnected and connected to the second differential input voltage vin- (i.e., the inverting input voltage). The drains of the first PMOS transistor MP3 and NMOS transistor MN3 are connected to each other and to the second differential voltage output terminal vo+ (i.e., the output terminal of the positive phase output voltage). The source of the third PMOS transistor MP3 is connected to the drain of the first PMOS transistor MP1, and the source of the third NMOS transistor MN3 is connected to the drain of the first NMOS transistor MN1. The sources of the fourth PMOS transistor MP4 and the fourth NMOS transistor MN4 are connected to the high-level output terminal VDD and the low-level output terminal VSS of the driving power supply, respectively. Their drains are connected to each other and to the first differential voltage output terminal vo-, and their gates are connected to each other and to the second differential voltage output terminal vo+. The sources of the fifth PMOS transistor MP5 and the fifth NMOS transistor MN5 (MP4, MN4, MP5 and MN5 are the latch module) are connected to the high-level output terminal VDD and the low-level output terminal VSS of the driving power supply, respectively. Their drains are connected to each other and to the second differential voltage output terminal vo+, and their gates are connected to each other and to the first differential voltage output terminal vo-.
[0063] Specifically, the first differential input voltage vin+ and the second differential input voltage vin− drive four differential delay transistors MP2, MN2, MP3, and MN3. Transistors MN1 and MP1 connect the input transistors to ground and power supply, respectively, to control the delay unit. To reduce power consumption, the enable time of the ring differential delay oscillator is only slightly longer than the input pulse width. That is, after receiving the second input signal, the ring differential delay oscillator generates a disable signal ENB (i.e., ENB is pulled to VDD and EN is pulled to VSS) after a short preset time difference. At this time, MN1 and MP1 are disabled, and the ring differential delay oscillator stops oscillating. When MN1 and MP1 are off, no current flows through MP1, MN1, MP2, MN2, MP3, or MN3. However, unlike MP2 and MP3, the sources of MP4 and MP5 are directly connected to VDD, and unlike MN2 and MN3, the sources of MN4 and MN5 are directly connected to VSS. Therefore, after MP1 and MN1 are off, the transistors MP4, MP5, MN4, and MN5 of the latch module are still powered on, enabling one end of the differential output to be high and the other end to be low. This ensures that the next conversion always starts from a known position (sampled by the second set of flip-flops). Based on this, the time-to-digital converter architecture does not require parasitic capacitance at the output node to maintain the output voltage, and is therefore unaffected by leakage problems that occur in deep submicron CMOS technology.
[0064] Two asynchronous counters are used to count the delay units of the differential delay pulses to obtain the first count result.
[0065] Specifically, two asynchronous counters are configured corresponding to a ring differential delay oscillator, with the differential delay oscillator serving as the... Figure 1 Taking the 16-phase output differential delay oscillator shown as an example, the two asynchronous counters correspond to two 8-bit asynchronous counters.
[0066] Multiple digital delay generators are used to delay the sampled signal to generate multiple first delayed sampled signals; the delay of the multiple first delayed sampled signals relative to the sampled signal increases progressively with a preset delay difference.
[0067] Specifically, the number of digital delay generators can be set according to the resolution requirements of the time-to-digital conversion circuit in the specific application. For example, if the delay of one delay unit in a ring differential delay oscillator is... If the number of digital delay generators is N, then it is only necessary to set the preset delay difference between the N digital delay generators. Set as This can be achieved The resolution. That is, if the number of digital delay generators is 4, then the delay of the first-stage digital delay generator is... for The delay of the second-stage digital delay generator is The delay of the third-stage digital delay generator is The delay of the fourth-stage digital delay generator is .
[0068] Multiple first trigger groups are configured to correspond to multiple digital delay generators. Each first trigger group is used to acquire the phase state of the ring differential delay oscillator under the triggering of the corresponding first delay sampling signal.
[0069] Specifically, taking four digital delay generators as an example, such as Figure 1 As shown, the first trigger group has four triggers.
[0070] The oscillation damping delay is used to delay the disable signal and generate a second delayed sampling signal; the second trigger group is used to acquire the phase state of the ring differential delay oscillator when it is disabled under the trigger of the second delayed sampling signal.
[0071] In an optional embodiment of this invention, to further improve the quantization data accuracy of the time-to-digital conversion circuit, the flip-flops in both the first and second flip-flop groups can be configured as D flip-flops based on a sense amplifier. Specifically, the D flip-flops based on the sense amplifier may include a sense amplifier module and a latch module, and their specific component structures can be as follows: Figure 5 The diagram shows the component types and connections between components in a D flip-flop based on a sense amplifier. Figure 5 All of these can be clearly shown in the text, so they will not be repeated here.
[0072] The phase decoder is used to generate a second counting result based on the phase states acquired by multiple first trigger groups; it is also used to generate a start position marker for the next time interval quantization based on the phase state of the ring differential delay oscillator when it is disabled, acquired by the second trigger group; the output calculator is used to output the time interval quantization result between the first input signal and the second input signal based on the first counting result, the second counting result and the start position marker.
[0073] In one optional embodiment of this example, in order to expand the application range of the time-to-digital conversion circuit and further improve the accuracy of its quantization data, such as... Figure 1 As shown, the time-to-digital conversion circuit can also include a digital delay controller. This digital delay controller is located between the phase decoder and the digital delay generator, and is used to adjust the delay of the multiple digital delay generators according to the phase states collected by the multiple first trigger groups, until a preset delay difference exists between the multiple digital delay generators. Where N refers to the number of digital delay generators. It refers to the delay of a delay unit in a ring differential delay oscillator.
[0074] At this time, as Figure 6 As shown, the digital delay generator can be configured to include: a binary code to thermometer code converter, a PMOS load array, an input inverter, a first output inverter, and a second output inverter; wherein, the binary code to thermometer code converter is used to receive the control signal DCW<5:0> from the digital delay controller and convert the control signal DCW<5:0> into thermometer code output; the PMOS load array T... <0> ~T <63> Each PMOS load in the array has its source shorted to its drain, and the source of each PMOS load is connected to the respective output of the binary code to thermometer code converter. The input of the input inverter is connected to the sampling signal Clk0, and its output is connected to the input of the first buffer inverter group, the second buffer inverter group, and the third buffer inverter group. The first buffer inverter group includes one buffer inverter, the second buffer inverter group includes two buffer inverters, and the third buffer inverter group includes four buffer inverters. The gate of each PMOS load in the PMOS load array and the output of the first buffer inverter group are connected to the input of the first output inverter. The output of the second buffer inverter group is connected to the first output inverter after passing through the first selection control switch, and the output of the third buffer inverter group is connected to the first output inverter after passing through the second selection control switch. The input of the second output inverter is connected to the output of the first output inverter, and the output outputs the first delayed sampling signal. Specifically, the first and second selection control switches are controlled by the switch control signal SEL<1:0>. When SEL<1:0>=00, both switches are open, and only the first buffer inverter group is connected to drive the PMOS load array, resulting in the longest time delay difference. When SEL<1:0>=11, both switches are closed, and the first, second, and third buffer inverter groups are all connected to the PMOS load array, reducing the maximum delay (correspondingly, the preset delay difference between multiple digital delay generators is reduced, and the resolution of the time-to-digital conversion circuit is improved).
[0075] In summary, the time-to-digital converter circuit in this embodiment, by correspondingly setting multiple digital delay generators and multiple first trigger groups, performs multiple delayed samplings of the phase state of the ring differential delay oscillator, which can improve the time resolution of the time-to-digital converter circuit to one-Nth of the resolution in the ring differential delay oscillator (N being the number of digital delay generators). Moreover, the power consumed by the digital delay generators and trigger groups is far lower than that consumed by the core ring oscillator and counters. Therefore, high resolution can be achieved with low power consumption. Furthermore, by setting the oscillator to a ring differential delay oscillator and correspondingly setting two asynchronous counters, the possibility of errors in the first counting result latched by the counters can be greatly reduced. By setting the ring differential delay oscillator to be disabled after the circuit receives the second input signal for a period of time (correspondingly, the two asynchronous counters also do not work), and oscillating from the previously stopped position when the next time interval quantization begins (that is, the ring differential delay oscillator can start oscillating from any of its delay units), dynamic component matching can be achieved while reducing circuit power consumption. Randomizing the linear error generated by the mismatch of buffer components solves the problem of high integral nonlinearity caused by the mismatch of a large number of delay units in the prior art, giving the digital converter circuit good linearity and wide dynamic range.
[0076] Example 2
[0077] Figure 7 A flowchart of a time array conversion method in one embodiment of this paper is shown. The method in this embodiment is based on the time data conversion circuit in Embodiment 1 above. Therefore, the content already disclosed in Embodiment 1 will not be repeated in this embodiment. Figure 7 As shown, the time array conversion method in this embodiment may include the following steps:
[0078] S701: Input the first time signal and the second time signal into the time-to-digital conversion circuit in Embodiment 1 to obtain the quantization result of the time interval between the first time signal and the second time signal.
[0079] The ring differential delay oscillator in the time array conversion circuit starts oscillating from its previously stopped position. That is, during a single time interval quantization process, the ring differential delay oscillator can start from any delay unit. Mismatches between different delay units lead to different measurement results. Random errors may manifest as variations in the output code during single-shot accuracy testing. Therefore, to reduce output variations and further improve the accuracy of the time interval quantization results... Figure 8 A flowchart of a time array conversion method in another embodiment of this example is shown. Figure 8 As shown, the time array conversion method in this embodiment includes the following steps:
[0080] S801: The first time signal and the second time signal are input into the time-to-digital conversion circuit in Embodiment 1 multiple times to obtain multiple preliminary time interval quantization results between the first time signal and the second time signal.
[0081] S802: Calculate the average value of multiple preliminary time interval quantization results to obtain the time interval quantization result between the first time signal and the second time signal.
[0082] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.
Claims
1. A time-to-digital conversion circuit, characterized in that, include: A signal generator is used to receive a first input signal and a second input signal, and to generate an enable signal based on the first input signal and the second input signal, and to generate a sampling signal based on the second input signal; It is also used to generate a disable signal after a preset time difference has elapsed after receiving the second input signal; A ring differential delay oscillator is used to generate differential delay pulses under the control of the enable signal; The ring differential delay oscillator stops oscillating under the control of the disable signal and starts oscillating from the disable position at the start of the next time interval quantization; the ring differential delay oscillator includes: a plurality of delay units connected in sequence, the positive output terminal of the first-level delay unit is connected to the positive input terminal of the next-level delay unit, and the negative output terminal is connected to the negative input terminal of the next-level delay unit; and the positive output terminal of the last-level delay unit is connected to the negative input terminal of the first-level delay unit, and the negative output terminal of the last-level delay unit is connected to the positive input terminal of the first-level delay unit; Two asynchronous counters are configured corresponding to the ring differential delay oscillator; the asynchronous counters are used to count the number of delay units for the propagation of the differential delay pulse, and obtain a first counting result; Multiple digital delay generators are used to delay the sampled signal to generate multiple first delayed sampled signals; the delay of the multiple first delayed sampled signals relative to the sampled signal increases progressively with a preset delay difference. Multiple first trigger groups are configured corresponding to multiple digital delay generators, and each first trigger group is used to acquire the phase state of the ring differential delay oscillator under the triggering of the corresponding first delay sampling signal; A vibration damping delay device is used to delay the disable signal and generate a second delayed sampling signal; The second trigger group is used to acquire the phase state of the ring differential delay oscillator when it is disabled, triggered by the second delayed sampling signal. A phase decoder is used to generate a second counting result based on the phase states acquired by multiple first trigger groups; it is also used to generate a start position marker for the next time interval quantization based on the phase states acquired by the second trigger group when the ring differential delay oscillator is disabled. An output calculator is used to output the time interval quantization result between the first input signal and the second input signal based on the first counting result, the second counting result, and the start position marker of this time interval quantization.
2. The time-to-digital conversion circuit according to claim 1, characterized in that, The delay unit includes a differential delay module, a control module, and a latch module. The differential delay module is connected to the control module, and the latch module is connected to the differential delay module. The control module is used to receive the enable signal and the disable signal. The differential delay module is used to receive the differential input voltage and generate the differential output voltage under the control of the enable signal. The latch module is used to latch the level state of the differential delay module.
3. The time-to-digital conversion circuit according to claim 2, characterized in that, The delay unit includes: The sources of the first PMOS transistor and the first NMOS transistor are respectively connected to the high-level output terminal and the low-level output terminal of the driving power supply. The gates of the second PMOS transistor and the second NMOS transistor are connected to each other and connected to the first differential input voltage. The drains of the two transistors are connected to each other and connected to the first differential voltage output terminal. The source of the second PMOS transistor is connected to the drain of the first PMOS transistor, and the source of the second NMOS transistor is connected to the drain of the first NMOS transistor. The gates of the third PMOS transistor and the third NMOS transistor are connected to each other and connected to the second differential input voltage. The drains of the two transistors are connected to each other and connected to the second differential voltage output terminal. The source of the third PMOS transistor is connected to the drain of the first PMOS transistor, and the source of the third NMOS transistor is connected to the drain of the first NMOS transistor. The fourth PMOS transistor and the fourth NMOS transistor have their sources connected to the high-level output terminal and the low-level output terminal of the driving power supply, respectively. Their drains are connected to each other and connected to the first differential voltage output terminal. Their gates are connected to each other and connected to the second differential voltage output terminal. The fifth PMOS transistor and the fifth NMOS transistor have their sources connected to the high-level output terminal and the low-level output terminal of the driving power supply, respectively. Their drains are connected to each other and to the second differential voltage output terminal, and their gates are connected to each other and to the first differential voltage output terminal.
4. The time-to-digital conversion circuit according to claim 1, characterized in that, Both the first and second flip-flop groups contain D flip-flops based on sense amplifiers.
5. The time-to-digital conversion circuit according to any one of claims 1-4, characterized in that, Also includes: A digital delay controller, disposed between the phase decoder and the digital delay generator, is used to adjust the delay of the multiple digital delay generators according to the phase states collected by the multiple first trigger groups, until the preset delay difference between the multiple digital delay generators is reached. Where N refers to the number of digital delay generators. This refers to the delay amount of a delay unit in the ring differential delay oscillator.
6. The time-to-digital conversion circuit according to claim 5, characterized in that, The digital delay generator includes: A binary code to thermometer code converter is used to receive the control signal from the digital delay controller and convert the control signal into thermometer code output; The PMOS load array has each PMOS load's source shorted to its own drain, and each PMOS load's source is connected to its respective output terminal of the binary code to thermometer code converter. An input inverter is provided, with its input terminal connected to the sampling signal and its output terminal connected to the input terminals of a first buffer inverter group, a second buffer inverter group, and a third buffer inverter group; the first buffer inverter group includes one buffer inverter, the second buffer inverter group includes two buffer inverters, and the third buffer inverter group includes four buffer inverters. The first output inverter has its gates of each PMOS load in the PMOS load array and the output terminals of the first buffer inverter group connected to the input terminal of the first output inverter. The output terminals of the second buffer inverter group and the third buffer inverter group are also connected to the input terminal of the first output inverter after passing through the first selection control switch and the second selection control switch, respectively. The second output inverter has its input terminal connected to the output terminal of the first output inverter, and its output terminal outputs the first delayed sampling signal.
7. A time-to-digital conversion method, characterized in that, Includes the following steps: The first time signal and the second time signal are input into the time-to-digital conversion circuit according to any one of claims 1-6 to obtain the time interval quantization result between the first time signal and the second time signal.
8. A time-to-digital conversion method, characterized in that, Includes the following steps: By repeatedly inputting the first time signal and the second time signal into the time-to-digital conversion circuit according to any one of claims 1-6, multiple preliminary time interval quantization results between the first time signal and the second time signal are obtained; The average value of the multiple preliminary time interval quantization results is calculated to obtain the time interval quantization result between the first time signal and the second time signal.