A source follower circuit

Abstract

This invention relates to the field of analog integrated circuit technology and discloses a source follower circuit. The source follower includes an input switch and a current source; the input switch and the current source are electrically connected, and the current source includes at least two switches connected in series; the sampling circuit includes a load capacitor, which is connected in parallel with at least one switch in the current source to form a load loop. This solution improves the bandwidth of the source follower by forming a load loop with the load capacitor connected in parallel with at least one switch in the current source.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and more specifically to a source follower circuit. Background Technology

[0002] A source follower circuit mainly consists of two parts: an input switch and a current source. Source followers are often used as signal buffers in high-speed signal transmission paths, and their bandwidth often limits the bandwidth of the entire signal path.

[0003] To improve the bandwidth of the source follower, existing technologies reduce the current interference of the load circuit on the source follower itself when receiving high-frequency signals by increasing the current of the source follower. This reduces the proportion of the current drawn by the load circuit to the total current of the source follower, slows down the rate of decrease of the source follower gain, and thus increases the bandwidth of the source follower.

[0004] However, increasing the device size of the source follower is necessary to increase the current, but this will result in greater parasitic capacitance, which will limit further bandwidth improvement. Summary of the Invention

[0005] In view of this, the present invention provides a source follower circuit to solve the problem of limited bandwidth improvement in source followers. The technical solution is as follows:

[0006] A source follower circuit is provided, the source follower circuit including a source follower and a sampling circuit;

[0007] The source follower includes an input switch and a current source; the input switch is electrically connected to the current source, and the current source includes at least two switches connected in series.

[0008] The sampling circuit includes a load capacitor connected in parallel with at least one switch in the current source to form a load loop.

[0009] The above scheme forms a load loop by connecting the load capacitor in parallel with at least one switch in the current source. This allows the current drawn by the sampling circuit to be returned to the source follower itself without considering parasitic capacitance. The input switch current is always equal to the sum of the current source current and the sampling circuit current. Therefore, the input switch current does not change with the input signal, and the interference of the current drawn by the load circuit on the current of the source follower itself is smaller, thus improving the bandwidth of the source follower.

[0010] In one possible implementation, the current source includes a first switch and a second switch connected in series. The input switch, the first switch, and the second switch are connected in series in sequence. The first end of the load capacitor is connected to one end of the input switch, and the second end of the load capacitor is connected between the first switch and the second switch.

[0011] The above scheme further defines the structure of the source follower circuit when the current source includes two series-connected switching transistors.

[0012] In one possible implementation, the input switch, the first switch, and the second switch are NMOS transistors; the positive terminal of the source follower is connected to the input switch, the first switch, and the second switch in sequence, and the second switch is grounded.

[0013] The above scheme further defines the structure of the source follower circuit when the input switch, the first switch, and the second switch are NMOS transistors.

[0014] In one possible implementation, the sampling circuit further includes a first switch; the source of the input switch is connected to the first terminal of the load capacitor via the first switch.

[0015] The above scheme uses a first switch to sample whether the circuit is on or off.

[0016] In one possible implementation, the back gate of the first switch is connected to the back gate of the second switch.

[0017] In one possible implementation, the sampling circuit further includes a second switch; the second terminal of the load capacitor is connected between the first switch and the second switch via the second switch.

[0018] The above scheme further defines the structure of the source follower circuit when the sampling circuit is a baseboard sampling circuit.

[0019] In one possible implementation, the input switch, the first switch, and the second switch are PMOS transistors; the positive terminal of the source follower is connected sequentially through the second switch, the first switch, and the input switch, and the input switch is grounded.

[0020] The above scheme further defines the structure of the source follower circuit when the input switch, the first switch, and the second switch are PMOS transistors.

[0021] In one possible implementation, the sampling circuit further includes a first switch; the first terminal of the load capacitor is connected to the source of the input switch transistor via the first switch.

[0022] The above scheme uses a first switch to sample whether the circuit is on or off.

[0023] In one possible implementation, the back gate of the first switch is connected to the back gate of the second switch.

[0024] In one possible implementation, the sampling circuit further includes a second switch; the second terminal of the load capacitor is connected between the first switch and the second switch via the second switch.

[0025] The above scheme further defines the structure of the source follower circuit when the sampling circuit is a baseboard sampling circuit. Attached Figure Description

[0026] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 This illustrates a source follower circuit in the related art;

[0028] Figure 2 This is a schematic diagram of the source follower circuit according to an embodiment of the present invention;

[0029] Figure 3 Another source follower circuit in the related art is shown;

[0030] Figure 4 A schematic diagram of the small-signal equivalent model in related technologies is shown;

[0031] Figure 5 This is a schematic diagram of the small-signal equivalent model according to an embodiment of the present invention;

[0032] Figure 6 This is a schematic diagram of another source follower circuit according to an embodiment of the present invention;

[0033] Figure 7 This is a schematic diagram of the structure of another source follower circuit according to an embodiment of the present invention;

[0034] Figure 8 This illustrates yet another source follower circuit in the related art;

[0035] Figure 9 This is a schematic diagram of another source follower circuit according to an embodiment of the present invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] Source followers are often used as signal buffers in high-speed signal transmission paths. The bandwidth of the source follower often limits the bandwidth of the entire signal path, thus affecting the speed of the entire signal path.

[0038] To improve the bandwidth of a source follower, the mainstream approach is to increase its current to reduce current interference from the load circuit when receiving high-frequency signals. This increases the bandwidth. However, increasing the device size of the source follower is necessary to achieve this increased current, which increases chip power consumption and area. Furthermore, the increased area also increases the parasitic capacitance of the source follower, limiting further bandwidth improvements.

[0039] For example, Figure 1 This diagram illustrates a source follower circuit in the related art, including a source follower and a sampling circuit. The source follower includes an input switch and a current source, while the sampling circuit includes a capacitor and a switch. An NMOS transistor is used as an example of the input switch. When the sampling circuit is off, the current in the input switch equals the current in the current source. When the sampling circuit is on, it draws or releases current from the input switch of the source follower; at this time, the current in the input switch equals the sum of the current in the current source and the current in the sampling circuit. When the input signal V of the input switch... IN When the voltage rises, the potential on the capacitor also rises, which will draw current from the source follower. If the current source of the source follower is an ideal current source, the drawn current will come entirely from the input switch of the source follower, which will increase the current of the input switch, and thus increase the gate-source voltage of the input switch, ultimately resulting in a smaller increase in the capacitor potential; when the input signal V... INWhen the voltage drops, the potential on the capacitor also decreases, which releases current to the source follower. If the tail current source of the source follower is an ideal current source, all the released current will flow into the input switch of the source follower. This will reduce the current of the input switch, and consequently reduce the gate-source voltage of the input switch, ultimately resulting in a smaller drop in the capacitor potential. The higher the frequency of the signal output by the source follower, the greater the current drawn or released by the sampling circuit, and therefore the greater the impact on the current of the input switch of the source follower, leading to a decrease in the high-frequency gain of the source follower. The sampling circuit current is usually the main factor limiting the bandwidth of the source follower. The current of the source follower can be increased to reduce the current interference of the load circuit on the source follower itself when receiving high-frequency signals, thereby improving the bandwidth of the source follower. However, this method increases the chip power consumption and area. In addition, the increase in circuit area will also increase the parasitic capacitance of the source follower itself, which will limit further improvement in bandwidth. Among them, parasitic capacitance generally refers to the capacitive characteristics exhibited by inductors, resistors, chip pins, etc. at high frequencies.

[0040] Therefore, embodiments of the present invention provide a source follower circuit that improves the bandwidth of the source follower by multiplexing the current of the sampling circuit.

[0041] Figure 2 This is a schematic diagram of the source follower circuit according to an embodiment of the present invention. Figure 2 As shown, the source follower circuit includes a source follower and a sampling circuit;

[0042] The source follower includes an input switch M0 and a current source; the input switch M0 is electrically connected to the current source, and the current source includes at least two switches connected in series.

[0043] The sampling circuit includes a load capacitor connected in parallel with at least one switch in the current source to form a load loop.

[0044] In one possible implementation, the current source includes a first switch M1 and a second switch M2 connected in series. The input switch M0, the first switch M1, and the second switch M2 are connected in series in sequence. The first end of the load capacitor is connected to one end of the input switch M0, and the second end of the load capacitor is connected between the first switch M1 and the second switch M2.

[0045] In one possible implementation, the input switch M0, the first switch M1, and the second switch M2 are NMOS transistors; the positive terminal of the source follower is connected to the input switch M0, the first switch M1, and the second switch M2 in sequence, and the second switch M2 is grounded.

[0046] Figure 2 The working principle of the source follower circuit shown is as follows:

[0047] To achieve higher voltage gain at a given supply voltage, the impedance of the load circuit must be as large as possible to maintain a high gain. If the impedance of the load circuit is small, a source follower can be used as a signal buffer to reduce gain loss. A source follower consists of an input switch M0 and a current source. Taking an NMOS transistor as an example, the source follower receives the input signal V at the gate of the input switch M0. IN The source drive load circuit of the input switch M0 allows the source voltage of the input switch M0 to change according to the gate voltage. To increase the impedance of the source follower and obtain a higher voltage gain, this scheme uses at least two switches connected in series to form a common-source, common-gate current source. The load circuit in this scheme is a sampling circuit that includes a load capacitor.

[0048] It should be noted that when the current source includes two or more switching transistors connected in series, the second terminal of the load capacitor can be connected to the source of any one of the switching transistors in the current source.

[0049] Figure 3 Another source follower circuit from the related art is shown. For example... Figure 3 As shown, when the sampling circuit is not conducting, the input switch current equals the current source current. When the sampling circuit is conducting, it draws or releases current from the input switch of the source follower. At this time, the current in the input switch equals the sum of the current source current and the sampling circuit current. The higher the frequency of the signal output by the source follower, the larger the current drawn or released by the sampling circuit, and the larger the proportion of the current drawn by the sampling circuit to the total current of the source follower. This results in a greater decrease in the gain of the source follower. This causes the source follower gain to decrease to DC gain. The signal frequency at that time is the bandwidth of the source follower. To increase the bandwidth, the current of the source follower can be increased. This reduces the proportion of the current drawn by the load circuit to the total current of the source follower, slowing down the drop in the source follower gain and increasing the bandwidth. However, increasing the device size of the source follower is necessary to achieve this increase in current, which in turn introduces larger parasitic capacitance.

[0050] It should be noted that the sampling circuit can be turned on or off by directly connecting or disconnecting the wires, or by setting a corresponding switch; this is not limited here.

[0051] Therefore, this scheme connects the load capacitor in parallel with at least one switch in the current source to form a load loop. Through the load loop, the current drawn by the sampling circuit can be returned to the source follower itself, thus reducing the interference of the current drawn by the load circuit on the current of the source follower and improving the bandwidth of the source follower. Taking a current source consisting of a first switch M1 and a second switch M2 connected in series, where both switches M1 and M2 are NMOS transistors, as an example... Figure 3 The other end of the sampling circuit shown is connected to the source of the common-source cascode transistor (i.e., the first switching transistor M1) of the common-source cascode current source, forming... Figure 2 At this point, the sampling circuit current will flow into or out of the source follower's common-source cascode current source in the opposite direction to the current flowing into or out of the source follower's output terminal (i.e., the source of the input switch M0). The sampling circuit current flowing into or out of the common-source cascode current source will merge with the sampling circuit current flowing into or out of the source follower at the source follower's output terminal; these two currents are equal in magnitude and opposite in direction. Without considering parasitic capacitance, the input switch current is always equal to the sum of the current source current and the sampling circuit current. Therefore, the input switch current does not change with the input signal, allowing the source follower to have a high bandwidth.

[0052] Alternatively, it can be understood from another perspective: the sampling circuit and the cascode current source structure combine to form a closed loop. The sampling circuit current flows out of and back into the cascode current source without passing through the input switch M0. The required sampling circuit current is provided by the sampling circuit current itself, thus achieving the multiplexing of the sampling circuit current. Since the sampling circuit current does not pass through the input switch, the influence of the sampling circuit current on the input switch M0 can be ignored.

[0053] In one possible implementation, the sampling circuit further includes a first switch; the source of the input switch transistor M0 is connected to the first terminal of the load capacitor via the first switch. The sampling circuit can be turned on or off by setting the first switch.

[0054] In one possible implementation, the back gate of the first switch M1 is connected to the back gate of the second switch M2.

[0055] A back-gate structure adds an additional control electrode to the bottom of a MOSFET to further regulate its characteristics. For NMOS transistors, the back-gate potential is no higher than the source potential.

[0056] For example, the source follower circuit in related technologies and the source follower circuit of this solution are analyzed using the small-signal equivalent model. The small-signal equivalent model is a commonly used analysis model in electronic engineering, which uses linear equations to approximate the properties of nonlinear components. Figure 4A schematic diagram of the small-signal equivalent model in related technologies is shown. Figure 5 This is a schematic diagram of the small-signal equivalent model according to an embodiment of the present invention.

[0057] If we disregard the sampling circuit and parasitic capacitance, given a fixed input switch size and bias state, the gain of the source follower depends only on the output impedance of the current source; the higher the current source output impedance, the higher the source follower gain. To quantitatively analyze the impact of this scheme on the source follower bandwidth, we can consider the sampling circuit as part of the current source and study the expression for their total output impedance. For structures in related technologies, ignoring the switch on-resistance, the small-signal equivalent model of the current source and sampling circuit is as follows: Figure 4 As shown, where g m1 r is the transconductance of the first switching transistor M1. o1 For the drain-source small-signal resistor of the first switching transistor M1, g mb1 For the bulk effect transconductance of the first switching transistor M1, r o2 Let be the drain-source small-signal resistance of the second switching transistor M2, C be the capacitance of the load capacitor, and s be the Laplace transform parameter, s = j (imaginary unit) × w (angular frequency), representing the frequency. According to the small-signal model, we can obtain... Figure 4 The expression for the total output impedance of the medium current source and sampling circuit is:

[0058]

[0059] For the structure proposed in this scheme, neglecting the switch conduction impedance, the small-signal equivalent model of the current source and sampling circuit is as follows: Figure 5 As shown. Where g m1 For the transconductance of the first switching transistor M1, r o1 For the drain-source small-signal resistor of the first switching transistor M1, g mb1 For the bulk effect transconductance of the first switching transistor M1, r o2 Let be the drain-source small-signal resistance of the second switching transistor M2, C be the capacitance of the load capacitor, and s be the Laplace transform parameter, s = j (imaginary unit) × w (angular frequency), representing the frequency. According to the small-signal model, we can obtain... Figure 5 The expression for the total output impedance of the medium current source and sampling circuit is:

[0060]

[0061] Comparing the two expressions, we can see that, Figure 4 In the structure shown, the output impedance of the current source and sampling circuit has a very small pole, which causes the output impedance to decrease very rapidly with increasing frequency; while Figure 5 The structure shown has a large pole, which makes the output impedance decrease more slowly with increasing frequency, and Figure 5The structure shown has a zero point, which allows the impedance to increase with frequency. Therefore, in the structure proposed in this solution, the output impedance of the current source and sampling circuit does not change significantly with frequency, thus this patent can effectively improve the bandwidth of the source follower.

[0062] Figure 6 This is a schematic diagram of another source follower circuit according to an embodiment of the present invention. In one possible implementation, the sampling circuit further includes a second switch; the second terminal of the load capacitor is connected between the first switch M1 and the second switch M2 through the second switch.

[0063] like Figure 6 As shown, the sampling circuit in this scheme can also be a base plate sampling circuit. The base plate sampling circuit, i.e., the base plate of the load capacitor (i.e., the second terminal of the load capacitor), is connected to a second switch. When sampling ends, the second switch is opened, causing the base plate of the capacitor to float. The base plate of the capacitor is in a high-impedance state, so the charge in the input switch transistor will not flow into the load capacitor, thus avoiding sampling errors caused by charge injection. The base plate potential of the capacitor can be provided by the source potential of the common-source cascode transistor (i.e., the first switch transistor M1).

[0064] In summary, by connecting the load capacitor in parallel with at least one switch in the current source to form a load loop, the current drawn by the sampling circuit can be returned to the source follower itself without considering parasitic capacitance. The input switch current is always equal to the sum of the current source current and the sampling circuit current. Therefore, the input switch current does not change with the input signal, and the interference of the current drawn by the load circuit on the current of the source follower itself will be smaller, thus improving the bandwidth of the source follower.

[0065] Figure 7 This is a schematic diagram of another source follower circuit according to an embodiment of the present invention. This source follower circuit is... Figure 2 The difference in the source follower circuit shown is that the input switch M0, the first switch M1, and the second switch M2 are PMOS transistors.

[0066] In one possible implementation, the input switch, the first switch, and the second switch are PMOS transistors; the positive terminal of the source follower is connected sequentially through the second switch, the first switch, and the input switch, which is grounded.

[0067] Figure 7 The working principle of the source follower circuit shown is as follows:

[0068] To achieve higher voltage gain at a given supply voltage, the impedance of the load circuit must be as large as possible to maintain a high gain. If the impedance of the load circuit is small, a source follower can be used as a signal buffer to reduce gain loss. A source follower consists of an input switch M0 and a current source. Taking a PMOS transistor as an example, the source follower receives the input signal V at the gate of the input switch M0. IN The source drive load circuit of the input switch M0 allows the source voltage of the input switch M0 to change according to the gate voltage. To increase the impedance of the source follower and obtain a higher voltage gain, this scheme uses at least two switches connected in series to form a common-source, common-gate current source. The load circuit in this scheme is a sampling circuit that includes a load capacitor.

[0069] It should be noted that when the current source includes two or more switching transistors connected in series, the second terminal of the load capacitor can be connected to the source of any one of the switching transistors in the current source.

[0070] Figure 8 Another source follower circuit in the related art is shown. For example... Figure 8 As shown, when the sampling circuit is not conducting, the input switch current equals the current source current. When the sampling circuit is conducting, it draws or releases current from the input switch of the source follower. At this time, the current in the input switch equals the sum of the current source current and the sampling circuit current. The higher the frequency of the signal output by the source follower, the larger the current drawn or released by the sampling circuit, and the larger the proportion of the current drawn by the sampling circuit to the total current of the source follower. This results in a greater decrease in the gain of the source follower. This causes the source follower gain to decrease to DC gain. The signal frequency at that time is the bandwidth of the source follower. To increase the bandwidth, the current of the source follower can be increased. This reduces the proportion of the current drawn by the load circuit to the total current of the source follower, slowing down the drop in the source follower gain and increasing the bandwidth. However, increasing the device size of the source follower is necessary to achieve this increase in current, which in turn introduces larger parasitic capacitance.

[0071] It should be noted that the sampling circuit can be turned on or off by directly connecting or disconnecting the wires, or by setting a corresponding switch; this is not limited here.

[0072] Therefore, this scheme connects the load capacitor in parallel with at least one switch in the current source to form a load loop. Through the load loop, the current drawn by the sampling circuit can be returned to the source follower itself, thus reducing the interference of the current drawn by the load circuit on the source follower's own current and improving the source follower's bandwidth. Taking a current source comprising a first switch M1 and a second switch M2 connected in series, where both switches M1 and M2 are PMOS transistors, as an example... Figure 8The other end of the sampling circuit shown is connected to the source of the common-source cascode transistor (i.e., the first switching transistor M1) of the common-source cascode current source, forming... Figure 7 At this point, the sampling circuit current will flow into or out of the source follower's common-source cascode current source in the opposite direction to the current flowing into or out of the source follower's output terminal (i.e., the source of the input switch M0). The sampling circuit current flowing into or out of the common-source cascode current source will merge with the sampling circuit current flowing into or out of the source follower at the source follower's output terminal; these two currents are equal in magnitude and opposite in direction. Without considering parasitic capacitance, the input switch current is always equal to the sum of the current source current and the sampling circuit current. Therefore, the input switch current does not change with the input signal, allowing the source follower to have a high bandwidth.

[0073] Alternatively, it can be understood from another perspective: the sampling circuit and the cascode current source structure combine to form a closed loop. The sampling circuit current flows out of and back into the cascode current source without passing through the input switch M0. The required sampling circuit current is provided by the sampling circuit current itself, thus achieving the multiplexing of the sampling circuit current. Since the sampling circuit current does not pass through the input switch, the influence of the sampling circuit current on the input switch M0 can be ignored.

[0074] In one possible implementation, the sampling circuit further includes a first switch; the first terminal of the load capacitor is connected to the source of the input switch transistor via the first switch.

[0075] Figure 7 and Figure 8 Small-signal equivalent model analysis of the source follower circuit shown Figure 2 The corresponding content in the embodiments is similar and will not be repeated here.

[0076] In one possible implementation, the back gate of the first switch is connected to the back gate of the second switch. For a PMOS transistor, the back gate potential is not lower than the source potential.

[0077] Figure 9 This is a schematic diagram of another source follower circuit according to an embodiment of the present invention. In one possible implementation, the sampling circuit further includes a second switch; the second terminal of the load capacitor is connected between the first switch M1 and the second switch M2 through the second switch.

[0078] like Figure 9As shown, the sampling circuit in this scheme can also be a base plate sampling circuit. The base plate sampling circuit, i.e., the base plate of the load capacitor (i.e., the second terminal of the load capacitor), is connected to a second switch. When sampling ends, the second switch is opened, causing the base plate of the capacitor to float. The base plate of the capacitor is in a high-impedance state, so the charge in the input switch transistor will not flow into the load capacitor, thus avoiding sampling errors caused by charge injection. The base plate potential of the capacitor can be provided by the source potential of the common-source cascode transistor (i.e., the first switch transistor M1).

[0079] In summary, by connecting the load capacitor in parallel with at least one switch in the current source to form a load loop, the current drawn by the sampling circuit can be returned to the source follower itself without considering parasitic capacitance. The input switch current is always equal to the sum of the current source current and the sampling circuit current. Therefore, the input switch current does not change with the input signal, and the interference of the current drawn by the load circuit on the current of the source follower itself will be smaller, thus improving the bandwidth of the source follower.

[0080] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0081] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A source follower circuit, characterized by, The source follower circuit includes a source follower and a sampling circuit; The source follower includes an input switch and a current source; the input switch is electrically connected to the current source, and the current source includes at least two switches connected in series. The sampling circuit includes a load capacitor and a first switch. The load capacitor is connected in parallel with at least one switch in the current source to form a load loop. The source of the input switch is connected to the first terminal of the load capacitor through the first switch. The current source includes a first switch and a second switch connected in series. The input switch, the first switch, and the second switch are connected in series sequentially. The first end of the load capacitor is connected to one end of the input switch, and the second end of the load capacitor is connected between the first switch and the second switch. When the current source includes two or more switches connected in series, the second end of the load capacitor is connected to the source of any switch in the current source, so that the load capacitor is connected in parallel with at least one switch in the current source to form a load loop, and the current drawn by the sampling circuit is returned to the source follower.

2. The circuit of claim 1, wherein, The input switch, the first switch, and the second switch are NMOS transistors; The positive terminal of the source follower is connected in sequence to an input switch, a first switch, and a second switch, with the second switch grounded.

3. The circuit of claim 2, wherein, The back gate of the first switching transistor is connected to the back gate of the second switching transistor.

4. The circuit of claim 2, wherein, The sampling circuit also includes a second switch; The second terminal of the load capacitor is connected between the first switch and the second switch via the second switch.

5. The circuit according to claim 1, characterized in that, The input switch, the first switch, and the second switch are PMOS transistors; The positive terminal of the source follower is connected in sequence to a second switch, a first switch, and an input switch, and the input switch is grounded.

6. The circuit according to claim 5, characterized in that, The back gate of the first switching transistor is connected to the back gate of the second switching transistor.

7. The circuit according to claim 5, characterized in that, The sampling circuit also includes a second switch; The second terminal of the load capacitor is connected between the first switch and the second switch via the second switch.

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