A server chassis system, a server chassis system design method and equipment

Abstract

The application relates to a server case system, a server case system design method and equipment. The system comprises a first server mainboard, a second server mainboard and a plurality of slots, the number of GPUs arranged on the first server mainboard is greater than the number of GPUs arranged on the second server mainboard; a signal relay device is arranged on the second server mainboard; the signal relay device comprises a first connecting device and a second connecting device, the signal relay device is connected with at least one external general server through the first connecting device, and is connected with the first server mainboard and the second server mainboard through the second connecting device; a power board comprises a plurality of redundant power supplies, a first power board is arranged at the bottom layer of the server case; a second power board is arranged on the first power board; the second power board, the first server mainboard and the second server mainboard are arranged in the same layer. The application can effectively improve the stability of the system, enable stable operation of the server and improve the competitiveness of the server product.

Description

Technical Field

[0001] This application relates to the field of server architecture technology, and in particular to a server chassis system, a server chassis system design method, and a device. Background Technology

[0002] With the development of information technology, servers are being used in more and more scenarios. In addition to high performance, high reliability is an important indicator for measuring servers. Among them, the reliability of the power supply system is particularly important. It can be said that the stability of the power supply system is the foundation for the stable operation of the server.

[0003] The explosive growth in information volume has led to a continuous increase in the number of storage devices and servers—the carriers of information storage and services. This places demands on the space of various data center chassis. Since data center space is difficult to expand further, high-density deployment of storage devices and servers is necessary to fully utilize chassis space. This allows for more blade nodes to be housed in a single rack, but it also places higher demands on the structural space and power supply capacity of the rack's power supply section. To further save rack space, provide sufficient power, and ensure power reliability, this application proposes a server chassis system. Summary of the Invention

[0004] Therefore, it is necessary to provide a server chassis system, server chassis system design method and equipment that can effectively improve system stability and ensure stable operation of the server, in response to the above technical problems.

[0005] To address the aforementioned technical problems, in a first aspect, a server chassis system is provided, the system comprising: The server motherboard includes a first server motherboard, a second server motherboard, and multiple slots. The number of GPUs on the first server motherboard is greater than the number of GPUs on the second server motherboard. The signal relay device is located on the motherboard of the second server; A connection device, comprising a first connection device and a second connection device, wherein a signal relay device is connected to at least one external general-purpose server via the first connection device; The signal relay device is connected to the first server motherboard and the second server motherboard respectively via the second connection device; The power supply board includes multiple redundant power supplies. The power supply board includes a first power supply board and a second power supply board. The first power supply board is located at the bottom of the server chassis. The second power supply board is located on the first power supply board. The second power supply board, the first server motherboard and the second server motherboard are located on the same layer.

[0006] In one embodiment, the signal relay device connects to at least one external general-purpose server via a first connection device, including: The signal relay device communicates with an external general-purpose server via a first connector, or... The signal relay device communicates with an external general-purpose server through a first connector and a network switch.

[0007] In one embodiment, the network switch is a key board of the server, with one end of the network switch connected to a first connector and the other end connected to an external general-purpose server. In one embodiment, the plurality of slots includes a first slot group and a second slot group; the first server motherboard includes a main controller and the first slot group; the second server motherboard includes a plurality of network switches and a plurality of first connection devices.

[0008] In one embodiment, a first slot group on a first server motherboard is connected to a network switch via a second connection device; a second slot group is connected to the network switch via a second connector. The second slot group is located on the outside of the server motherboard and fixed to the inner wall of the server chassis.

[0009] In one embodiment, the server chassis system further includes: a clock generator, a buffer, and a series resistor; the clock generator is located on a first motherboard and is used to receive external clock signals and local clock signals; The series resistor includes a first series resistor and a second series resistor. The first end of the first series resistor is connected to the output of the clock generator, and the second end of the first series resistor is connected to the input of the buffer. The first end of the second series resistor is connected to the output of the clock generator, and the second end of the second series resistor is connected to the first connector. The buffer includes at least a first buffer output terminal and a second buffer output terminal. The first buffer output terminal is connected to a signal relay device, and the second buffer output terminal is connected to multiple slots. The clock signal input to the clock generator is processed by a series resistor to a buffer to obtain the processed clock signal. The processed clock signal is input into the network switch through the output of the first buffer and into multiple slots through the output of the second buffer.

[0010] In one embodiment, the server chassis system further includes a serial communication bus, which includes multiple signal pins. A first signal pin is connected to the controllers of multiple external general-purpose servers via cables, and a second signal pin is connected to multiple GPUs on the server motherboard via a network switch. The serial communication bus is used to collect the chassis temperature, chassis fan speed, and chassis voltage of the server chassis where the server chassis system is located.

[0011] To address the aforementioned technical problems, a second aspect provides a server chassis system design method, the method comprising: Provides a configuration selection interface; In response to obtaining the correspondence between the ID of the first connector and the position information of the first connector, the display device displays the correspondence between the ID of the first connector and the position information of the first connector; Obtain the configuration selected by the user and configure the quantity and specifications of the server motherboard, network switch, and connection devices to match the configuration. Given the number and specifications of server motherboards, network switches, and connection devices, there are multiple options available, and the system automatically selects the option that meets the preset conditions. If the configuration required by the user is not displayed in the configuration selection interface, the user can specify the configuration in the remarks to generate a customized configuration scheme; The server chassis is assembled according to the customized configuration plan, and the feasibility of the server chassis is assessed and verified to ensure the factory quality under the customized configuration requirements.

[0012] In one embodiment, obtaining the correspondence between the ID of the first connector and the location information of the first connector includes: The correspondence between the CDFP ID and CDFP location information can be obtained by reading values ​​via GPIO or I2C.

[0013] To address the aforementioned technical problems, a third aspect provides a server chassis device, including a server chassis body and a server chassis system as described in any of the above embodiments.

[0014] Unlike existing technologies, the server chassis system of this invention includes a first server motherboard and a second server motherboard. A signal relay device is located on the second server motherboard and is connected to at least one external general-purpose server via a first connection device. The signal relay device is also connected to both the first and second server motherboards via a second connection device. Compared to existing technologies that use a single server motherboard to support multiple devices, this application utilizes a structural design where two server motherboards share the burden of multiple devices. By connecting the two server motherboards with connectors and placing the external general-purpose server on the outside of the server chassis, sufficient space is left inside the server chassis to accommodate other devices, thus reducing lateral space. This allows a smaller server chassis to support more devices, facilitating multi-host sharing and allocation of the server. Furthermore, the power board of the server chassis system of this application includes multiple redundant power supplies. The power board is divided into a first power board and a second power board, and the two power boards are stacked together. This allows for the configuration of multiple redundant power supplies within a limited space, improving the reliability of server power supply and achieving high availability of the server system. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the server chassis system in one embodiment; Figure 2 This is a schematic diagram of the server chassis system in another embodiment; Figure 3 This is a schematic diagram of the structure of a network switch in one embodiment; Figure 4 This is a schematic diagram of the clock system structure in one embodiment; Figure 5 This is an internal structural diagram of a server chassis device in one embodiment; Figure 6 This is a flowchart illustrating a server chassis design method in another embodiment.

[0016] Explanation of reference numerals on the accompanying drawings: 102. Chassis; 10. Server motherboard; 11. First server motherboard; 12. Second server motherboard; 13. Signal relay device; 20. Connecting device; 21. First connecting device; 22. Second connecting device; 23. First connector; 24. Second connector; 25. Third connector; 26. Network switch; 30. Power board; 31. First power board; 32. Second power board; 40. Multiple slots; 41. First slot group; 42. Second slot group; 50. Clock generator; 51. First series resistor; 52. Second series resistor; 53. Buffer. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0018] With the continuous advancement of technology, the amount of data is becoming increasingly massive and the amount of computation is becoming increasingly complex. Due to the limitations of Moore's Law, the power wall, and the power consumption wall, the development of processors from single-core to multi-core is accelerating. Accelerators in various fields, such as GPUs and accelerator cards, are constantly emerging, making high-density computing and heterogeneous computing the mainstream of high-performance computing in the future.

[0019] In computing resource pooling, weakening the coupling between processors and GPUs or accelerator cards is an effective way to improve the efficiency of heterogeneous computing. Computing resource pooling requires a large-scale combination of computing units, such as server chassis. A server chassis can be a single computing resource pool or multiple server chassis can be combined. A server chassis does not have a central processing unit; it is a box composed of multiple GPUs or accelerator cards. The GPUs are close together, and when combined with network cards, the computing efficiency in applications with large computing scale and high computing requirements can be improved.

[0020] In current technology, the CPU (Central Processing Unit) and GPU or accelerator card are generally housed in the same server chassis. The GPU or accelerator card is connected to the motherboard via a riser card (adapter card), and most systems use a configuration of two or four cards per machine. However, this type of server chassis design limits the number of GPUs that can be accommodated; furthermore, the GPU occupies a significant amount of internal space in the server chassis, which has a considerable impact on other components within the server chassis.

[0021] To address the aforementioned issues, this application provides a server chassis system comprising: a server motherboard, including a first server motherboard, a second server motherboard, and multiple slots, wherein the first server motherboard has a greater number of GPUs than the second server motherboard; a signal relay device located on the second server motherboard; a connection device including a first connection device and a second connection device, wherein the signal relay device is connected to at least one external general-purpose server via the first connection device; the signal relay device is connected to both the first and second server motherboards via the second connection device; and a power supply board including multiple redundant power supplies, comprising a first power supply board and a second power supply board, wherein the first power supply board is located at the bottom layer of the server chassis; the second power supply board is located on the first power supply board; and the second power supply board, the first server motherboard, and the second server motherboard are arranged on the same layer. Thus, this application enables multi-host shared allocation of the server and achieves high availability of the server system. Example

[0022] In the embodiments of this disclosure, there are such Figure 1 The server chassis system 100 shown includes a chassis 102 for housing various components of the server chassis system 100. The chassis 102 is a standardized frame or enclosure for mounting or installing components such as one or more motherboard assemblies. The server chassis system 100 includes a server motherboard 10 that can be mounted / installed into the chassis 102, and a processor that can be coupled / coupled to the server motherboard 10. The server chassis system 100 also includes multiple signal relay devices 13 mounted on the server motherboard. A connection device 20 connects the server motherboard 10 to an external general-purpose server via the signal relay devices 13. A power board 30 provides all the power required by the server chassis system or network equipment, ensuring the equipment can operate normally.

[0023] Server motherboard 10 includes a first server motherboard 11 and a second server motherboard 12, on which various components of server motherboard 10 are mounted, including multiple slots 40 for configuring processors and heat sinks. The processor can be a GPU, used to perform computationally intensive tasks, enabling high-performance computing and data analysis of big data. The heat sink can be directly coupled to the processor to support its cooling. The number of GPUs on the first server motherboard 11 is greater than the number of GPUs on the second server motherboard 12. For example, if the server motherboard of this disclosure supports 16 GPUs, then the number of GPUs on the first server motherboard can be 6, and the number of GPUs on the second server motherboard can be 10. Compared to the prior art where all GPUs are placed on a single server motherboard, the configuration of this disclosure can also be applied to server chassis with limited space, allowing smaller server chassis to support more servers.

[0024] The second server motherboard 12 also has multiple signal relay devices 13. Optionally, the signal relay device 13 can be a Retimer card. The Retimer card is a signal conditioning chip, which performs signal equalization and enhancement. It is similar to a PHY chip. When the signal passes through the Retimer card, the signal is reconstructed by the clock inside the Retimer card, which can increase the signal transmission energy before continuing transmission, thereby improving the reliability of the server chassis system.

[0025] To support the aforementioned coupling between the server motherboard 10 and external general-purpose devices, this disclosure also includes a connection device 20 and multiple slots. The connection device 20 includes a first connection device 21 and a second connection device 22. The first connection device 21 includes multiple first connectors 23, and the second connection device 22 includes a second connector 24 and a third connector 25. For example, the first connector 23 can be an x16 CDFP connector, the second connector 24 can be a connector with a bandwidth of x32, and the third connector 25 can be an MCID connector. Of course, the connectors in this disclosure can be other types of connectors, and can be configured according to actual needs.

[0026] The multiple slots 40 include a first slot group 41 and a second slot group 42. The first slot group 41 is located on the first server motherboard 11, and the second slot group 42 is located on the outside of the server motherboard 10, fixed to the inside of the server chassis near the server fan. Compared with the conventional method of placing slots on the server motherboard 10, in this application, some slots in the server chassis system are located on the outside of the server motherboard 10, which is beneficial to increasing the density of GPU deployment on the server motherboard 10 and improving heat dissipation.

[0027] In a specific implementation, the first slot group 41 is used to configure multiple processors, which can be understood as one slot corresponding to one processor. The multiple processors are connected to multiple signal relay devices 13 on the second server motherboard 12 via the second connector 24, and the signal relay devices 13 are connected to at least one external general-purpose server via the first connection device 21.

[0028] The second slot group 42 is connected to a plurality of signal relay devices 13 on the second server motherboard 12 via a third connector 25, and the signal relay devices 13 are in turn connected to at least one external general-purpose server via a first connection device 21.

[0029] In other words, by placing multiple GPU chips on two server motherboards and connecting them via a second connector 24, the topology design of the connection device becomes more flexible, increasing the available space in the server chassis. Furthermore, by utilizing two server motherboards to share the structural design of multiple GPUs and connecting them via a connector, the horizontal space is reduced, significantly decreasing the horizontal size of a single server motherboard. For servers with chassis heights of 4U or less, this also reduces the maintenance costs of bridges and bridging cables.

[0030] The power supply board 30 is equipped with multiple redundant power supplies. The power supply board 30 includes a first power supply board 31 and a second power supply board 32. The first power supply board 31 is located at the bottom of the server chassis, and the second power supply board 32 is located on the first power supply board 31; the second power supply board 32, the first server motherboard 11 and the second server motherboard 12 are located on the same layer.

[0031] In this context, redundant power supplies can specifically be gel batteries. Redundant power supplies, used in servers, consist of two identical power supplies controlled by a chip for load balancing. When one power supply fails, the other immediately takes over. After a power supply replacement, the two power supplies work together again. Redundant power supplies are used to achieve high availability for server systems.

[0032] For example, in one embodiment, the server chassis architecture is designed to be divided into three layers: upper layer, middle layer, and lower layer.

[0033] The first power board is located on the lower layer of the server chassis, the second power board 32 and the first server motherboard 11 are located on the middle layer of the server chassis, and the upper layer of the server chassis includes the server's PSU (hot-swappable unit, etc.). The hot-swappable unit allows for the insertion or removal of hot-swappable peripheral devices without turning off the power, without causing the host or peripheral devices to burn out, and can detect and run new devices in real time.

[0034] For example, such as Figure 2 As shown, taking a standalone 4U high server chassis as an example, in a specific implementation, the first power supply board at the bottom of the server chassis may include four redundant power supplies, each 1U in height. Optionally, a first server motherboard 11 and a second server motherboard 12 can be placed on either side of the middle layer of the server chassis, forming a space between the first server motherboard 11 and the second server motherboard 12. This space can accommodate a second power supply motherboard 32. The structure of the second power supply board 32 shown in the figure consists of two stacked 1U high redundant power supplies. The upper layer of the server chassis includes hot-swappable components, etc. In this implementation, 3+3 power supply redundancy can be achieved, ensuring the server continues to operate normally even if any three redundant power supplies fail. This significantly improves the reliability of server operation.

[0035] It is understood that the server chassis architecture described in this application can also be used in server chassis of 6U, 8U height, etc.

[0036] In typical server power supplies, 1U power supplies generally employ a non-redundant structure, while the improved 1U power supply uses multiple redundant power supplies. This allows for improved server power supply reliability within a limited space, and the high-density power supply design increases the power supply's energy density, providing greater power output within a confined space.

[0037] With the development of artificial intelligence, deep learning is being applied more and more widely in the field of AI, and the demand for GPU (Graphics Processing Unit) server chassis in the application market is increasing. Therefore, server chassis design has become a hot project. Server chassis integrate a large number of GPU modules for processing and computing large amounts of data, and have superior performance. However, in current technology, general-purpose servers are usually directly connected to AIC cards. This method has a simpler system topology, but it cannot achieve multi-host sharing and dynamic allocation for scaling.

[0038] In a preferred embodiment, this application further includes a network switch 26, which is a key board of the server. The first end of the network switch 26 is connected to the first connector 23, and the second end of the network switch 26 is connected to an external general-purpose server. The signal relay device 13 can communicate with the external general-purpose server through the first connector 21 and the network switch 26.

[0039] Specifically, the network switch 26 can be a PCIe switch chip. The main function of the PCIe switch chip is to extend the PCIe signals transmitted from the computing node to enable interconnection and management of the GPU board, and at the same time, to expand four standard PCIe slots for connecting network cards and other PCIe devices. The PCIe switch chip can expand one x8 bandwidth PCIe port into four x2 PCIe ports, each of which can connect EPs (network cards, graphics cards, etc.). In addition, the PCIe bus can also use a PCIe bridge to convert the PCIe bus to a PCI bus or a PCI-X bus, and then connect PCI or PCI-X devices.

[0040] In one specific implementation, the signal relay device 13 on the second server motherboard 12 can be connected to the network switch 26 via the first connector 23, and then connected to an external general-purpose server via the network switch 26. The network switch 26 can expand external ports, thereby connecting more external devices to achieve dynamic allocation of shared multi-host machines.

[0041] Preferably, the network switch 26 and the external general-purpose server are both located outside the server chassis. This allows sufficient space inside the server chassis to accommodate other devices, such as power supply boards.

[0042] The network switch 26 of this application is connected to the general server (Host end) and the device end respectively, and the network switches 26 are interconnected to form a resource pool of multiple devices. Through the tree-like, network structure topology or redundant topology of PCIe Switch cascading, the general server can be expanded and interconnected.

[0043] For example, in the embodiments of this disclosure, there are such Figure 2 The network switch structure shown in this disclosure forms a network topology through network switches 26 (PCIe Switch chips) in fabric topology mode, thereby forming a PCIe resource pool. This allows the CPU to call all PCIe resources under the Switch after each resource is released, enabling resource mutual calling between PCIe Switches mounted under multiple CPUs.

[0044] Specifically, such as Figure 3 As shown, the network switch 26 adopts a two-level network switch design. The first-level network switch includes network switch 0, network switch 1, network switch 2, and network switch 3. The second-level network switch includes network switch 4, network switch 5, network switch 6, and network switch 7. The uplink ports of the first-level network switches are connected to multiple external general-purpose servers, and the downlink ports of the second-level network switches are connected to multiple GPUs on the motherboard of the first server. Furthermore, each network switch between the first and second network switches is interconnected, allowing the devices connected to the network switches to form a resource pool, enabling resource sharing between the network switch chips connected to multiple external general-purpose servers.

[0045] The connection between network switches can be via the I2C bus, which enables the interconnection of network switches in pairs. This allows for the initialization, linking, detection, enumeration, and registration of devices mounted on the downlink ports of the network switches, providing a non-continuous load / store interface for the devices mounted on the downlink ports.

[0046] Through the above implementation method, after all the device ends form a resource pool (in the figure, the PCIE Switch is multiple PCIE Switch modules interconnected), each device end can be called by the host end through the PCIE Switch module, and a host end can call multiple device ends at the same time.

[0047] In one embodiment, the server chassis system of this disclosure further includes: a clock generator and a buffer; the buffer includes at least a first buffer output terminal and a second buffer output terminal; the clock generator inputs a clock signal to the buffer for processing to obtain a processed clock signal; the processed clock signal is output to a network switch through the first buffer output terminal and to multiple slots through the second buffer output terminal.

[0048] Please see Figure 4 This disclosure contains the following: Figure 4 The clock system shown mainly includes a clock generator 50, a series resistor, and a buffer 53.

[0049] Clock generator 50 can receive both external clock signals and local clock signals. For example, the external clock signal on the server motherboard and the local clock signal on the processor are connected to the input of the clock generator. The output of clock generator 50 is used to output the clock signal for the PCIe bus. For example, the clock outputs for multiple PCIe buses can be 100MHz. The clock generator can be a clock generator conforming to the CK440 specification, specifically the 9SQ440 model. This model conforms to the PCIe Gen5 standard and features 20 differential outputs and excellent jitter performance—less than 50 fs RMS PCIe Gen5 universal clock phase jitter—to meet the clock requirements of various topologies, from simple single-board dual-slot systems to complex modular multi-slot systems, providing customers with greater design flexibility and margin.

[0050] The series resistor includes a first series resistor 51 and a second series resistor 52. The first end of the first series resistor 51 is connected to the output end of the clock generator 50, and the second end of the first series resistor 51 is connected to the input end of the buffer 53. The first end of the second series resistor 52 is connected to the output end of the clock generator 50, and the second end of the second series resistor 52 is connected to the first connector 23. Buffer 53 includes at least a first buffer output terminal and a second buffer output terminal. The output terminal of clock generator 50 can be connected to the first terminal of first series resistor 51, the second terminal of first series resistor 51 is connected to the input terminal of buffer, the first buffer output terminal is connected to signal relay device 13, and the second buffer output terminal is connected to multiple slots. When multiple slots are configured with multiple processors, the second buffer output terminal of buffer 53 is connected to multiple processors and can receive local clock signals. It is understood that the number of processors in this disclosure can be expanded according to the actual needs of connecting the required number of processors.

[0051] Optionally, the first series resistor 51 and the second series resistor 52 can be series resistors of the same model or series resistors of different models.

[0052] Preferably, the first series resistor 51 can be a 0-ohm series resistor, and the second series resistor 52 can be an EMPTY series resistor. By soldering series resistors on the clock link, when the signal source impedance is low and mismatched with the signal line, adding series resistors can improve the matching situation and avoid oscillation. Furthermore, the series resistors can form a loop with the distributed capacitance of the signal line and the input capacitance of the load, which can reduce the steepness of the signal edge, thereby reducing high-frequency noise and overshoot.

[0053] For example, buffer 53 can be a buffer chip. Through the frequency replication function of the buffer chip, a point-to-point topology can be achieved, which can effectively solve the signal integrity problem and achieve the best cost performance.

[0054] Understandably, the clock selector 50 can be connected to the main controller of the first motherboard of the server chassis system and controlled by hardware such as configuration jumpers, or by software such as control modules. For example, it can be controlled by outputting GPIO through the CPLD, and the first connector can control the clock selector by writing a program to output GPIO.

[0055] Please see Figure 5 ,like Figure 5 As shown, the server chassis system 100 of this disclosure includes a server chassis body 102 and is applied in the server chassis system 100 of the above-described embodiments. Example

[0056] In one embodiment, such as Figure 6 As shown, a server chassis design method 200 is provided, which can be applied to the design process of the server chassis system 100 as described in the first aspect above, including: S210: Provides a configuration selection interface; In this embodiment, since different user groups require different configurations of the server chassis system 100, in order to facilitate the configuration selection of each user, the various configurations that users may choose are evaluated and their feasibility verified in the early stage of design, and the verified feasible configurations are provided to the configuration selection interface, so as to meet the configuration needs of users and facilitate the assembly and delivery of products in the later stage, saving subsequent production time.

[0057] S220: In response to obtaining the correspondence between the ID of the first connector and the position information of the first connector, the display device displays the correspondence between the ID of the first connector and the position information of the first connector.

[0058] In this embodiment, a configuration scheme can be automatically generated based on the configuration selected by the user in the configuration selection interface. This scheme includes the quantity and specifications of server motherboard 10, signal relay device 13, connection device, power board 30, network switch 26, and other components such as cables that match the required configuration. This makes it easier for production personnel to assemble and produce the target server chassis system 100 directly according to the automatically generated configuration scheme, thereby improving assembly and production efficiency.

[0059] Meanwhile, when there are multiple options for the quantity and specifications of some hardware (such as server motherboard 10, signal relay device 13, connection device, power board 30, network switch 26, etc.), the system can automatically select the option that meets preset conditions and generate the corresponding configuration scheme. The preset conditions can be cost conditions or host maximization conditions, that is, when multiple options exist, the option with the lower cost can be selected to generate the configuration scheme; or the preset conditions can be host maximization conditions, that is, when multiple options exist, the option that can configure more hosts can be selected to generate the configuration scheme. It is understood that the above preset conditions can also be other conditions, such as weight, size, etc., which can be adjusted according to actual conditions and are not limited in this embodiment.

[0060] S230: Obtain the configuration selected by the user and configure the quantity and specifications of the server motherboard, network switch, and connection devices.

[0061] S240: In response to the availability of multiple options for the number and specifications of server motherboards, network switches, and connection devices, it automatically selects the option that meets the preset conditions.

[0062] S250: If the configuration required by the user is not presented in the configuration selection interface, the user can specify the configuration in the remarks to generate a customized configuration scheme.

[0063] In practical applications, when users make configuration selections, some hardware that the user needs may not be provided in the configuration selection interface, and the user does not want to replace it with other equivalent hardware. In this case, the user can choose to make a note of the hardware requirement so that the designer can understand the user's real needs and meet the customer's configuration requirements, thereby satisfying the user's diverse needs.

[0064] S260: Assemble server chassis according to customized configuration schemes and conduct feasibility assessments and verifications of the server chassis to ensure factory quality under customized configuration requirements.

[0065] In one embodiment, the server design method 200 may further include a development engineer conducting a preliminary evaluation based on the user-specified configuration, i.e., evaluating whether the specified hardware is compatible with other existing hardware to ensure the stability of the server chassis system 100. After the development engineer conducts the preliminary evaluation, a customized configuration scheme can be generated by matching hardware such as cables that meet the compatibility requirements, to facilitate subsequent assembly and production.

[0066] In this embodiment, by assembling the server chassis system 100 according to the generated configuration scheme, assembly and production time can be effectively saved and production efficiency can be improved.

[0067] In one embodiment, the server chassis system 100 may further include a serial communication bus, which includes multiple signal pins. A first signal pin is connected via a cable to the controllers of multiple external general-purpose servers, and a second signal pin is connected via a network switch to multiple GPUs on the server motherboard. The serial communication bus is used to collect data on the chassis temperature, chassis fan speed, and chassis voltage of the server chassis where the server chassis system is located. The main controller (BMC) on the first server motherboard 11 obtains the correspondence between the CDFP ID and CDFP location information through GPIO or I2C read values, and can monitor and manage the server chassis temperature, fan speed, and voltage via the I2C bus, while simultaneously monitoring the GPU's operating status.

[0068] Specifically, the first connector 23 is equipped with an I2C bus that connects to the I / O interface on the signal relay device 13, which is connected to the I2C bus of the external general-purpose server. The I / O interface serves as the link for information exchange between the host and the controlled object. The host exchanges data with external devices through the I / O interface. The local I2C bus of the server chassis is also connected to the I / O interface of the signal relay device 13. Each signal relay device has multiple I / O interfaces. The controller of the external general-purpose server reads the ID value of each I / O interface on each signal relay device through the I2C bus. The ID value reveals the location and attribute information of each first connector connected to each I / O interface of the signal relay device 13. By establishing the correspondence between each first connector and the external general-purpose server, the correspondence between the external general-purpose server and each I / O interface on the signal relay device 13 is obtained. The controller of the external general-purpose server then uploads this correspondence to the main server on the local server chassis system. It should be noted that each processor on the server chassis system corresponds to a first connector. By obtaining the correspondence between each processor and each first connector, as well as the correspondence between the external general server and each I / O interface on the signal relay device 13, out-of-band management of the processor can be achieved.

[0069] In practical applications, the high and low level signals of each I / O interface on each signal relay device can be obtained by reading GPIO or I2C values.

[0070] GPIO (General Purpose Input / Output Port) refers to a series of pins on a chip. When used as input ports, they allow us to read the pin's state—high or low. When used as output ports, they allow us to output high or low levels to control connected external devices. GPIO readings can be performed using the system's built-in GPIO driver, eliminating the need for independent development and saving costs.

[0071] In another implementation, the high and low level signals of each I / O interface on each signal relay device can be read via I2C. Specifically, the response signal of each I / O interface on each signal relay device can be obtained through the I2C driver chip connected to the motherboard; by parsing each interface response signal, an array corresponding to each I / O interface on each signal relay device can be obtained.

[0072] I2C is a very common communication protocol. It is applied through an I2C driver chip. I2C consists of two bidirectional signal lines: a data line (SDA) and a clock line (SCL). The CPU uses the serial clock line to generate a clock signal and the serial data line to send or receive data. Data transmission on the SDA line is big-endian (most significant byte first), transmitting 8 bits (1 byte) at a time. The I2C protocol has good portability; even in different devices, as long as they conform to the protocol, they can be driven by the same set of code. For example, reading values ​​through I2C can result in 0111 0000; 0111 0001; 0111 0010; etc., which correspond to an array for each interface. These arrays can be assigned to the first connector as first connector-0, first connector-1, first connector-2, etc., thus establishing the correspondence between each I / O interface connection and each first connector in each signal relay device 13.

[0073] In one feasible implementation, the I2C protocol can also be implemented using an FPGA to manage the server chassis system. Simultaneously, the FPGA controls the power-on and power-off sequence of the entire server chassis, and provides external interface signals via connectors, including a power-on signal (PWR_en), a power-on completion signal (PWR_ok), a reset signal (Reset), and other signals (MISC), to achieve system integration with external general-purpose servers.

[0074] In the above implementation, implementing the I2C protocol through an FPGA has the advantages of high bandwidth and low latency, and the FPGA can use parallel processing technology to improve execution efficiency.

[0075] In one embodiment, the server chassis system 100 further includes a temperature acquisition module, a voltage detection module, a server fan module, etc. The server chassis temperature, fan speed, and voltage are monitored and managed via an I2C bus, while the GPU's operating status is also monitored.

[0076] Let's take the temperature monitoring of a server chassis as an example: In one embodiment, the temperature acquisition module can be located at the front end of the first motherboard. The front end of the first motherboard can be the air intake of the motherboard, and the copper plating and traces on the motherboard position where the temperature acquisition module is placed can be removed to prevent heat from other components from being conducted to the temperature acquisition module and affecting the measurement accuracy. The temperature acquisition module is installed at this position. The temperature acquisition module is connected to the BMC chip through the I2C channel and transmits raw data to the BMC chip. The BMC chip performs data correction, thereby improving the accuracy of temperature detection.

[0077] Specifically, the temperature acquisition module can acquire the real-time operating temperature of various components in the server chassis system, such as the processor and network switch on the first motherboard, during operation. The I2C bus can determine whether the current operating temperature is within the normal operating temperature range of the server chassis system based on this operating temperature. If the real-time operating temperature of a certain component is not within the normal operating temperature range of the server chassis system, the location information of the component is acquired, an alarm message is issued, and it is displayed on the configuration interface.

[0078] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A server chassis system, characterized in that, The system includes: The server motherboard includes a first server motherboard, a second server motherboard, and multiple slots. The number of GPUs installed on the first server motherboard is greater than the number of GPUs installed on the second server motherboard. The multiple slots include a first slot group and a second slot group. Multiple signal relay devices, which are located on the motherboard of the second server; A connecting device, the connecting device including a first connecting device and a second connecting device, the first connecting device including a plurality of first connectors, and the second connecting device including a second connector and a third connector; A power supply board, comprising multiple redundant power supplies, including a first power supply board and a second power supply board, wherein the first power supply board is disposed at the bottom layer of the server chassis; the second power supply board is disposed on the first power supply board; the second power supply board, the first server motherboard, and the second server motherboard are disposed on the same layer. The first slot group is located on the first server motherboard and is used to configure multiple processors. The multiple processors are connected to multiple signal relay devices on the second server motherboard through a second connector. The second slot group is located on the outside of the server motherboard and fixed to the inner wall of the server chassis. The second slot group is connected to multiple signal relay devices on the second server motherboard through a third connector. Multiple signal relay devices communicate with multiple external general-purpose servers through a first connector and multiple network switches, with each signal relay device corresponding to a first connector, network switch, and external general-purpose server.

2. The system according to claim 1, characterized in that, The server chassis system also includes: a clock generator, a buffer, and a series resistor; The clock generator is located on the first motherboard and is used to receive external clock signals and local clock signals; The series resistor includes a first series resistor and a second series resistor. A first end of the first series resistor is connected to the output terminal of the clock generator, and a second end of the first series resistor is connected to the input terminal of the buffer. A first end of the second series resistor is connected to the output terminal of the clock generator, and a second end of the second series resistor is connected to a first connector. The buffer includes at least a first buffer output terminal and a second buffer output terminal, wherein the first buffer output terminal is connected to a signal relay device and the second buffer output terminal is connected to multiple slots; The clock generator input clock signal is processed by the buffer through the series resistor to obtain the processed clock signal; The processed clock signal is input into the network switch through the output of the first buffer and into multiple slots through the output of the second buffer.

3. The system according to claim 1, characterized in that, The server chassis system also includes a serial communication bus, which includes multiple signal pins. The first signal pin is connected to the controllers of multiple external general-purpose servers via cables, and the second signal pin is connected to multiple GPUs on the server motherboard via a network switch. The serial communication bus is used to collect the chassis temperature, chassis fan speed, and chassis voltage of the server chassis where the server chassis system is located.

4. A server chassis system design method, characterized in that, Applied to any one of the server chassis systems as described in claims 1-3, the method comprises: Provides a configuration selection interface; In response to obtaining the correspondence between the ID of the first connector and the position information of the first connector, the display device displays the correspondence between the ID of the first connector and the position information of the first connector; Obtain the configuration selected by the user, which matches the quantity and specifications of the server motherboard, the network switch, and the connection device; In response to the existence of multiple options for the number and specifications of the server motherboard, the network switch, and the connection device, the option that meets the preset conditions is automatically selected; If the configuration required by the user is not presented in the configuration selection interface, the user can specify the configuration in the remarks to generate a customized configuration scheme; Assemble the server chassis according to the customized configuration scheme and conduct a feasibility assessment and verification of the server chassis to ensure the factory quality under the customized configuration requirements.

5. The method according to claim 4, characterized in that, The step of responding to obtaining the correspondence between the ID of the first connector and the location information of the first connector includes: The correspondence between the CDFP ID and CDFP location information can be obtained by reading values ​​via GPIO or I2C.

6. A server chassis device, characterized in that, The server chassis device includes a server chassis body and a server chassis system as described in any one of claims 1-3.

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