Method, apparatus, operating system, device and storage medium for interrupt virtualization

Abstract

The embodiment of the present application provides a kind of interrupt virtualization method, device, operating system, equipment and storage medium, the method comprises: when hypervisor injects virtual interrupt to first virtual machine, in the physical CPU of running first virtual machine, select a free virtual interrupt register as the virtual interrupt register of the virtual interrupt, and first virtual machine is any virtual machine running on hypervisor;When storing virtual interrupt information in the selected virtual interrupt register, set the indication information that does not generate maintenance interrupt, so that first virtual machine does not generate maintenance interrupt when processing the virtual interrupt;When first virtual machine traps into hypervisor and first virtual machine has been handled and completed the virtual interrupt, hypervisor clears the content in the selected virtual interrupt register.The technical scheme of the present application does not generate maintenance interrupt when the virtual interrupt injected to virtual machine is responded each time, thereby reducing the number of times of generating maintenance interrupt, and improving the efficiency of interrupt virtualization.

Description

Technical Field

[0001] This invention relates to the field of operating systems, and more particularly to a method, apparatus, operating system, device, and storage medium for interrupt virtualization. Background Technology

[0002] Currently, in computer virtualization solutions, the interrupts received by the virtual machine are usually virtual interrupts. That is, after a physical interrupt occurs, it is first processed by the hypervisor, and then a virtual interrupt is injected into the virtual machine before the virtual machine can receive the virtual interrupt and process it.

[0003] However, during this process, the hypervisor not only receives the first physical interrupt, but also a maintenance interrupt when the virtual machine responds to the virtual interrupt. This maintenance interrupt clears the List register written when the virtual interrupt is injected. Thus, every time a physical interrupt is generated, an additional maintenance interrupt is generated, increasing the number of interrupts and reducing the efficiency of interrupt virtualization. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a method, apparatus, operating system, device, and storage medium for interrupt virtualization scenarios in virtualized operating systems. By setting an indication message in the selected virtual interrupt register to prevent maintenance interrupts from being generated, the virtual machine does not generate maintenance interrupts when processing virtual interrupts. Compared to the prior art where the virtual machine generates an additional maintenance interrupt when processing virtual interrupts, the technical solution of the present invention does not generate a maintenance interrupt every time the virtual interrupt injected into the virtual machine is responded to, thereby reducing the number of maintenance interrupts and improving interrupt virtualization efficiency.

[0005] In a first aspect, embodiments of the present invention provide a method for interrupt virtualization, comprising: when a hypervisor injects a virtual interrupt into a first virtual machine, selecting an idle virtual interrupt register in the physical CPU running the first virtual machine as the virtual interrupt register for the virtual interrupt, wherein the first virtual machine is any virtual machine running on the hypervisor; when storing virtual interrupt information in the selected virtual interrupt register, setting an indication message not to generate a maintenance interrupt, so that the first virtual machine does not generate a maintenance interrupt when processing the virtual interrupt; when the first virtual machine is trapped in the hypervisor and the first virtual machine has completed processing the virtual interrupt, the hypervisor clears the contents of the selected virtual interrupt register.

[0006] As described above, by setting an indication message in the selected virtual interrupt register to prevent maintenance interrupts from being generated, the virtual machine will not generate maintenance interrupts when processing virtual interrupts, thereby reducing the number of maintenance interrupts and improving the efficiency of interrupt virtualization.

[0007] In one possible implementation of the first aspect, when the first virtual machine enters the hypervisor and has completed processing the virtual interrupt, the hypervisor clears the contents of the selected virtual interrupt register, including: when the first virtual machine enters the hypervisor, the hypervisor queries the status of the virtual interrupt register in the physical CPU, clears the contents of the inactive virtual interrupt register, and makes it an idle virtual interrupt register, wherein the virtual interrupt corresponding to the inactive virtual interrupt register has been completed.

[0008] Therefore, by clearing the contents of all inactive virtual interrupt registers when trapped in the hypervisor for any reason, the virtual interrupt registers are made free and can be used by subsequent new virtual interrupt injections.

[0009] In one possible implementation of the first aspect, the sources of the virtual interrupts injected by the hypervisor into the first virtual machine include at least one of the following: physical interrupts that need to be processed by the first virtual machine; virtual interrupts generated by the first virtual machine that need to be processed by itself; and inter-core interrupts generated by other virtual machines that need to be processed by the first virtual machine.

[0010] Therefore, the embodiments of the present invention provide virtual interrupts suitable for various sources.

[0011] In one possible implementation of the first aspect, it further includes: when the number of virtual interrupts written in the physical CPU running the first virtual machine is equal to the number of virtual interrupt registers of the physical CPU, setting indication information for generating a maintenance interrupt in the selected virtual interrupt register, so that the first virtual machine generates a maintenance interrupt when processing the virtual interrupt, wherein the number of writes is the number of virtual interrupts that the first virtual machine has not completed processing and whose information has been written to the corresponding virtual interrupt register of the physical CPU.

[0012] As described above, by setting an indication message for generating a maintenance interrupt in the selected virtual interrupt register when the number of virtual interrupts written in the physical CPU running the first virtual machine is equal to the number of virtual interrupt registers of that physical CPU, the last idle or inactive virtual interrupt register can be maintained in a timely manner, so that subsequent virtual interrupts can be injected in a timely manner.

[0013] In one possible implementation of the first aspect, when the first virtual machine is not running, the virtual interrupt register of the physical CPU running the first virtual machine is stored in the data structure of the context of the first virtual machine, and the operation on the virtual interrupt register of the physical CPU running the first virtual machine during virtual interrupt injection is an operation on the data structure corresponding to the context of the first virtual machine.

[0014] As described above, by manipulating the data structure corresponding to the virtual interrupt register of the physical CPU running the first virtual machine stored in the context of the first virtual machine, the virtual interrupt injection of the present invention can be performed even when the first virtual machine is not running.

[0015] In one possible implementation of the first aspect, when the hypervisor runs on an ARM-based chip, the virtual interrupt register is the List register.

[0016] As described above, the technical solution of this invention utilizes the List register of an ARM-based chip to implement the virtual interrupt register, resulting in a simpler implementation.

[0017] Secondly, embodiments of the present invention provide an interrupt virtualization apparatus, comprising: a register selection module, configured to select an idle virtual interrupt register as the virtual interrupt register of the physical CPU running the first virtual machine when the hypervisor injects a virtual interrupt into the first virtual machine, wherein the first virtual machine is any virtual machine running on the hypervisor; a maintenance interrupt setting module, configured to set an indication message not to generate a maintenance interrupt when storing virtual interrupt information in the selected virtual interrupt register, so that the first virtual machine does not generate a maintenance interrupt when processing the virtual interrupt; and a register content clearing module, configured to clear the contents of the selected virtual interrupt register when the first virtual machine is trapped in the hypervisor and the first virtual machine has completed processing the virtual interrupt.

[0018] As described above, by setting an indication message in the selected virtual interrupt register to prevent maintenance interrupts from being generated, the virtual machine will not generate maintenance interrupts when processing virtual interrupts, thereby reducing the number of maintenance interrupts and improving the efficiency of interrupt virtualization.

[0019] In one possible implementation of the second aspect, the register content clearing module is specifically used to, when the first virtual machine is trapped in the hypervisor, query the status of the virtual interrupt register in the physical CPU, clear the contents of the inactive virtual interrupt register, and make it an idle virtual interrupt register, wherein the virtual interrupt corresponding to the inactive virtual interrupt register has been processed.

[0020] Therefore, by clearing the contents of all inactive virtual interrupt registers when trapped in the hypervisor for any reason, the virtual interrupt registers are made free and can be used by subsequent new virtual interrupt injections.

[0021] In one possible implementation of the second aspect, the sources of the virtual interrupts injected by the hypervisor into the first virtual machine include at least one of the following: physical interrupts that need to be processed by the first virtual machine; virtual interrupts generated by the first virtual machine that need to be processed by itself; and inter-core interrupts generated by other virtual machines that need to be processed by the first virtual machine.

[0022] Therefore, the embodiments of the present invention provide virtual interrupts suitable for various sources.

[0023] In one possible implementation of the second aspect, the maintenance interrupt setting module is further configured to set an indication message for generating a maintenance interrupt in a selected virtual interrupt register when the number of virtual interrupts written in the physical CPU running the first virtual machine is equal to the number of virtual interrupt registers of the physical CPU, so that the first virtual machine generates a maintenance interrupt when processing the virtual interrupt, wherein the number of writes is the number of virtual interrupts that the first virtual machine has not completed processing and whose information has been written to the corresponding virtual interrupt register of the physical CPU.

[0024] As described above, by setting an indication message for generating a maintenance interrupt in the selected virtual interrupt register when the number of virtual interrupts written in the physical CPU running the first virtual machine is equal to the number of virtual interrupt registers of that physical CPU, the last idle or inactive virtual interrupt register can be maintained in a timely manner, so that subsequent virtual interrupts can be injected in a timely manner.

[0025] In one possible implementation of the second aspect, when the first virtual machine is not running, the virtual interrupt register of the physical CPU running the first virtual machine is stored in the data structure of the context of the first virtual machine. When a virtual interrupt is injected, the operation on the virtual interrupt register of the physical CPU running the first virtual machine is an operation on the data structure corresponding to the context of the first virtual machine.

[0026] As described above, by manipulating the data structure corresponding to the virtual interrupt register of the physical CPU running the first virtual machine stored in the context of the first virtual machine, the virtual interrupt injection of the present invention can be performed even when the first virtual machine is not running.

[0027] In one possible implementation of the second aspect, when the hypervisor runs on an ARM-based chip, the virtual interrupt register is the List register.

[0028] As described above, the technical solution of this invention utilizes the List register of an ARM-based chip to implement the virtual interrupt register, resulting in a simpler implementation.

[0029] Thirdly, embodiments of the present invention provide an operating system, wherein when a program included therein is executed by a computer, the computer performs any of the methods described in the first aspect.

[0030] Fourthly, embodiments of the present invention provide a computing device, comprising: a bus; a communication interface connected to the bus; at least one processor connected to the bus; and at least one memory connected to the bus and storing program instructions, which, when executed by the at least one processor, cause the at least one processor to perform any of the embodiments described in the first aspect of the present invention.

[0031] Fifthly, embodiments of the present invention provide a computer-readable storage medium having program instructions stored thereon, which, when executed by a computer, cause the computer to perform any of the embodiments described in the first aspect of the present invention. Attached Figure Description

[0032] Figure 1 This is a flowchart illustrating a method for interrupting virtualization according to the present invention.

[0033] Figure 2A This is a schematic diagram illustrating the process of virtual interrupt injection and processing when the virtual interrupt register includes an indication message for generating a maintenance interrupt.

[0034] Figure 2B This is a schematic diagram illustrating the process of virtual interrupt injection and processing corresponding to the indication information that does not generate maintenance interrupts in the virtual interrupt register according to the present invention;

[0035] Figure 3 This is a flowchart illustrating a second embodiment of the method for interrupting virtualization according to the present invention;

[0036] Figure 4 This is a schematic diagram of a first embodiment of the device for interrupting virtualization according to the present invention;

[0037] Figure 5 This is a schematic diagram of a second embodiment of the device for interrupting virtualization according to the present invention;

[0038] Figure 6 This is a schematic diagram of the structure of an embodiment of the computing device of the present invention. Detailed Implementation

[0039] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0040] In the following description, the terms “first, second, third, etc.” or module A, module B, module C, etc. are used only to distinguish similar objects or different embodiments and do not represent a specific ordering of objects. It is understood that a specific order or sequence may be interchanged where permitted so that the embodiments of the invention described herein can be implemented in an order other than that illustrated or described herein.

[0041] In the following description, the labels of the steps, such as S110, S120, etc., do not necessarily mean that the steps will be executed in this way. The order of the steps can be interchanged or executed simultaneously if permitted.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing embodiments of the invention only and is not intended to limit the invention.

[0043] This invention provides a method, apparatus, operating system, device, and storage medium for interrupt virtualization. The method includes: when a hypervisor injects a virtual interrupt into a first virtual machine, selecting an idle virtual interrupt register in the physical CPU running the first virtual machine as the virtual interrupt register for the virtual interrupt, wherein the first virtual machine is any virtual machine running on the hypervisor; when storing virtual interrupt information in the selected virtual interrupt register, setting an indication message to prevent maintenance interruption, so that the first virtual machine does not generate a maintenance interrupt when processing the virtual interrupt; when the first virtual machine is trapped in the hypervisor and has completed processing the virtual interrupt, clearing the contents of the selected virtual interrupt register.

[0044] This invention is applied to interrupt virtualization scenarios in virtualized operating systems. By setting an indication in the selected virtual interrupt register to prevent maintenance interrupts, the virtual machine avoids generating maintenance interrupts when handling virtual interrupts. Compared to existing technologies where the virtual machine generates an additional maintenance interrupt when handling virtual interrupts, the technical solution of this invention does not generate a maintenance interrupt every time a virtual interrupt is responded to, thereby reducing the number of maintenance interrupts and improving interrupt virtualization efficiency.

[0045] The following is combined with Figures 1 to 3 The method embodiments of the present invention are described below.

[0046] Figure 1 The flowchart of a method for interrupting virtualization is shown in Embodiment 1, including steps S110 to S140.

[0047] For ease of explanation, let's take the example of the hypervisor injecting a virtual interrupt into the first virtual machine, where the first virtual machine is any virtual machine running on the hypervisor.

[0048] S110: When the hypervisor injects a virtual interrupt into the first virtual machine and the first virtual machine is running, select an idle virtual interrupt register in the physical CPU running the first virtual machine as the virtual interrupt register for that virtual interrupt.

[0049] The sources of virtual interrupts injected by the hypervisor into the first virtual machine include at least one of the following:

[0050] Physical interrupts that require processing by the first virtual machine will be processed by the hypervisor.

[0051] Virtual interrupts generated by the first virtual machine that need to be processed by itself, such as SGI interrupts of the first virtual machine, will set the GIC register and thus fall into hypervisor processing.

[0052] When other virtual machines generate inter-core interrupts that require the first virtual machine to process, the hypervisor of the physical CPU where the other virtual machine resides will send hypervisor inter-core communication to the hypervisor where the first virtual machine resides, thereby causing the first virtual machine to be trapped in the hypervisor.

[0053] The virtual interrupt register has three states: idle, active, and inactive. An idle virtual interrupt register contains no virtual interrupt information. An active virtual interrupt register contains virtual interrupt information but the interrupt has not yet been processed. An inactive virtual interrupt register contains virtual interrupt information but the interrupt has been processed. Once the contents of an inactive virtual interrupt register are cleared, it becomes an idle virtual interrupt register.

[0054] In some embodiments, when the first virtual machine is not running, the virtual interrupt register of the physical CPU running the first virtual machine is stored in the data structure of the first virtual machine's context. The physical CPU running the first virtual machine is the physical CPU that runs when the first virtual machine is invoked. When the first virtual machine is not running, the operations on the virtual interrupt register of the physical CPU running the first virtual machine in the embodiments of the present invention are operations on the data structure corresponding to the virtual interrupt register in the context of the first virtual machine.

[0055] In some embodiments, when there are no free registers, an inactive virtual interrupt register is selected. Before performing virtual interrupt injection, the contents of the inactive virtual interrupt register are cleared to make it an idle virtual interrupt register for selection in this step.

[0056] S120: When storing the information of the injected virtual interrupt in the selected virtual interrupt register, set an indication message to prevent maintenance interrupts from being generated, so that the first virtual machine does not generate maintenance interrupts when processing the virtual interrupt.

[0057] The virtual interrupt injected into the selected virtual interrupt register is the process of storing the injected virtual interrupt information in the selected virtual interrupt register, so that the first virtual machine can respond to the virtual interrupt according to the information in the selected virtual interrupt register.

[0058] In some embodiments, when the number of virtual interrupts written in the physical CPU running the first virtual machine is equal to the number of virtual interrupt registers of the physical CPU, an indication message for generating a maintenance interrupt is set in the selected virtual interrupt register, so that the first virtual machine generates a maintenance interrupt when processing the virtual interrupt, wherein the number of writes is the number of virtual interrupts that the first virtual machine has not completed processing and whose information has been written to the corresponding virtual interrupt register of the physical CPU.

[0059] In some embodiments, when the hypervisor runs on an ARM-based chip, the virtual interrupt register is the List register. Bits are set in the List register to indicate whether a maintenance interrupt has occurred. After the first virtual machine processes the virtual interrupt, it will set its corresponding List register to an inactive state via hardware.

[0060] S130: The first virtual machine responds to the virtual interrupt, and no maintenance interrupt is generated during the response process.

[0061] When the first virtual machine processes a virtual interrupt, it determines whether a maintenance interrupt should be generated based on the indication information in the virtual interrupt register corresponding to the virtual interrupt. The maintenance interrupt is used to clear the contents of the corresponding virtual interrupt register.

[0062] Figure 2A This diagram illustrates the process of virtual interrupt injection and processing when the virtual interrupt register includes an indication message for generating a maintenance interrupt. Specifically, the first virtual machine generates a maintenance interrupt in response to this virtual interrupt.

[0063] Figure 2B This diagram illustrates the process of virtual interrupt injection and handling when the virtual interrupt register includes an indication that no maintenance interrupt is generated. Specifically, the first virtual machine does not generate a maintenance interrupt when responding to this virtual interrupt. Figure 2B For the effect of this embodiment, the virtual machine does not generate a maintenance interrupt when responding to a virtual interrupt.

[0064] S140: When the first virtual machine enters the hypervisor and has finished processing the virtual interrupt, the hypervisor clears the contents of the selected virtual interrupt register.

[0065] In this case, since the inactive virtual interrupt register contains the contents of its last corresponding virtual interrupt, the contents are cleared to make it an idle virtual interrupt register so that it can be used by other virtual interrupts.

[0066] In some embodiments, when the first virtual machine enters the hypervisor (including for any reason), the status of the virtual interrupt register in the physical CPU is queried, and the contents of inactive virtual interrupt registers are cleared to make them idle virtual interrupt registers. The virtual interrupt corresponding to an inactive virtual interrupt register has already been processed. Therefore, when the first virtual machine enters the hypervisor after completing the processing of the virtual interrupt, the hypervisor detects that the first virtual machine has completed the virtual interrupt and clears the contents of the selected virtual interrupt register.

[0067] In some embodiments, when the first virtual machine falls into the hypervisor due to a new virtual interrupt injection, this step is executed first, and then the new virtual interrupt injection is executed starting from step S110.

[0068] In summary, one embodiment of an interrupt virtualization method sets an indication in the selected virtual interrupt register to prevent maintenance interrupts from being generated when the virtual machine processes virtual interrupts. Compared to the prior art where the virtual machine generates an additional maintenance interrupt when processing virtual interrupts, the technical solution of this embodiment does not generate a maintenance interrupt every time the virtual interrupt injected into the virtual machine is responded to, thereby reducing the number of maintenance interrupts and improving the efficiency of interrupt virtualization.

[0069] An embodiment of an interrupt virtualization method, second embodiment, inherits from an embodiment of an interrupt virtualization method, first embodiment, and has all the advantages of the first embodiment. Furthermore, when the number of virtual interrupts written in the physical CPU running the first virtual machine is equal to the number of virtual interrupt registers of the physical CPU, an indication message for the virtual machine to generate a maintenance interrupt is set in the selected virtual interrupt register, thereby allowing subsequent virtual interrupts to be injected as quickly as possible.

[0070] Figure 3 The flowchart of a second embodiment of a method for interrupting virtualization is shown, including steps S210 to S260.

[0071] For ease of explanation, let's continue with the example of the hypervisor injecting a virtual interrupt into the first virtual machine. The first virtual machine is any virtual machine running on the hypervisor, and when the hypervisor injects a virtual interrupt into the first virtual machine, the first virtual machine is in a running state.

[0072] When the hypervisor injects a virtual interrupt into the first virtual machine, the first virtual machine is in a non-running state. The steps and methods are the same as in this embodiment, except that the operations on the selected virtual interrupt register and the number of virtual interrupts written are all operations on the corresponding data structures in the context of the first virtual machine.

[0073] S210: When the hypervisor injects a virtual interrupt into the first virtual machine and the first virtual machine is running, select an idle virtual interrupt register in the physical CPU running the first virtual machine as the virtual interrupt register for that virtual interrupt.

[0074] The specific method and advantages of this step are described in step S110 of an embodiment of a method for interrupting virtualization.

[0075] S220: Determine whether the number of virtual interrupts written to the physical CPU running the first virtual machine is less than the number of virtual interrupt registers of that physical CPU.

[0076] The number of writes refers to the number of virtual interrupts that the first virtual machine has not yet processed and whose information has been written to the corresponding virtual interrupt register of the physical CPU.

[0077] Specifically, when the number of virtual interrupts written in the physical CPU running the first virtual machine is less than the number of virtual interrupt registers of the physical CPU, step S230 is executed; when the number of virtual interrupts written in the physical CPU running the first virtual machine is equal to the number of virtual interrupt registers of the physical CPU, step S240 is executed.

[0078] S230: When storing the information of the injected virtual interrupt in the selected virtual interrupt register, set an indication message to prevent maintenance interrupts from being generated, so that the first virtual machine does not generate maintenance interrupts when processing the virtual interrupt.

[0079] When the number of virtual interrupts written in the physical CPU running the first virtual machine is less than the number of virtual interrupt registers of the physical CPU, the physical CPU still has free virtual interrupt registers remaining after this virtual interrupt injection, which can be selected for the next virtual interrupt injection. When storing the information of the injected virtual interrupt in the selected interrupt register, the virtual machine is set to not generate maintenance interrupt indication information, which does not affect the speed of subsequent virtual interrupt injection.

[0080] S240: Set the indication information for generating a maintenance interrupt in the selected virtual interrupt register, so that the first virtual machine generates a maintenance interrupt when processing the virtual interrupt.

[0081] Specifically, when the number of virtual interrupts written to the physical CPU running the first virtual machine is equal to the number of virtual interrupt registers of that physical CPU, an indication message for the virtual machine to generate a maintenance interrupt is set in the selected virtual interrupt register. This allows the virtual interrupt register to be cleared and released when the corresponding virtual interrupt is responded to, so that subsequent virtual interrupts can be injected as soon as possible.

[0082] S250: The first virtual machine responds to the virtual interrupt, and during the response process, determines whether to generate a maintenance interrupt based on the maintenance interrupt indication information in the corresponding virtual interrupt register.

[0083] Specifically, if the virtual interrupt register corresponding to the virtual interrupt includes an indication to generate a maintenance interrupt, a maintenance interrupt will be generated during the response process; if the virtual interrupt register corresponding to the virtual interrupt includes an indication not to generate a maintenance interrupt, a maintenance interrupt will not be generated during the response process.

[0084] S260: When the first virtual machine gets stuck in the hypervisor, query the status of the virtual interrupt register in the physical CPU and clear the contents of the inactive virtual interrupt register.

[0085] In this case, since the inactive virtual interrupt register contains the contents of its last corresponding virtual interrupt, the contents are cleared to make it an idle virtual interrupt register so that it can be used by other virtual interrupts.

[0086] The first virtual machine gets trapped in the hypervisor for any reason. It queries the status of the virtual interrupt register in the physical CPU of the game, clears the contents of the inactive virtual interrupt register, and makes it an idle virtual interrupt register. The virtual interrupt corresponding to the inactive virtual interrupt register has been processed.

[0087] When the first virtual machine falls into the hypervisor due to a new virtual interrupt injection, this step is executed first, and then the new virtual interrupt injection is executed from step S210.

[0088] In summary, the second embodiment of the interrupt virtualization method adds a determination of whether the number of virtual interrupts written in the physical CPU running the first virtual machine is less than the number of virtual interrupt registers of the physical CPU. If it is less, an indication message indicating that the virtual machine will not generate maintenance interrupts is set in the selected virtual interrupt register; if it is equal, an indication message indicating that the virtual machine will generate maintenance interrupts is set in the selected virtual interrupt register. This reduces the number of maintenance interrupts generated when the virtual machine processes virtual interrupts, improves interrupt virtualization efficiency, and also ensures that virtual interrupts are injected as soon as possible after the number of virtual interrupts written in the physical CPU running the first virtual machine equals the number of virtual interrupt registers of the physical CPU.

[0089] The following is combined with Figure 4 and Figure 5 An embodiment of the apparatus of the present invention is described below.

[0090] An apparatus embodiment for interrupting virtualization executes the method of an embodiment for interrupting virtualization, and has all the advantages of an embodiment for interrupting virtualization.

[0091] Figure 4 The structure of an embodiment of an interrupt virtualization device is shown, including: a register selection module 410, a maintenance interrupt setting module 420, a virtual interrupt response module 430, and a register content clearing module 440.

[0092] For ease of explanation, we will continue with the example of the hypervisor injecting a virtual interrupt into the first virtual machine, which is any virtual machine running on the hypervisor. The register selection module 410, the interrupt maintenance setting module 420, and the register content clearing module 440 are located in the hypervisor, while the virtual interrupt response module 430 is located in the first virtual machine.

[0093] The register selection module 410 is used to select an idle virtual interrupt register in the physical CPU running the first virtual machine when the hypervisor injects a virtual interrupt into the first virtual machine and the first virtual machine is running. For its working principle and advantages, please refer to step S110 of Embodiment 1 of an interrupt virtualization method.

[0094] The maintenance interrupt setting module 420 is used to set an indication message to prevent maintenance interruption when storing information about the injected virtual interrupt in the selected virtual interrupt register, so that the first virtual machine does not generate a maintenance interrupt when processing the virtual interrupt. For its working principle and advantages, please refer to step S120 of an embodiment of an interrupt virtualization method.

[0095] The virtual interrupt response module 430 is used by the first virtual machine to respond to the virtual interrupt, and no maintenance interrupt is generated during the response process. For its working principle and advantages, please refer to step S130 of Embodiment 1 of an interrupt virtualization method.

[0096] The register content clearing module 440 is used when the first virtual machine is trapped in the hypervisor and has completed processing the virtual interrupt, to clear the contents of the selected virtual interrupt register. For its working principle and advantages, please refer to step S140 of Embodiment 1 of an interrupt virtualization method.

[0097] An embodiment of an interrupt virtualization apparatus performs the method of an interrupt virtualization method embodiment two, and has all the advantages of an interrupt virtualization method embodiment two.

[0098] Figure 5 The structure of a second embodiment of an interrupt virtualization device is shown, including: a register selection module 510, a write count determination module 520, a maintenance interrupt setting module 530, a virtual interrupt response module 540, and a register content clearing module 550.

[0099] For ease of explanation, we will continue with the example of the hypervisor injecting a virtual interrupt into the first virtual machine. The first virtual machine is any virtual machine running on the hypervisor, and when the hypervisor injects a virtual interrupt into the first virtual machine, the first virtual machine is in a running state. When the hypervisor injects a virtual interrupt into the first virtual machine, the first virtual machine is in a non-running state. The working principle of each module is the same as in this embodiment, except that the operations on the selected virtual interrupt register and the number of virtual interrupts written are all operations on the corresponding data structures in the context of the first virtual machine. Among them, the register selection module 510, the write count judgment module 520, the interrupt setting maintenance module 530, and the register content clearing module 550 are located in the hypervisor, and the virtual interrupt response module 540 is located in the first virtual machine.

[0100] The register selection module 510 is used to select an idle virtual interrupt register in the physical CPU running the first virtual machine when the hypervisor injects a virtual interrupt into the first virtual machine and the first virtual machine is running. For its working principle and advantages, please refer to step S210 of Embodiment 2 of an Interrupt Virtualization Method.

[0101] The write count determination module 520 is used to determine whether the write count of virtual interrupts in the physical CPU running the first virtual machine is less than the number of virtual interrupt registers of that physical CPU. For its working principle and advantages, please refer to step S220 of Embodiment 2 of an Interrupt Virtualization Method.

[0102] The maintenance interrupt setting module 530 is used to set an indication message not to generate a maintenance interrupt when storing virtual interrupt information in a selected virtual interrupt register, when the number of virtual interrupts written in the physical CPU running the first virtual machine is less than the number of virtual interrupt registers of the physical CPU, so that the first virtual machine does not generate a maintenance interrupt when processing the virtual interrupt. For its working principle and advantages, please refer to step S230 of Embodiment 2 of an interrupt virtualization method.

[0103] The maintenance interrupt setting module 530 is also used to set an indication information for generating a maintenance interrupt when storing virtual interrupt information in a selected virtual interrupt register, when the number of virtual interrupts written in the physical CPU running the first virtual machine is equal to the number of virtual interrupt registers of the physical CPU, so that the first virtual machine generates a maintenance interrupt when processing the virtual interrupt. For its working principle and advantages, please refer to step S240 of Embodiment 2 of an interrupt virtualization method.

[0104] The virtual interrupt response module 540 is used by the first virtual machine to respond to the virtual interrupt, and during the response process, it determines whether a maintenance interrupt should be generated based on the maintenance interrupt indication information in the corresponding virtual interrupt register. For its working principle and advantages, please refer to step S250 of Embodiment 2 of an interrupt virtualization method.

[0105] The register content clearing module 550 is used to query the status of the virtual interrupt register in the physical CPU and clear the contents of inactive virtual interrupt registers when the first virtual machine is trapped in the hypervisor. For its working principle and advantages, please refer to step S260 of Embodiment 2 of an Interrupt Virtualization Method.

[0106] This invention also provides an operating system in which the programs included, when executed by a computer, cause the computer to perform either the interrupt virtualization method embodiment one or the interrupt virtualization method embodiment two.

[0107] This invention also provides a computing device, which will be described below in conjunction with... Figure 6 Detailed introduction.

[0108] The computing device 600 includes a processor 610, a memory 620, a communication interface 630, and a bus 640.

[0109] It should be understood that the communication interface 630 in the computing device 600 shown in the figure can be used to communicate with other devices.

[0110] The processor 610 can be connected to the memory 620. The memory 620 can be used to store the program code and data. Therefore, the memory 620 can be a storage unit inside the processor 610, an external storage unit independent of the processor 610, or a component that includes both the storage unit inside the processor 610 and the external storage unit independent of the processor 610.

[0111] Optionally, the computing device 600 may also include a bus 640. The memory 620 and communication interface 630 can be connected to the processor 610 via the bus 640. The bus 640 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus 640 can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one line is used in this figure, but this does not mean that there is only one bus or one type of bus.

[0112] It should be understood that in this embodiment of the invention, the processor 610 may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor. Alternatively, the processor 610 may employ one or more integrated circuits to execute relevant programs to implement the technical solutions provided in this embodiment of the invention.

[0113] The memory 620 may include read-only memory and random access memory, and provides instructions and data to the processor 610. A portion of the processor 610 may also include non-volatile random access memory. For example, the processor 610 may also store device type information.

[0114] When the computing device 600 is running, the processor 610 executes computer execution instructions stored in the memory 620 to perform the operation steps of each method embodiment.

[0115] It should be understood that the computing device 600 according to the embodiments of the present invention can correspond to the corresponding subject in executing the methods according to the various embodiments of the present invention, and the above and other operations and / or functions of each module in the computing device 600 are respectively for implementing the corresponding processes of the methods in the embodiments of the present method. For the sake of brevity, they will not be described in detail here.

[0116] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0117] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0118] In the embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0119] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this method embodiment according to actual needs.

[0120] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0121] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the decoding method described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0122] This invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, is used to perform the operation steps of the various method embodiments.

[0123] The computer storage medium of this invention can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0124] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0125] The program code contained on a computer-readable medium may be transmitted using any suitable medium, including, but not limited to, wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0126] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0127] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, all of which fall within the scope of protection of the present invention.

Claims

1. A method for interrupting virtualization, characterized in that, include: When the hypervisor injects a virtual interrupt into the first virtual machine, it selects an idle virtual interrupt register in the physical CPU running the first virtual machine as the virtual interrupt register for that virtual interrupt. The first virtual machine is any virtual machine running on the hypervisor. When the number of virtual interrupts written to the physical CPU running the first virtual machine is less than the number of virtual interrupt registers of that physical CPU, when storing virtual interrupt information in the selected virtual interrupt register, an indication message is set not to generate a maintenance interrupt, so that the first virtual machine does not generate a maintenance interrupt when processing the virtual interrupt; wherein, the number of writes is the number of virtual interrupts that the first virtual machine has not completed processing and whose information has been written to the corresponding virtual interrupt register of the physical CPU; when the first virtual machine is trapped in the hypervisor and the first virtual machine has completed processing the virtual interrupt, the hypervisor clears the contents of the selected virtual interrupt register; When the number of virtual interrupts written to the physical CPU running the first virtual machine is equal to the number of virtual interrupt registers of the physical CPU, an indication message for generating a maintenance interrupt is set in the selected virtual interrupt register, so that the first virtual machine generates a maintenance interrupt when processing the virtual interrupt.

2. The method according to claim 1, characterized in that, When the first virtual machine enters the hypervisor and has completed processing the virtual interrupt, the hypervisor clears the contents of the selected virtual interrupt register, specifically including: When the first virtual machine enters the hypervisor, the hypervisor queries the status of the virtual interrupt registers in the physical CPU, clears the contents of the inactive virtual interrupt registers, and makes them idle virtual interrupt registers. The virtual interrupts corresponding to the inactive virtual interrupt registers have been processed.

3. The method according to claim 1, characterized in that, The sources of virtual interrupts injected by the hypervisor into the first virtual machine include at least one of the following: Physical interrupts that require handling by the first virtual machine; The first virtual interrupt generated by the virtual machine and requiring its own processing; Inter-core interrupts generated by other virtual machines that require processing by the first virtual machine.

4. The method according to claim 1, characterized in that, When the first virtual machine is not running, the contents of the virtual interrupt register of the physical CPU running the first virtual machine are stored in the data structure of the first virtual machine's context. When a virtual interrupt is injected, the operation on the virtual interrupt register of the physical CPU running the first virtual machine is an operation on the data structure corresponding to its context in the first virtual machine.

5. The method according to claim 1, characterized in that, When the hypervisor runs on an ARM architecture chip, the virtual interrupt register is the List register.

6. An apparatus for interrupting virtualization, characterized in that, include: The register selection module is used to select an idle virtual interrupt register in the physical CPU running the first virtual machine as the virtual interrupt register when the hypervisor injects a virtual interrupt into the first virtual machine. The first virtual machine is any virtual machine running on the hypervisor. The maintenance interrupt setting module is used to set an indication message to not generate a maintenance interrupt when storing virtual interrupt information in a selected virtual interrupt register, when the number of virtual interrupts written in the physical CPU running the first virtual machine is less than the number of virtual interrupt registers of the physical CPU, so that the first virtual machine does not generate a maintenance interrupt when processing the virtual interrupt; wherein, the number of writes is the number of virtual interrupts that the first virtual machine has not completed processing and whose information has been written to the corresponding virtual interrupt register of the physical CPU. The register content clearing module is used to clear the contents of the selected virtual interrupt register when the first virtual machine is trapped in the hypervisor and the first virtual machine has finished processing the virtual interrupt. The maintenance interrupt setting module is further configured to set an indication message for generating a maintenance interrupt in a selected virtual interrupt register when the number of virtual interrupts written in the physical CPU running the first virtual machine is equal to the number of virtual interrupt registers of the physical CPU, so that the first virtual machine generates a maintenance interrupt when processing the virtual interrupt.

7. An operating system, characterized in that, The procedure it includes performs the method described in any one of claims 1 to 5.

8. A computing device, characterized in that, include: bus; A communication interface, which is connected to the bus; At least one processor is connected to the bus; as well as At least one memory connected to the bus and storing program instructions that, when executed by the at least one processor, cause the at least one processor to perform the method of any one of claims 1 to 5.

9. A computer-readable storage medium, characterized in that, It stores program instructions that, when executed by a computer, cause the computer to perform the method of any one of claims 1 to 5.

Images