An error correction method, an error correction system and a storage medium

Abstract

The embodiments of the present specification provide an error correction method, an error correction system and a storage medium. In the first pass mode, the error correction method can meet the transmission requirements of different types of memories for operation instructions, and meets the requirement that a specific type of memory (for example, NOR FLASH) can only identify whether it is an operation instruction when receiving complete eight-bit data, so that the error correction method can meet the instruction transmission requirements of various types of memories such as SRAM, DRAM and NOR FLASH in the first pass mode, and the adaptability of the error correction method is improved.

Description

Technical Field

[0001] The embodiments described in this specification relate to the field of data storage technology, specifically to data error correction technology within the field of data storage technology, and more specifically, to an error correction method, an error correction system, and a storage medium. Background Technology

[0002] ECC (Error Checking and Correcting) codes are a technology used to detect and correct errors during data transmission and storage. In storage systems, data may be corrupted due to various reasons (such as transmission noise, electromagnetic interference, and storage media damage), which may lead to data loss or corruption. Therefore, to ensure data reliability and integrity, ECC technology is needed for error checking and correction.

[0003] However, the applicability of ECC codes needs to be improved at present. Summary of the Invention

[0004] This specification provides an error correction method, error correction system, and storage medium through various embodiments, in order to achieve the purpose of using ECC codes in memory to ensure data reliability and integrity, and to expand the applicability of ECC technology.

[0005] In one aspect, one embodiment of this specification provides an error correction method for transmitting error checking and correction ECC codes output by the processor's internal controller to a memory; the memory includes a first address interface, a first communication interface, and a second communication interface; the internal controller is used to access the memory, and the internal controller includes a second address interface, a third communication interface, and an ECC interface; the error correction method includes: In the first path mode, the operation instructions output by the internal controller are transmitted to the memory; the first path mode includes: the first address interface is connected to the second address interface; both the first communication interface and the second communication interface are connected to the third communication interface; the operation instructions are used to instruct the memory to perform read, write or erase operations; In the second path mode, the ECC code is transmitted to the memory; the second path mode includes: the first address interface is connected to the second address interface, and the ECC interface is connected to the second communication interface.

[0006] In the first-path mode, the transmission requirements of operation instructions for different types of memory can be met. It satisfies the requirement that a specific type of memory (such as NOR FLASH) can only identify whether it is an operation instruction when it receives complete eight bits of data. This allows the error correction method to meet the instruction transmission requirements of various types of memory such as SRAM, DRAM and NOR FLASH in the first-path mode, thus improving the adaptability of the error correction method.

[0007] In one feasible implementation, the memory is a single memory, and the first communication interface and the second communication interface are used to connect to the same data line; The operation instructions include a data write instruction, which carries the stored data, the ECC code, and the target storage address; In the first path mode, transmitting the operation instructions output by the internal controller to the memory includes: According to the data write instruction, a first write instruction and a second write instruction are obtained. The first write instruction carries the stored data and a first storage address; the second write instruction carries the ECC code and a second storage address; the first storage address is used to indicate the storage location of the stored data in the memory, and the second storage address is used to indicate the storage location of the ECC code in the memory; the first storage address and the second storage address are different. In the first path mode, the first write instruction and the second write instruction are transmitted to the memory; In the second path mode, transmitting the ECC code to the memory includes: In the second path mode, the ECC code is stored in the storage location indicated by the second storage address; The method further includes the following steps before transmitting the ECC code to the memory in the second path mode: In the first path mode, the stored data is stored in the storage location indicated by the first storage address.

[0008] To avoid storing ECC codes and stored data at the same address on the memory chip, in this embodiment, the path control module, upon receiving the data write instruction from the operation command, can obtain a first write instruction carrying the stored data and a first storage address, and a second write instruction carrying the ECC code and a second storage address, based on the data write instruction. In the first path mode, the first and second write instructions are transmitted to the memory to determine the storage addresses of the stored data and the ECC code respectively, avoiding the possibility of the stored data and ECC code overlapping. This satisfies the error correction requirements of a single memory chip, making the error correction method applicable to scenarios where the memory consists of a single memory chip, thus improving the applicability of the error correction method. Furthermore, the error correction method is applicable to storing both stored data and ECC codes on a single memory chip, reducing the hardware resource requirements of the error correction method and thereby lowering the overall cost.

[0009] In one feasible implementation, the memory includes a data storage area and an ECC code storage area; The first storage address is used to indicate the storage location of the stored data in the data storage area; The second storage address is used to indicate the storage location of the ECC code in the ECC code storage area.

[0010] In this embodiment, by dividing the memory into a data storage area and an ECC code storage area, the stored data and the corresponding ECC code can be stored in separate areas. This facilitates the management of the stored data and ECC code, and makes it easier to find the required data from different areas.

[0011] In one feasible implementation, the memory includes a first sub-memory and a second sub-memory that are independent of each other, and the number of the first address interfaces is two; The first sub-memory includes a first communication interface and a first address interface; The second sub-memory includes a second communication interface and another of the first address interfaces; The second path mode further includes: the first communication interface is connected to the third communication interface.

[0012] In one feasible implementation, the operation instruction includes a data write instruction, which carries stored data, the ECC code, and a target storage address; In the second path mode, transmitting the ECC code to the memory includes: In the second path mode, the ECC code is transmitted to the second sub-memory; The error correction method also includes: In the second path mode, the storage data is transmitted to the first sub-memory.

[0013] In this embodiment, since the ECC code and the stored data are stored in different memory chips, the single target memory address carried in the data write instruction can be used to indicate the storage addresses of the stored data and the ECC code in the first sub-memory and the second sub-memory, without having to consider the problem of the stored data and the ECC code overwriting each other if their storage addresses are the same.

[0014] Secondly, one embodiment of this specification provides an error correction system, including: an internal controller, a path control module, and a memory; The pathway control module is connected between the memory and the internal controller; The memory includes a first address interface, a first communication interface, and a second communication interface. The internal controller is used to access the memory, and the internal controller includes a second address interface, a third communication interface, and an ECC interface. The path control module is used to transmit operation instructions output by the internal controller to the memory in a first path mode; the first path mode includes: the first address interface is connected to the second address interface; both the first communication interface and the second communication interface are connected to the third communication interface; and is used to transmit the ECC code to the memory in a second path mode; the second path mode includes: the first address interface is connected to the second address interface, and the ECC interface is connected to the second communication interface; the operation instructions are used to instruct the memory to perform read, write, or erase operations.

[0015] In one feasible implementation, the internal controller is integrated within the processor; the pathway control module includes a programmable logic array independent of the processor.

[0016] In this embodiment, the path control module includes a programmable logic array independent of the processor, so that the switching operation between the first path mode and the second path mode does not need to be performed by the processor, which helps to reduce the processor's computational logic and reduce the processor's computational pressure.

[0017] In one feasible implementation, both the internal controller and the pathway control module are integrated within the processor.

[0018] In this embodiment, the path control module is integrated inside the processor, which helps to reduce the number of devices in the system and improve the system integration.

[0019] In one feasible implementation, the memory is a single memory, and the first communication interface and the second communication interface are used to connect to the same data line; The operation instructions include a data write instruction, which carries the stored data, the ECC code, and the target storage address; In the first path mode, the path control module transmits the operation instructions output by the internal controller to the memory specifically for: According to the data write instruction, a first write instruction and a second write instruction are obtained. The first write instruction carries the stored data and a first storage address; the second write instruction carries the ECC code and a second storage address; the first storage address is used to indicate the storage location of the stored data in the memory, and the second storage address is used to indicate the storage location of the ECC code in the memory; the first storage address and the second storage address are different. In the first path mode, the first write instruction and the second write instruction are transmitted to the memory; In the second path mode, the path control module transmits the ECC code to the memory specifically for the following purposes: In the second path mode, the ECC code is stored in the storage location indicated by the second storage address; The path control module is further configured to: in the second path mode, before transmitting the ECC code to the memory, store the stored data in the storage location indicated by the first storage address in the first path mode.

[0020] In one feasible implementation, the number of the first address interfaces is two, and the memory includes a first sub-memory and a second sub-memory that are independent of each other. The first sub-memory includes a first communication interface and a first address interface; The second sub-memory includes a second communication interface and another of the first address interfaces; The second path mode further includes: the first communication interface is connected to the third communication interface.

[0021] In one feasible implementation, the operation instruction includes a data write instruction, which carries stored data, the ECC code, and a target storage address; In the second path mode, the path control module transmits the ECC code to the memory specifically for the following purposes: In the second path mode, the ECC code is transmitted to the second sub-memory; The path control module is further configured to: transmit the storage data to the first sub-memory in the second path mode.

[0022] Thirdly, one embodiment of this specification provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the error correction method described above.

[0023] Fourthly, embodiments of this specification provide a computer program product or a computer program, the computer program product including a computer program stored in a computer-readable storage medium; the processor of the computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program to implement the steps of the above-described error correction method.

[0024] The various embodiments provided in this specification, by transmitting operation instructions and ECC codes in different path modes, achieve the goal of ensuring data reliability and integrity in memory while simultaneously meeting the specific operation instruction transmission requirements of the memory and the requirement for transmitting ECC codes output by the memory's internal controller to the memory. This expands the scope of ECC technology application. Specifically, in the error correction method provided in the embodiments of this specification, in the first path mode, the operation instructions output by the internal controller are transmitted to the memory. The first path mode includes: the first address interface is connected to the second address interface; both the first communication interface and the second communication interface are connected to the third communication interface. In this mode, the transmission requirements of operation instructions with specific instruction formats of the memory can be met. When transmitting ECC codes, the system can switch to the second path mode, and in the second path mode, the ECC codes are transmitted to the memory. The second path mode includes: the first address interface is connected to the second address interface, and the ECC interface is connected to the second communication interface. In this mode, the ECC interface of the internal controller is connected to the second communication interface, so that the ECC codes output through the ECC interface can be transmitted to the memory based on this connection path, realizing the writing of ECC codes. Attached Figure Description

[0025] Figure 1 This is a schematic diagram illustrating an application scenario for one embodiment of this specification.

[0026] Figure 2 This is a schematic diagram illustrating another application scenario provided for one embodiment of this specification.

[0027] Figure 3 This is a flowchart illustrating an error correction method provided for one embodiment of this specification.

[0028] Figure 4 This is a schematic diagram of the connection relationship of a first path mode provided for one embodiment of this specification.

[0029] Figure 5 This is a schematic diagram of the connection relationship of a second path mode provided for one embodiment of this specification.

[0030] Figure 6 This is a schematic diagram of the connection relationship of another first path mode provided for one embodiment of this specification.

[0031] Figure 7 This is a schematic diagram of the connection relationship for another second path mode provided in one embodiment of this specification.

[0032] Figure 8 This is a schematic diagram of the structure of an error correction system provided for one embodiment of this specification.

[0033] Figure 9 This is a schematic diagram of another error correction system provided as one embodiment of this specification.

[0034] Figure 10 This is a schematic diagram of an error correction device provided for one embodiment of this specification. Detailed Implementation

[0035] Unless otherwise defined, the technical or scientific terms used in the embodiments of this specification shall have the ordinary meaning understood by one of ordinary skill in the art to which this specification pertains. The terms "first," "second," and similar terms used in the embodiments of this specification do not indicate any order, quantity, or importance, but are merely used to avoid confusion of constituent elements.

[0036] Unless the context otherwise requires, throughout this specification, "a plurality of" means "at least two," and "including" is interpreted as open-ended or encompassing, that is, "including, but not limited to." In the description of this specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this specification. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example.

[0037] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0038] Overview In digital communication and storage processes, errors can occur during data transmission and storage due to noise, signal attenuation, interference, and other factors. These errors can lead to data loss or corruption, thus requiring a mechanism to detect and correct them. Therefore, ECC (Error Checking and Correcting) technology is commonly used to detect and correct errors in data transmission and storage. The primary goal of ECC is to improve the reliability of data transmission and storage. It detects errors by using redundant information and corrects the data, thereby ensuring the integrity and correctness of transmitted and stored data. For some critical application scenarios, such as computer memory systems, the importance of ECC is particularly prominent.

[0039] When performing ECC encoding on data bits, a corresponding baseline can be used for the encoding operation. For example, in one scenario, if 8 data bits require 5 ECC bits as a checksum, then when ECC encoding data in memory, the 8 data bits will be transmitted and stored along with the 5 ECC bits. If more data needs to be stored or transmitted, an additional 1 ECC bit is added for every additional 8 data bits to ensure data integrity, thus saving storage space and transmission bandwidth. The ECC code used can be Hamming code, BCH code (Bose-Chaudhuri-Hocquenghem code), or RS code (Reed-Solomon code), etc.

[0040] However, the instruction formats may differ between different types of memory and processors. For example, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and NOR FLASH (or non-flash memory) have different requirements for the data width of read and write operations. Taking the example above, when performing error correction on memory based on 8 data bits and 5-bit ECC code, the 5-bit ECC code cannot be used correctly because NOR FLASH and other types of memory require a complete 8-bit data width for erase and write operations (i.e., NOR FLASH needs to receive a complete 8-bit instruction to recognize it).

[0041] To address this issue, the inventors discovered that by transmitting operation instructions and ECC codes separately in different path modes, they can simultaneously meet the specific operation instruction transmission requirements of the memory and the requirement for transmitting ECC codes output by the memory's internal controller to the memory. This achieves the goal of using ECC codes in the memory to ensure data reliability and integrity, expanding the application scope of ECC technology. Specifically, in the first path mode, the operation instructions output by the internal controller are transmitted to the memory. This first path mode includes: the first address interface is connected to the second address interface; both the first and second communication interfaces are connected to the third communication interface. In this mode, the transmission requirements of operation instructions with specific memory instruction formats can be met. When transmitting ECC codes, the system can switch to a second path mode, and in this mode, the ECC codes are transmitted to the memory. The second path mode includes: the first address interface is connected to the second address interface; the ECC interface is connected to the second communication interface. In this mode, the internal controller's ECC interface is connected to the second communication interface, allowing the ECC codes output through the ECC interface to be transmitted to the memory via this connection path, thus enabling the writing of ECC codes.

[0042] Based on the above concept, the embodiments of this specification provide an error correction method, which will be described below with reference to the accompanying drawings.

[0043] Scenario Example The error correction method provided in this specification can be applied to data access scenarios of computing devices. In such scenarios, when the computing device 10 needs to store or read data in the memory 13, the error correction method can be executed through the path control module 12 to meet the format requirements of the processor 11 to transmit ECC codes, read / write instructions, and erase instructions to the memory 13.

[0044] In some implementations, reference Figure 1 The computing device 10 may include a processor 11, a path control module 12, and a memory 13. The path control module 12 establishes communication connections with both the processor 11 and the memory 13, and can control the data transmission path between the processor 11 and the memory 13. In one embodiment, for example in… Figure 1 In this embodiment, the path control module 12 can be a device independent of the processor 11. This device can be, for example, a programmable logic device (FPGA), which can possess the relevant computational resources and data transmission capabilities for instruction error correction methods. In another embodiment, the path control module 12 can be integrated within the processor 11.

[0045] Example method To be applied Figure 1 and Figure 2 Taking the path control module 12 shown in the figure as an example, this embodiment of the specification provides an error correction method for transmitting the error checking and correction ECC code output by the internal controller 111 of the processor 11 to the memory 13; the memory 13 includes a first address interface ADDR1, a first communication interface IO1, and a second communication interface IO2; the internal controller 111 is used to access the memory 13, and the internal controller 111 includes a second address interface ADDR2, a third communication interface IO3, and an ECC interface IOE, as shown in the figure. Figure 3 and Figure 4 As shown, the error correction method includes: S301: In the first path mode, the operation instructions output by the internal controller are transmitted to the memory; the first path mode includes: the first address interface is connected to the second address interface; both the first communication interface and the second communication interface are connected to the third communication interface; the operation instructions are used to instruct the memory to perform read, write or erase operations; S302: In the second path mode, the ECC code is transmitted to the memory; the second path mode includes: the first address interface is connected to the second address interface, and the ECC interface is connected to the second communication interface.

[0046] In this embodiment, the internal controller 111 provides the processor 11 with the ability to access the memory 13. In some embodiments, the internal controller 111 has the ability to access volatile memories such as SRAM and DRAM, and also has the ability to access non-volatile memories such as NOR FLASH. That is, the internal controller 111 can be used to access both volatile and non-volatile memories, supporting the ability to provide / transfer instructions and data to these types of memories. The processor 11 can support ECC error correction for volatile memories such as SRAM and DRAM, and can also support ECC error correction for non-volatile memories such as NOR FLASH. In some embodiments, the internal controller 111 can be a memory controller. This specification does not limit the specific type of the internal controller; it depends on the actual situation.

[0047] Figure 4 and Figure 5 The illustration shows a configuration where memory 13 comprises two memory chips 131. (Reference) Figure 4 , Figure 4 The connection relationship between memory 13 and internal controller 111 is shown in the first path mode. Figure 4 In this configuration, the first address interface ADDR1 and the second address interface ADDR2 are connected, so that the address information ADDR in the operation instruction can be transmitted through this connection path.

[0048] Both the first communication interface IO1 and the second communication interface IO2 are connected to the third communication interface IO3, so that other information DATA in the operation instructions can be transmitted through this connection path.

[0049] Thus, in the first path mode, the transmission requirements of operation instructions for different types of memory can be met. It satisfies the requirement that a specific type of memory 13 (e.g., NOR FLASH) can only identify whether it is an operation instruction when it receives complete eight bits of data. This allows the error correction method to meet the instruction transmission requirements of various types of memory such as SRAM, DRAM and NOR FLASH in the first path mode, thereby improving the adaptability of the error correction method.

[0050] refer to Figure 5 , Figure 5 The connection relationship between memory 13 and internal controller 111 is shown in the second path mode. Figure 5In this configuration, the first address interface IO1 and the second address interface IO2 are connected, allowing the storage address of the data to be stored to be transmitted via this connection path (ADDR). The ECC interface IOE is connected to the second communication interface IO2, allowing the ECC code corresponding to the data to be stored to be transmitted via this connection path. This satisfies the transmission requirements of ECC code and stored data between the internal controller 111 and the memory 13.

[0051] exist Figure 4 and Figure 5 The diagram illustrates a scenario where the memory 13 comprises two memory chips 131. To improve the applicability of the error correction method, in one embodiment of this specification, a scenario is provided where the memory 13 comprises a single memory chip 131. (Refer to...) Figure 6 and Figure 7 The memory is a single memory, and the first communication interface and the second communication interface are used to connect to the same data line; The operation instructions include a data write instruction, which carries the stored data, the ECC code, and the target storage address; In the first path mode, transmitting the operation instructions output by the internal controller to the memory includes: According to the data write instruction, a first write instruction and a second write instruction are obtained. The first write instruction carries the stored data and a first storage address; the second write instruction carries the ECC code and a second storage address; the first storage address is used to indicate the storage location of the stored data in the memory, and the second storage address is used to indicate the storage location of the ECC code in the memory; the first storage address and the second storage address are different. In the first path mode, the first write instruction and the second write instruction are transmitted to the memory; In the second path mode, transmitting the ECC code to the memory includes: In the second path mode, the ECC code is stored in the storage location indicated by the second storage address; The method further includes the following steps before transmitting the ECC code to the memory in the second path mode: In the first path mode, the stored data is stored in the storage location indicated by the first storage address.

[0052] In this embodiment, the memory 13 is a single memory, that is, the memory 13 includes a memory chip 131. The first communication interface IO1 and the second communication interface IO2 are used to connect to the same data line, which means that the first communication interface IO1 and the second communication interface IO2 can be the same interface. In the memory chip 131, it can be manifested as a physical interface to the outside world, and can be connected to the path control module 12 through a data line.

[0053] In this embodiment, a single memory chip 131 can be divided into different storage regions, which can be used to store data and ECC codes respectively. To avoid storing ECC codes and stored data in the same address of the memory chip 131, in this embodiment, after receiving the data write instruction of the operation instruction, the path control module 12 can obtain a first write instruction carrying the stored data and a first storage address and a second write instruction carrying the ECC code and a second storage address according to the data write instruction. In the first path mode, the first write instruction and the second write instruction are transmitted to the memory 13 to determine the storage addresses of the stored data and the ECC code respectively, avoiding the possibility of the stored data and ECC code overlapping, satisfying the error correction requirements of a single memory chip 131, and making the error correction method applicable to the case where the memory 13 includes a single memory chip 131, which is beneficial to improving the applicability of the error correction method. In addition, the error correction method can be applied to the storage of stored data and ECC codes in a single memory chip 131, which can reduce the hardware resource requirements of the error correction method, thereby reducing the overall cost.

[0054] For details, please refer to the following: Figure 6 and Figure 7 ,exist Figure 6 In the first path mode, the first address interface ADDR1 and the second address interface ADDR2 are connected, and the first data interface IO1 / second data interface IO2 are connected to the third data interface IO3 to meet the writing requirements of the first write instruction and the second write instruction. Furthermore, in this first path mode, since the third data interface IO3 establishes a communication connection with the first data interface IO1 / second data interface IO2, it can meet the requirement that stored data be output from the third data interface IO3 and transmitted to the memory 13 via the first data interface IO1 / second data interface IO2. The storage address of the stored data in the memory 13 is the first storage address.

[0055] exist Figure 7In the second path mode, the first data interface IO1 and the second data interface IO2 are connected to the ECC interface IOE, so that the ECC code output by the internal controller 111 from the ECC interface IOE can be transmitted to the memory 13 and stored through the first data interface IO1 and the second data interface IO2. The storage address of the ECC code in the memory 13 is the second storage address.

[0056] As described above, in one embodiment of this specification, the memory includes a data storage area and an ECC code storage area; The first storage address is used to indicate the storage location of the stored data in the data storage area; The second storage address is used to indicate the storage location of the ECC code in the ECC code storage area.

[0057] In this embodiment, by dividing the memory 13 into a data storage area and an ECC code storage area, the stored data and the corresponding ECC code can be stored in separate areas. This facilitates the management of the stored data and the ECC code, and makes it easier to find the required data from different areas.

[0058] In some embodiments, the memory 13 may contain two or more memory chips 131, for example, referring to FIG4 and Figure 5 In these embodiments, the memory includes a first sub-memory and a second sub-memory that are independent of each other, and the number of the first address interfaces ADDR1 is two; The first sub-memory includes a first communication interface IO1 and a first address interface ADDR; The second sub-memory includes a second communication interface IO2 and another of the first address interfaces ADDR; The second path mode also includes: the first communication interface IO1 is connected to the third communication interface IO3.

[0059] exist Figure 4 and Figure 5 In this memory, the two memory chips 131 in memory 13 can be independent first sub-memory and second sub-memory, respectively. These two memory chips 131 can be used to store ECC codes and store data, respectively. This makes the storage areas for ECC codes and stored data more distinct and simplifies the storage logic for ECC codes and stored data.

[0060] Specifically, in one embodiment of this specification, a feasible process is provided for storing the ECC code and storage data in two memory chips 131 respectively, still referring to Figure 4 and Figure 5The operation instructions include a data write instruction, which carries the stored data, the ECC code, and the target storage address; In the second path mode, transmitting the ECC code to the memory includes: In the second path mode, the ECC code is transmitted to the second sub-memory; The error correction method also includes: In the second path mode, the storage data is transmitted to the first sub-memory.

[0061] In this embodiment, since the ECC code and the stored data are stored in different memory chips 131, the single target storage address carried in the data write instruction can be used to indicate the storage addresses of the stored data and the ECC code in the first sub-memory and the second sub-memory, without having to consider the problem of the stored data and the ECC code overlapping each other if their storage addresses are the same.

[0062] In one specific embodiment of this specification, a feasible execution process for a specific error correction method is provided, the specific process of which can be referred to as follows: S1: The processor's internal controller is initialized normally; S2: The path control module (e.g., an FPGA) monitors the data lines connected to the processor; S3: The processor sends erase or write commands via the data lines connected to the FPGA. Taking the 8-bit full-chip erase command of NOR FLASH as an example, the format of the erase command can be found in Table 1: ① Taking an 8-bit full-chip erase as an example, the format of the erase instruction (Chip Erase) is shown in Table 1: Table 1 ② Taking 8-bit full-chip writing as an example, the format of the write command (Chip program) is shown in Table 2: Table 2 In Tables 1 and 2, `cycle i` represents the information sent in the i-th transmission, where i = 1 to 6. In each transmission, `addr` represents address information, and `data` represents other information in the instruction besides the address information. For example, `PA` represents the write address, and `PD` represents the write data. Similarly, "AAA", "AA", "555", "55", "80", "10", and "A0" in Tables 1 and 2 are examples of write addresses or write data. The bit width of both `addr` and `data` is 8 bits to meet the instruction transmission requirements of memories such as NOR FLASH.

[0063] S4: The FPGA detects an erase or write command issued by the processor's internal controller; S5: In the first path mode, the FPGA transmits the erase or write instruction to the memory; S6: After the FPGA detects that the erase or write command has been transmitted, it switches to the second path mode and transmits the ECC code and storage data to the memory in the second path mode.

[0064] Exemplary System Accordingly, the embodiments of this specification also provide an error correction system, referencing Figures 4-7 The error correction system includes: an internal controller 111, a path control module 12, and a memory 13; The path control module 12 is connected between the memory 13 and the internal controller 111; The memory 13 includes a first address interface ADDR1, a first communication interface IO1, and a second communication interface IO2. The internal controller 111 is used to access the memory 13. The internal controller 111 includes a second address interface ADDR2, a third communication interface IO3, and an ECC interface IOE. The path control module 12 is used to transmit operation instructions output by the internal controller 111 to the memory 13 in a first path mode; the first path mode includes: the first address interface ADDR1 is connected to the second address interface ADDR2; the first communication interface IO1 and the second communication interface IO2 are both connected to the third communication interface IO3; and is used to transmit the ECC code to the memory 13 in a second path mode; the second path mode includes: the first address interface ADDR1 is connected to the second address interface ADDR2, and the ECC interface IOE is connected to the second communication interface IO2; the operation instructions are used to instruct the memory 13 to perform read, write, or erase operations.

[0065] In one implementation, reference Figure 8 The internal controller 111 is integrated within the processor 11; the path control module 12 includes a programmable logic array independent of the processor 11, such as an FPGA 121. In this embodiment, the path control module includes a programmable logic array independent of the processor 11, so that the switching operation between the first path mode and the second path mode does not need to be performed by the processor 11, which helps to reduce the computational logic of the processor 11 and reduce the computational pressure on the processor 11.

[0066] In another implementation, refer to Figure 9The internal controller 111 and the path control module 12 are both integrated inside the processor 11. In this embodiment, the path control module 12 is integrated inside the processor 11, which helps to reduce the number of components in the system and improve the system integration.

[0067] In one feasible implementation, refer to Figure 6 and Figure 7 The memory is a single memory, and the first communication interface and the second communication interface are used to connect to the same data line; The operation instructions include a data write instruction, which carries the stored data, the ECC code, and the target storage address; In the first path mode, the path control module transmits the operation instructions output by the internal controller to the memory specifically for: According to the data write instruction, a first write instruction and a second write instruction are obtained. The first write instruction carries the stored data and a first storage address; the second write instruction carries the ECC code and a second storage address; the first storage address is used to indicate the storage location of the stored data in the memory, and the second storage address is used to indicate the storage location of the ECC code in the memory; the first storage address and the second storage address are different. In the first path mode, the first write instruction and the second write instruction are transmitted to the memory; In the second path mode, the path control module transmits the ECC code to the memory specifically for the following purposes: In the second path mode, the ECC code is stored in the storage location indicated by the second storage address; The path control module is further configured to: in the second path mode, before transmitting the ECC code to the memory, store the stored data in the storage location indicated by the first storage address in the first path mode.

[0068] In one feasible implementation, refer to Figure 4 and Figure 5 The number of the first address interfaces is two, and the memory includes a first sub-memory and a second sub-memory that are independent of each other; The first sub-memory includes a first communication interface and a first address interface; The second sub-memory includes a second communication interface and another of the first address interfaces; The second path mode further includes: the first communication interface is connected to the third communication interface.

[0069] In one feasible implementation, the operation instruction includes a data write instruction, which carries stored data, the ECC code, and a target storage address; In the second path mode, the path control module transmits the ECC code to the memory specifically for the following purposes: In the second path mode, the ECC code is transmitted to the second sub-memory; The path control module is further configured to: transmit the storage data to the first sub-memory in the second path mode.

[0070] For details regarding the functional limitations of each component in the error correction system, please refer to the description of the error correction method above. This manual will not elaborate further on these details.

[0071] Example devices, electronic devices, storage media, and software In one exemplary embodiment of this specification, an error correction device is also provided, such as Figure 10 As shown, an error checking and correction ECC code output by the processor's internal controller is transmitted to a memory. The memory includes a first address interface, a first communication interface, and a second communication interface. The internal controller accesses the memory and includes a second address interface, a third communication interface, and an ECC interface. The error correction method includes: The instruction transmission module 1001 is used to transmit operation instructions output by the internal controller to the memory in a first path mode; the first path mode includes: the first address interface is connected to the second address interface; the first communication interface and the second communication interface are both connected to the third communication interface; the operation instructions are used to instruct the memory to perform read, write or erase operations; The data transmission module 1002 transmits the ECC code to the memory in a second path mode; the second path mode includes: the first address interface is connected to the second address interface, and the ECC interface is connected to the second communication interface.

[0072] For specific limitations regarding the error correction device, please refer to the limitations regarding the error correction method above, which will not be repeated here. Each module in the aforementioned error correction device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the computer device in hardware form, or stored in the computer device in software form, so that the processor or controller can call and execute the corresponding operations of each module.

[0073] Exemplary computing device Another embodiment of this application also proposes a computing device, see [link to relevant documentation] Figure 1 or Figure 2An exemplary embodiment of this specification also provides a computing device 30, including: an internal controller 111, a access control module 12, and a memory 13; The pathway control module is connected between the memory and the internal controller; The memory includes a first address interface, a first communication interface, and a second communication interface. The internal controller is used to access the memory, and the internal controller includes a second address interface, a third communication interface, and an ECC interface. The path control module is used to transmit operation instructions output by the internal controller to the memory in a first path mode; the first path mode includes: the first address interface is connected to the second address interface; both the first communication interface and the second communication interface are connected to the third communication interface; and is used to transmit the ECC code to the memory in a second path mode; the second path mode includes: the first address interface is connected to the second address interface, and the ECC interface is connected to the second communication interface; the operation instructions are used to instruct the memory to perform read, write, or erase operations.

[0074] In some embodiments, the internal controller 111 and the access control module 12 may both be integrated within the processor. In other embodiments, the internal controller 111 is integrated within the processor, while the access control module 12 may be located independently of the processor; the access control module 12 may be, for example, an FPGA.

[0075] For details on the feasible execution process and beneficial effects of the memory self-correction performed by the computing device 30, please refer to the relevant description of the error correction method above. This manual will not repeat it here.

[0076] Those skilled in the art will understand that Figure 1 or Figure 2 The structures shown are merely block diagrams of some structures related to the solutions in this specification and do not constitute a limitation on the computing devices on which the solutions in this specification are applied. Specific computing devices may include more or fewer components than those shown in the figures, or combine certain components, or have different component arrangements.

[0077] Exemplary computer program products and storage media In addition to the methods and devices described above, the error correction methods provided in the embodiments of this specification can also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the error correction methods according to various embodiments of this specification as described in the "Exemplary Methods" section above.

[0078] The computer program product described herein can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments described herein. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0079] Furthermore, embodiments of this specification also provide a computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor of the steps in the error correction methods according to various embodiments of this specification as described in the "Exemplary Methods" section above.

[0080] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this specification can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0081] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The embodiments described above are merely illustrative of several implementation methods outlined in this specification. While the descriptions are specific and detailed, they should not be construed as limiting the scope of the solutions provided in this specification. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this specification, and these all fall within the scope of protection of this specification. Therefore, the scope of protection for this patent should be determined by the appended claims.

Claims

1. An error correction method, characterized in that, This method is used to transmit error checking and correction ECC codes output by the processor's internal controller to the memory; the memory includes a first address interface, a first communication interface, and a second communication interface; the internal controller is used to access the memory, and the internal controller includes a second address interface, a third communication interface, and an ECC interface; the error correction method includes: In the first path mode, the operation instructions output by the internal controller are transmitted to the memory; the first path mode includes: the first address interface is connected to the second address interface; both the first communication interface and the second communication interface are connected to the third communication interface; the operation instructions are used to instruct the memory to perform read, write or erase operations; In the second path mode, the ECC code is transmitted to the memory; the second path mode includes: the first address interface is connected to the second address interface, and the ECC interface is connected to the second communication interface.

2. The method according to claim 1, characterized in that, The memory is a single memory, and the first communication interface and the second communication interface are used to connect to the same data line; The operation instructions include a data write instruction, which carries the stored data, the ECC code, and the target storage address; In the first path mode, transmitting the operation instructions output by the internal controller to the memory includes: According to the data write instruction, a first write instruction and a second write instruction are obtained. The first write instruction carries the stored data and a first storage address; the second write instruction carries the ECC code and a second storage address; the first storage address is used to indicate the storage location of the stored data in the memory, and the second storage address is used to indicate the storage location of the ECC code in the memory; the first storage address and the second storage address are different. In the first path mode, the first write instruction and the second write instruction are transmitted to the memory; In the second path mode, transmitting the ECC code to the memory includes: In the second path mode, the ECC code is stored in the storage location indicated by the second storage address; The method further includes the following steps before transmitting the ECC code to the memory in the second path mode: In the first path mode, the stored data is stored in the storage location indicated by the first storage address.

3. The method according to claim 2, characterized in that, The memory includes a data storage area and an ECC code storage area; The first storage address is used to indicate the storage location of the stored data in the data storage area; The second storage address is used to indicate the storage location of the ECC code in the ECC code storage area.

4. The method according to claim 1, characterized in that, The memory includes a first sub-memory and a second sub-memory that are independent of each other, and the number of the first address interfaces is two; The first sub-memory includes a first communication interface and a first address interface; The second sub-memory includes a second communication interface and another of the first address interfaces; The second path mode further includes: the first communication interface is connected to the third communication interface.

5. The method according to claim 4, characterized in that, The operation instructions include a data write instruction, which carries the stored data, the ECC code, and the target storage address; In the second path mode, transmitting the ECC code to the memory includes: In the second path mode, the ECC code is transmitted to the second sub-memory; The error correction method also includes: In the second path mode, the storage data is transmitted to the first sub-memory.

6. An error correction system, characterized in that, The error correction system is used to transmit the error checking and correction ECC codes output by the processor's internal controller to the memory; the error correction system includes: an internal controller, a path control module, and a memory. The pathway control module is connected between the memory and the internal controller; The memory includes a first address interface, a first communication interface, and a second communication interface. The internal controller is used to access the memory, and the internal controller includes a second address interface, a third communication interface, and an ECC interface. The path control module is used to transmit operation instructions output by the internal controller to the memory in a first path mode; the first path mode includes: the first address interface is connected to the second address interface; both the first communication interface and the second communication interface are connected to the third communication interface; and is used to transmit the ECC code to the memory in a second path mode; the second path mode includes: the first address interface is connected to the second address interface, and the ECC interface is connected to the second communication interface; the operation instructions are used to instruct the memory to perform read, write, or erase operations.

7. The system according to claim 6, characterized in that, The internal controller is integrated inside the processor; the path control module includes a programmable logic array independent of the processor.

8. The system according to claim 6, characterized in that, Both the internal controller and the path control module are integrated inside the processor.

9. The system according to claim 6, characterized in that, The memory is a single memory, and the first communication interface and the second communication interface are used to connect to the same data line; The operation instructions include a data write instruction, which carries the stored data, the ECC code, and the target storage address; In the first path mode, the path control module transmits the operation instructions output by the internal controller to the memory specifically for: According to the data write instruction, a first write instruction and a second write instruction are obtained. The first write instruction carries the stored data and a first storage address; the second write instruction carries the ECC code and a second storage address; the first storage address is used to indicate the storage location of the stored data in the memory, and the second storage address is used to indicate the storage location of the ECC code in the memory; the first storage address and the second storage address are different. In the first path mode, the first write instruction and the second write instruction are transmitted to the memory; In the second path mode, the path control module transmits the ECC code to the memory specifically for the following purposes: In the second path mode, the ECC code is stored in the storage location indicated by the second storage address; The path control module is further configured to: in the second path mode, before transmitting the ECC code to the memory, store the stored data in the storage location indicated by the first storage address in the first path mode.

10. The system according to claim 6, characterized in that, The number of the first address interfaces is two, and the memory includes a first sub-memory and a second sub-memory that are independent of each other; The first sub-memory includes a first communication interface and a first address interface; The second sub-memory includes a second communication interface and another of the first address interfaces; The second path mode further includes: the first communication interface is connected to the third communication interface.

11. The system according to claim 10, characterized in that, The operation instructions include a data write instruction, which carries the stored data, the ECC code, and the target storage address; In the second path mode, the path control module transmits the ECC code to the memory specifically for the following purposes: In the second path mode, the ECC code is transmitted to the second sub-memory; The path control module is further configured to: transmit the storage data to the first sub-memory in the second path mode.

12. A storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the error correction method as described in any one of claims 1-5.

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