A matrix operation system, method, device and medium

Abstract

This application discloses a matrix operation system, method, device, and medium, relating to the field of artificial intelligence technology. The system includes an operation control unit for acquiring opcodes and address codes via an instruction opcode bus interface, determining whether the opcodes meet matrix validity conditions, and if so, generating a matrix validity signal and sending it to the central processing unit (CPU) via an operation interaction bus interface. A matrix input buffer is used to acquire and store opcodes and address codes, acquire matrix data to be operated on via a matrix data bus interface, and save the matrix data. A matrix operation unit is used to acquire matrix operation instructions, perform matrix operations on the matrix data to be operated on, and obtain the matrix operation result and matrix dimension. A matrix output buffer is used to acquire and store the matrix operation result and matrix dimension so that the CPU can read the matrix operation result. This application can improve matrix operation efficiency, reduce matrix operation time, and lower hardware costs.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence technology, and in particular to a matrix operation system, method, device and medium. Background Technology

[0002] With the development of artificial intelligence, people's demand for matrix operations is increasing. However, many processors based on the RISC-V (Reduced Instruction Set Computing) architecture do not support hardware-level matrix operations. This means that matrix operations can only be performed through software simulation, which reduces the efficiency of program execution.

[0003] As can be seen from the above, how to improve the efficiency of matrix operations, reduce the time required for matrix operations, and lower hardware costs are problems that need to be solved in this field. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a matrix operation system, method, device, and medium that can improve matrix operation efficiency, reduce matrix operation time, and lower hardware costs. The specific solution is as follows:

[0005] In a first aspect, this application discloses a matrix operation system, comprising:

[0006] The arithmetic control unit is used to obtain the opcode and address code sent by the central processing unit for implementing artificial intelligence operations through the instruction opcode bus interface, determine whether the opcode meets the preset matrix validity conditions, and if the opcode meets the preset matrix validity conditions, generate a matrix validity signal and send the matrix validity signal to the central processing unit through the arithmetic interaction bus interface.

[0007] A matrix input buffer is used to acquire and store the operation code and the address code in the operation control unit, acquire the matrix data to be operated sent by the central processing unit through the matrix data bus interface, and save the matrix data to be operated.

[0008] A matrix operation unit is used to acquire matrix operation instructions sent by the operation control unit, and perform matrix operations on the matrix data to be operated in the matrix input buffer based on the matrix operation instructions to obtain the matrix operation result and the matrix dimension;

[0009] A matrix output buffer is used to acquire and store the matrix operation result and the matrix dimension in the matrix operation unit, so that the central processing unit can read the matrix operation result through the matrix dimension.

[0010] Optionally, the arithmetic control unit includes:

[0011] The acquisition module is used to acquire the opcode and address code sent by the central processing unit for implementing artificial intelligence operations using the instruction opcode bus interface; the opcode includes matrix operation and input matrix dimension;

[0012] The judgment module is used to determine the matrix validity condition type corresponding to the dimension of the input matrix in the opcode, and to determine whether the dimension of the input matrix satisfies the matrix validity condition corresponding to the matrix validity condition type; the matrix validity condition type includes matrix addition, matrix scalar multiplication, matrix transpose, matrix multiplication and matrix inversion;

[0013] The valid signal sending module is used to generate a valid matrix signal if the dimension of the input matrix satisfies the valid matrix condition corresponding to the valid matrix condition type, and to send the valid matrix signal to the central processing unit using the computational interaction bus interface;

[0014] An invalid signal sending module is used to generate an invalid matrix signal if the dimension of the input matrix does not meet the matrix validity condition corresponding to the matrix validity condition type, and to send the invalid matrix signal to the central processing unit using the computational interaction bus interface.

[0015] Optionally, the arithmetic control unit further includes:

[0016] The signal receiving module is used to acquire, via the computational interaction bus interface, a data transmission signal sent by the central processing unit that indicates the completion of data transmission of the matrix to be computed;

[0017] The instruction generation and sending module is used to generate a matrix operation instruction when the signal receiving module detects that the data transmission signal has been acquired, and send the matrix operation instruction to the matrix operation component so that the matrix operation component can perform matrix operations based on the matrix operation instruction.

[0018] Optionally, the matrix operation system further includes:

[0019] The interface setting module is used to configure the local indicator bus interface used to display the matrix operation process; the matrix operation process includes matrix operation completed, matrix operation in progress, and matrix operation error.

[0020] Optionally, the interface setting module includes:

[0021] The monitoring module is used to monitor the matrix operation process in real time;

[0022] The first setting module is used to set the status indicator bus interface to matrix operation completion when it is detected that the matrix operation process has been completed.

[0023] The second setting module is used to set the status indicator bus interface to matrix operation error when an error is detected in the matrix operation process.

[0024] The third setting module is used to set the status of the status indicator bus interface to matrix operation in progress when the matrix operation process is detected to be in progress.

[0025] Optionally, the matrix operation system further includes:

[0026] The signal generation module is used to generate an interrupt signal when the status indicator bus interface is detected to be set to matrix operation completion or matrix operation error.

[0027] The signal sending module is used to send the interrupt signal to the central processing unit via the interrupt interface, so that the central processing unit can call the read instruction based on the interrupt signal and read the matrix operation result through the matrix dimension.

[0028] Optionally, the matrix operation system further includes:

[0029] The dimension sending module is used to send the matrix dimension in the matrix output buffer to the instruction opcode bus interface, so that the central processing unit can use the matrix data bus interface and read the matrix operation result through the matrix dimension of the instruction opcode bus interface.

[0030] Secondly, this application discloses a matrix operation method, including:

[0031] The opcode and address code sent by the central processing unit for implementing artificial intelligence operations are obtained using the instruction opcode bus interface. It is determined whether the opcode meets the preset matrix validity conditions. If the opcode meets the preset matrix validity conditions, a matrix validity signal is generated and sent to the central processing unit using the operation interaction bus interface.

[0032] The operation code and address code in the operation control unit are obtained and saved. The matrix data bus interface is used to obtain the matrix data to be operated sent by the central processing unit and the matrix data to be operated is saved.

[0033] The matrix operation instruction sent by the operation control unit is obtained, and matrix operation is performed on the matrix data to be operated in the matrix input buffer based on the matrix operation instruction to obtain the matrix operation result and matrix dimension;

[0034] The matrix operation result and the matrix dimension are acquired and saved in the matrix operation component so that the central processing unit can read the matrix operation result through the matrix dimension.

[0035] Thirdly, this application discloses an electronic device, including:

[0036] Memory, used to store computer programs;

[0037] A processor is used to execute the computer program to implement the aforementioned matrix operation method.

[0038] Fourthly, this application discloses a computer storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the steps of the aforementioned disclosed matrix operation method.

[0039] As can be seen, this application provides a matrix operation system, including an operation control unit, used to acquire the operation code and address code sent by the central processing unit (CPU) for implementing artificial intelligence operations via an instruction opcode bus interface, determine whether the operation code meets preset matrix validity conditions, and if the operation code meets the preset matrix validity conditions, generate a matrix validity signal and send the matrix validity signal to the CPU via an operation interaction bus interface; a matrix input buffer, used to acquire and store the operation code and address code in the operation control unit, acquire the matrix data to be operated sent by the CPU via a matrix data bus interface, and store the matrix data to be operated; a matrix operation unit, used to acquire the matrix operation instruction sent by the operation control unit, perform matrix operations on the matrix data to be operated in the matrix input buffer based on the matrix operation instruction, so as to obtain the matrix operation result and matrix dimension; and a matrix output buffer, used to acquire and store the matrix operation result and matrix dimension in the matrix operation unit, so that the CPU can read the matrix operation result through the matrix dimension. This application uses an arithmetic control unit to determine whether the input opcode meets the matrix validity conditions. If it does, it uses the interfaces between the local unit and the central processing unit to complete the transmission and storage of the matrix data to be operated, the matrix operation, and the storage of the matrix operation results. This allows the central processing unit to directly read the matrix operation results from the matrix operation system. During the matrix operation process, the central processing unit can execute other instructions, thereby improving the matrix operation efficiency, reducing the matrix operation time, and lowering the hardware cost. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of a matrix operation system structure disclosed in this application;

[0042] Figure 2 This is a diagram of a matrix operation instruction decoding structure disclosed in this application;

[0043] Figure 3 This is a specific structural diagram of a particular matrix operation disclosed in this application;

[0044] Figure 4 This is a flowchart illustrating a specific matrix operation disclosed in this application;

[0045] Figure 5 This application discloses a specific matrix operation system and interface structure diagram.

[0046] Figure 6 This is a flowchart of a matrix operation method disclosed in this application;

[0047] Figure 7 This is a schematic diagram of the structure of an electronic device provided in this application. Detailed Implementation

[0048] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] With the development of artificial intelligence, the demand for matrix operations is increasing. However, many RISC-V-based processors do not support hardware-level matrix operations, forcing them to rely on software simulation, which reduces program execution efficiency. Therefore, improving matrix operation efficiency, reducing computation time, and lowering hardware costs are pressing issues in this field.

[0050] See Figure 1 As shown in the figure, this application discloses a matrix operation system, including:

[0051] The arithmetic control unit 11 is used to obtain the opcode and address code sent by the central processing unit for implementing artificial intelligence operations through the instruction opcode bus interface, determine whether the opcode meets the preset matrix validity conditions, and if the opcode meets the preset matrix validity conditions, generate a matrix validity signal and send the matrix validity signal to the central processing unit through the arithmetic interaction bus interface.

[0052] In this embodiment, the computation control unit 11 includes: an acquisition module, configured to acquire, via the instruction opcode bus interface, the opcode and address code sent by the central processing unit for performing artificial intelligence computation; the opcode includes a matrix operation and an input matrix dimension; a judgment module, configured to determine the matrix validity condition type corresponding to the input matrix dimension in the opcode, and to determine whether the input matrix dimension satisfies the matrix validity condition corresponding to the matrix validity condition type; the matrix validity condition type includes matrix addition, matrix scalar multiplication, matrix transpose, matrix multiplication, and matrix inversion; a validity signal sending module, configured to generate a matrix validity signal if the input matrix dimension satisfies the matrix validity condition corresponding to the matrix validity condition type, and send the matrix validity signal to the central processing unit via the computation interaction bus interface; and an invalid signal sending module, configured to generate a matrix invalid signal if the input matrix dimension does not satisfy the matrix validity condition corresponding to the matrix validity condition type, and send the matrix invalid signal to the central processing unit via the computation interaction bus interface.

[0053] The matrix operation system of this application supports six matrix operations: matrix addition, matrix subtraction, matrix scalar multiplication, matrix transpose, matrix multiplication, and matrix inversion. Matrix subtraction can be represented by adding a negative value to matrix addition. The input, output, and corresponding valid matrix conditions for each operation are shown in Table 1.

[0054] Table 1

[0055]

[0056] In order to implement the above five commonly used matrix operations, the operation control unit 11 judges the matrix legality conditions according to the operation code and address code sent by the CPU (Central Processing Unit) for implementing artificial intelligence operations. It can also use the generated micro-operations to control the entire matrix operation system to complete the corresponding matrix operation operations.

[0057] The matrix input buffer 12 is used to acquire and store the operation code and the address code in the operation control unit, acquire the matrix data to be operated sent by the central processing unit through the matrix data bus interface, and save the matrix data to be operated.

[0058] In this embodiment, there can be multiple matrix input buffers 12, such as matrix input buffer 1 and matrix input buffer 2. Each matrix input buffer includes a corresponding input matrix dimension register. The matrix input buffer is responsible for storing the input matrix data to be operated on. The input matrix dimension register is used to indicate the dimension of the input matrix currently stored in the buffer. The opcode includes matrix operation operation and input matrix dimension.

[0059] The matrix operation unit 13 is used to acquire the matrix operation instructions sent by the operation control unit, and perform matrix operations on the matrix data to be operated in the matrix input buffer based on the matrix operation instructions to obtain the matrix operation result and the matrix dimension.

[0060] In this embodiment, the arithmetic control unit 11 further includes: a signal receiving module, used to acquire a data transmission signal sent by the central processing unit to characterize the completion of the data transmission of the matrix to be processed using the arithmetic interaction bus interface; and an instruction generation and sending module, used to generate a matrix operation instruction when the signal receiving module acquires the data transmission signal, and send the matrix operation instruction to the matrix operation unit so that the matrix operation unit can perform matrix operations based on the matrix operation instruction.

[0061] Matrix output buffer 14 is used to acquire and save the matrix operation result and the matrix dimension in the matrix operation unit, so that the central processing unit can read the matrix operation result through the matrix dimension.

[0062] In this embodiment, the matrix operation system further includes: an interface setting module, used to set the local indicator bus interface for displaying the matrix operation process; the matrix operation process includes matrix operation completed, matrix operation in progress, and matrix operation error. The interface setting module includes: a monitoring module, used to monitor the matrix operation process in real time; a first setting module, used to set the status indicator bus interface to matrix operation completed when the matrix operation process is detected to be completed; a second setting module, used to set the status indicator bus interface to matrix operation error when an error is detected in the matrix operation process; and a third setting module, used to set the status of the status indicator bus interface to matrix operation in progress when the matrix operation process is detected to be in progress.

[0063] In this embodiment, the matrix operation system further includes: a signal generation module, used to generate an interrupt signal when the status indicator bus interface is detected to be set to matrix operation completion or matrix operation error; and a signal sending module, used to send the interrupt signal to the central processing unit via the interrupt interface, so that the central processing unit can call a read instruction based on the interrupt signal and read the matrix operation result through the matrix dimension.

[0064] In this embodiment, the matrix operation system further includes a dimension sending module, used to send the matrix dimension in the matrix output buffer to the instruction opcode bus interface, so that the central processing unit can use the matrix data bus interface and read the matrix operation result through the matrix dimension of the instruction opcode bus interface.

[0065] To improve program execution efficiency, this application separates the instructions for executing matrix operations (let's call them MAT_OP) from the instructions for reading the results of matrix operations (let's call them RET_READ). This allows the MAT_OP instruction to run within the main program, while the RET_READ instruction runs in the interrupt service routine after a system interrupt in the matrix operation unit. Thus, while the matrix operation system is performing matrix operations, the CPU can execute other instructions. The instruction decoding structures for MAT_OP and RET_READ are as follows: Figure 2 As shown.

[0066] The specific structure of the matrix operation system in this application is as follows: Figure 3 As shown, the matrix operation system consists of an operation control unit, a matrix input buffer, a matrix operation unit, and a matrix output buffer. The specific process of implementing matrix operations using the matrix operation system is as follows: Figure 4As shown: (1) The CPU decodes the matrix operation instruction (assuming it is MAT_OP) into an opcode and an address code. The opcode includes the matrix operation to be performed and the dimension of the input matrix. The address code is the address of the input matrix. There can be one or two address codes. (2) The CPU sends the opcode and address code, which include the matrix operation and the dimension of the input matrix, to the operation control unit 11. (3) The operation control unit 11 determines whether the dimension of the input matrix meets the preset matrix legality condition based on the opcode. (If the type of matrix legality condition is inversion operation, this step only determines whether it is a square matrix. The determination of whether it is invertible is made after all the input matrix data has been transmitted into the matrix input buffer.) (4) If it is legal, the operation control unit 11 sends a legality signal to the CPU through the operation interaction bus interface and puts the opcode, which includes the dimension of the input matrix, into the input matrix dimension register in the corresponding matrix input buffer 12. After receiving a valid signal, the CPU transmits the matrix data to be processed into the corresponding matrix input buffer 12 through the matrix data bus interface. After the transmission is completed, it sends a data transmission signal to the operation control unit 11 through the operation interaction bus interface to indicate that the data transmission of the matrix data to be processed is complete. (5) After receiving the data transmission signal, the operation control unit 11 instructs the entire matrix operation system to perform the corresponding matrix operation and sets the status of the status indicator bus interface to matrix operation in progress. At the same time, the CPU can run other instructions. (6) If the matrix operation is successfully completed, the matrix operation result and the matrix dimension will be stored in the matrix output buffer and the corresponding matrix output dimension register, respectively. The status of the status indicator bus interface will be set to matrix operation completed, and the matrix dimension will be placed in the corresponding position of the instruction opcode bus interface. If the matrix operation fails, the status of the status indicator bus interface will be set to matrix operation error. In either case, the matrix operation system will send an interrupt signal to the CPU through the interrupt interface; (7) After receiving the interrupt signal, the CPU will call the RET_READ instruction (matrix operation result and memory address read instruction) in the interrupt service routine. This instruction is also divided into an opcode and an address code after decoding. The opcode is for reading the matrix operation result, and the address code indicates the memory address where the matrix operation result is stored. When executing this instruction, the CPU first determines whether the operation is successful based on the status set by the status indicator bus. If the operation is successful, the matrix operation result and memory address are read through the matrix data bus interface according to the matrix dimension indicated by the instruction opcode bus interface; if the operation fails, an exception is generated; (8) For cases where the matrix legality conditions are not met, the operation control unit 11 sends an invalid signal to the CPU through the operation interaction bus interface. After receiving the invalid signal, the CPU generates an exception.

[0067] The matrix operation system of this application includes multiple bus interfaces with the CPU, the specific structure of which is as follows: Figure 5 As shown, the specific interfaces and their functions are as follows: (1) Instruction opcode bus interface, used to send the opcode of matrix operation to the operation control unit 11, thereby generating a series of micro-operation control matrix operation processes. When the matrix operation operation instruction MAT_OP is executed, the input matrix dimension is indicated at the end of the opcode to prepare for judging the legality of the matrix and transmitting the input matrix. When the RET_READ instruction (matrix operation result and memory address read instruction) is executed, the matrix dimension is indicated at the corresponding position of the bus; (2) Operation interaction bus interface, used by the operation control unit 11 to indicate to the CPU whether the operation to be performed is legal, and by the CPU to send a data transmission signal to the matrix operation system indicating that the data transmission of the matrix to be operated has been completed; (3) Matrix data bus interface, used to send the matrix data to be operated to the matrix input buffer 12 or for the CPU to read the matrix operation result in the matrix output buffer 14; (4) Status indication bus interface, used by the matrix operation system to report the status of the current matrix operation process to the CPU, such as matrix operation completed, matrix operation error, matrix operation in progress, etc.; (5) Interrupt interface, which sends an interrupt signal to the CPU when the matrix operation is completed or the matrix operation error occurs.

[0068] In this embodiment, the arithmetic control unit is used to acquire the opcode and address code sent by the central processing unit (CPU) for implementing artificial intelligence operations via the instruction opcode bus interface, determine whether the opcode meets a preset matrix validity condition, and if the opcode meets the preset matrix validity condition, generate a matrix validity signal and send the matrix validity signal to the CPU via the arithmetic interaction bus interface; the matrix input buffer is used to acquire and store the opcode and address code in the arithmetic control unit, acquire the matrix data to be operated sent by the CPU via the matrix data bus interface, and store the matrix data to be operated; the matrix operation unit is used to acquire the matrix operation instruction sent by the arithmetic control unit, perform matrix operations on the matrix data to be operated in the matrix input buffer based on the matrix operation instruction, and obtain the matrix operation result and matrix dimension; the matrix output buffer is used to acquire and store the matrix operation result and matrix dimension in the matrix operation unit, so that the CPU can read the matrix operation result through the matrix dimension. This application uses an arithmetic control unit to determine whether the input opcode meets the matrix validity conditions. If it does, it uses the interfaces between the local unit and the central processing unit to complete the transmission and storage of the matrix data to be operated, the matrix operation, and the storage of the matrix operation results. This allows the central processing unit to directly read the matrix operation results from the matrix operation system. During the matrix operation process, the central processing unit can execute other instructions, thereby improving the matrix operation efficiency, reducing the matrix operation time, and lowering the hardware cost.

[0069] See Figure 6 As shown, an embodiment of the present invention discloses a matrix operation method, including:

[0070] Step S21: Obtain the opcode and address code sent by the central processing unit for implementing artificial intelligence operations using the instruction opcode bus interface, determine whether the opcode meets the preset matrix validity conditions, if the opcode meets the preset matrix validity conditions, generate a matrix validity signal, and send the matrix validity signal to the central processing unit using the operation interaction bus interface.

[0071] Step S22: Obtain and save the operation code and the address code in the operation control unit, obtain the matrix data to be operated sent by the central processing unit using the matrix data bus interface, and save the matrix data to be operated.

[0072] Step S23: Obtain the matrix operation instruction sent by the operation control unit, and perform matrix operation on the matrix data to be operated in the matrix input buffer based on the matrix operation instruction to obtain the matrix operation result and matrix dimension.

[0073] Step S24: Obtain and save the matrix operation result and the matrix dimension in the matrix operation component so that the central processing unit can read the matrix operation result through the matrix dimension.

[0074] In this embodiment, the arithmetic control unit is used to acquire the opcode and address code sent by the central processing unit (CPU) for implementing artificial intelligence operations via the instruction opcode bus interface, determine whether the opcode meets a preset matrix validity condition, and if the opcode meets the preset matrix validity condition, generate a matrix validity signal and send the matrix validity signal to the CPU via the arithmetic interaction bus interface; the matrix input buffer is used to acquire and store the opcode and address code in the arithmetic control unit, acquire the matrix data to be operated sent by the CPU via the matrix data bus interface, and store the matrix data to be operated; the matrix operation unit is used to acquire the matrix operation instruction sent by the arithmetic control unit, perform matrix operations on the matrix data to be operated in the matrix input buffer based on the matrix operation instruction, and obtain the matrix operation result and matrix dimension; the matrix output buffer is used to acquire and store the matrix operation result and matrix dimension in the matrix operation unit, so that the CPU can read the matrix operation result through the matrix dimension. This application uses an arithmetic control unit to determine whether the input opcode meets the matrix validity conditions. If it does, it uses the interfaces between the local unit and the central processing unit to complete the transmission and storage of the matrix data to be operated, the matrix operation, and the storage of the matrix operation results. This allows the central processing unit to directly read the matrix operation results from the matrix operation system. During the matrix operation process, the central processing unit can execute other instructions, thereby improving the matrix operation efficiency, reducing the matrix operation time, and lowering the hardware cost.

[0075] Figure 7 This is a schematic diagram of a matrix operation device provided in an embodiment of this application. The matrix operation device 20 specifically includes: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the matrix operation method performed by the electronic device disclosed in any of the foregoing embodiments.

[0076] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the matrix operation device 20; the communication interface 24 can create a data transmission channel between the matrix operation device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0077] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored on it include operating system 221, computer program 222 and data 223, etc., and the storage method can be temporary storage or permanent storage.

[0078] The operating system 221 manages and controls the various hardware devices and computer programs 222 on the matrix operation device 20 to enable the processor 21 to perform operations and processes on the data 223 in the memory 22. The operating system 221 can be Windows, Unix, Linux, etc. The computer program 222, in addition to including a computer program capable of performing the matrix operation methods executed by the matrix operation device 20 as disclosed in any of the foregoing embodiments, may further include computer programs capable of performing other specific tasks. The data 223 may include data received by the matrix operation device from external devices, as well as data collected by its own input / output interface 25.

[0079] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0080] Furthermore, embodiments of this application also disclose a computer-readable storage medium storing a computer program, which, when loaded and executed by a processor, implements the matrix operation method steps disclosed in any of the foregoing embodiments.

[0081] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0082] The matrix operation system, method, device, and storage medium provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A matrix operation system, characterized in that, include: The arithmetic control unit is used to obtain the opcode and address code sent by the central processing unit for implementing artificial intelligence operations through the instruction opcode bus interface, determine whether the opcode meets the preset matrix validity conditions, and if the opcode meets the preset matrix validity conditions, generate a matrix validity signal and send the matrix validity signal to the central processing unit through the arithmetic interaction bus interface. A matrix input buffer is used to acquire and store the operation code and the address code in the operation control unit, acquire the matrix data to be operated sent by the central processing unit through the matrix data bus interface, and save the matrix data to be operated. A matrix operation unit is used to acquire matrix operation instructions sent by the operation control unit, and perform matrix operations on the matrix data to be operated in the matrix input buffer based on the matrix operation instructions to obtain the matrix operation result and the matrix dimension; A matrix output buffer is used to acquire and store the matrix operation result and the matrix dimension in the matrix operation unit, so that the central processing unit can read the matrix operation result through the matrix dimension.

2. The matrix operation system according to claim 1, characterized in that, The arithmetic control unit includes: The acquisition module is used to acquire the opcode and address code sent by the central processing unit for implementing artificial intelligence operations using the instruction opcode bus interface; the opcode includes matrix operation and input matrix dimension; The judgment module is used to determine the matrix validity condition type corresponding to the dimension of the input matrix in the opcode, and to determine whether the dimension of the input matrix satisfies the matrix validity condition corresponding to the matrix validity condition type; the matrix validity condition type includes matrix addition, matrix scalar multiplication, matrix transpose, matrix multiplication and matrix inversion; The valid signal sending module is used to generate a valid matrix signal if the dimension of the input matrix satisfies the valid matrix condition corresponding to the valid matrix condition type, and to send the valid matrix signal to the central processing unit using the computational interaction bus interface; An invalid signal sending module is used to generate an invalid matrix signal if the dimension of the input matrix does not meet the matrix validity condition corresponding to the matrix validity condition type, and to send the invalid matrix signal to the central processing unit using the computational interaction bus interface.

3. The matrix operation system according to claim 1, characterized in that, The arithmetic control unit further includes: The signal receiving module is used to acquire, via the computational interaction bus interface, a data transmission signal sent by the central processing unit that indicates the completion of data transmission of the matrix to be computed; The instruction generation and sending module is used to generate a matrix operation instruction when the signal receiving module detects that the data transmission signal has been acquired, and send the matrix operation instruction to the matrix operation component so that the matrix operation component can perform matrix operations based on the matrix operation instruction.

4. The matrix operation system according to claim 1, characterized in that, The matrix operation system also includes: The interface setting module is used to configure the local status indicator bus interface used to display the matrix operation process; the matrix operation process includes matrix operation completed, matrix operation in progress, and matrix operation error.

5. The matrix operation system according to claim 4, characterized in that, The interface setting module includes: The monitoring module is used to monitor the matrix operation process in real time; The first setting module is used to set the status indicator bus interface to matrix operation completion when it is detected that the matrix operation process has been completed. The second setting module is used to set the status indicator bus interface to matrix operation error when an error is detected in the matrix operation process. The third setting module is used to set the status of the status indicator bus interface to matrix operation in progress when the matrix operation process is detected to be in progress.

6. The matrix operation system according to claim 4, characterized in that, The matrix operation system also includes: The signal generation module is used to generate an interrupt signal when the status indicator bus interface is detected to be set to matrix operation completion or matrix operation error. The signal sending module is used to send the interrupt signal to the central processing unit via the interrupt interface, so that the central processing unit can call the read instruction based on the interrupt signal and read the matrix operation result through the matrix dimension.

7. The matrix operation system according to any one of claims 1 to 6, characterized in that, The matrix operation system also includes: The dimension sending module is used to send the matrix dimension in the matrix output buffer to the instruction opcode bus interface, so that the central processing unit can use the matrix data bus interface and read the matrix operation result through the matrix dimension of the instruction opcode bus interface.

8. A matrix operation method, characterized in that, include: The arithmetic control unit uses the instruction opcode bus interface to obtain the opcode and address code sent by the central processing unit for implementing artificial intelligence operations, determines whether the opcode meets the preset matrix validity conditions, and if the opcode meets the preset matrix validity conditions, generates a matrix validity signal and sends the matrix validity signal to the central processing unit using the arithmetic interaction bus interface. The matrix input buffer acquires and saves the operation code and the address code in the operation control unit, acquires the matrix data to be operated sent by the central processing unit using the matrix data bus interface, and saves the matrix data to be operated. The matrix operation unit acquires the matrix operation instruction sent by the operation control unit, and performs matrix operation on the matrix data to be operated in the matrix input buffer based on the matrix operation instruction to obtain the matrix operation result and the matrix dimension; The matrix operation result and the matrix dimension are acquired and saved in the matrix operation component so that the central processing unit can read the matrix operation result through the matrix dimension.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the matrix operation method as described in claim 8.

10. A computer-readable storage medium, characterized in that, Used to store computer programs; wherein, when the computer program is executed by a processor, it implements the matrix operation method as described in claim 8.

Images