Impedance determination methods, systems, platforms, devices, and media

Abstract

The application provides an impedance determination method, system, platform, device and medium, the method comprises: the method comprises: obtaining the S parameters corresponding to each of a plurality of links in a memory bank; wherein a link is a link in which a data line of a byte in a memory particle of the memory bank is located; input the S parameters into a target model, the target model is obtained by training a preset neural network based on S parameter samples of a plurality of sample links as input, and the target position of each sample link corresponds to the optimal impedance of the node; obtaining the target impedance corresponding to each of the plurality of links output by the target model; wherein the target impedance is the impedance corresponding to the node located at the target position in the link; match the target impedance for the node at the target position, to improve the electrical performance of each link, the electrical performance at least includes the signal transmission quality of the link. To improve the efficiency and the degree of refinement of the ODT numerical setting of the memory bank.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to an impedance determination method, system, platform, device, and medium. Background Technology

[0002] ODT (on-die termination), as an on-chip termination, can reduce reflections, resulting in a significant improvement in signal quality. It can greatly enhance the SI performance of memory modules. Furthermore, memory chips can freely choose whether or not to configure ODT resistors. ODT resistors, also known as matching impedances, can be configured or not configured for any chip and its bytes, offering a high degree of freedom and resulting in numerous signal quality combinations. For multi-chip, multi-byte scenarios where each DQ data line within a byte has multiple corresponding ODT options, the selection and combination of ODT values ​​becomes extremely complex for signal integrity simulation and testing.

[0003] The current approach uses a specific byte of a particular chip as an example, selecting a standard ODT value. However, this approach doesn't guarantee optimal simulation and testing results for all chips and bytes using the same ODT value. Furthermore, it may overgeneralize and fail to fully utilize the potential performance of DDR5 SODIMM, leading to wasted memory resources. The second approach uses a specific byte of a particular chip as an example. The difference is that this approach uses a simulation loop to iterate through each byte, then selects a more optimal ODT value as the ODT value for all chips and bytes.

[0004] Both of the above solutions have the following three problems: First, they tend to overgeneralize and fail to fully utilize the ODT adjustment capabilities of each DQ data line of each byte in the SODIMM, leading to resource waste. Second, due to time and manpower limitations, the number of bytes traversed is limited, sometimes even only one byte. In such cases, the SODIMM cannot exhibit its optimal performance at the board level. Third, the routing of each byte in each chip is usually different at the board level, and even the routing of the eight DQ data lines of the same byte can vary. For example, during testing, a specific ODT value may cause one or more bytes to perform poorly, leading testers to repeatedly try different ODT values ​​to achieve the desired test results, which consumes a lot of time, effort, and manpower. Summary of the Invention

[0005] In view of this, the present invention provides a method, system, platform, device, and medium for determining impedance. The aim is to improve the efficiency and precision of setting the ODT value of memory modules.

[0006] In a first aspect of the present invention, an impedance determination method is provided, the method comprising:

[0007] Obtain the S-parameters corresponding to each of the multiple links in the memory module; wherein, one of the links is the link containing a data line of one byte in one memory chip of the memory module;

[0008] The S-parameters are input into the target model, which is obtained by training a preset neural network based on the S-parameter samples of multiple sample links as input and the optimal impedance corresponding to the node at the target position in each sample link as the label.

[0009] Obtain the target impedance corresponding to each of the multiple links output by the target model; wherein, the target impedance is the impedance corresponding to the node located at the target position in the link;

[0010] The target impedance is matched to the node at the target location to improve the electrical performance of each link, the electrical performance including at least the signal transmission quality of the link.

[0011] Optionally, the training of the target model includes:

[0012] Obtain the S-parameter samples corresponding to each of the sample links included in the sample memory module; wherein, a sample link is the link containing a data line of one byte in a memory chip of the sample memory module;

[0013] Obtain the optimal impedance corresponding to the node at the target location in each sample link, and use the optimal impedance as a label;

[0014] The S-parameter samples are input into a preset neural network to obtain the predicted impedance output by the preset neural network corresponding to the node at the target position in each sample link;

[0015] Based on the label and the predicted impedance, the preset neural network is updated multiple times to obtain the target model.

[0016] Optionally, obtaining the optimal impedance corresponding to the node at the target location in each sample link includes:

[0017] The working environment parameters of the sample memory module are set, wherein the working environment parameters include at least temperature parameters and humidity parameters;

[0018] Obtain the optimal impedance of the node at the target location in each sample link for different working environment parameters;

[0019] Inputting the S-parameters into the target model includes:

[0020] The S-parameters and the target operating environment parameters of the memory module are input into the target model to obtain the target impedance of each link of the memory module under the target operating environment parameters.

[0021] Optionally, obtaining the optimal impedance corresponding to the node at the target location in each sample link includes:

[0022] The electrical performance of the sample link under different impedances is tested to obtain the optimal impedance corresponding to the node at the target location of the sample link.

[0023] Alternatively, the optimal impedance can be obtained by following these steps:

[0024] Connect the sample memory module to the motherboard;

[0025] The electrical performance of the motherboard is tested under different impedance combinations to obtain the test results of the motherboard under each impedance combination; wherein, the impedance combination includes the impedance corresponding to the node at the target position in each sample link of the sample memory module;

[0026] Based on the test results, the optimal impedance combination corresponding to the memory module is selected from multiple impedance combinations.

[0027] Optionally, the node at the target location includes at least one of the following: an on-chip resistor terminated with the data line, an address line of the memory chip, and a control line of the memory chip.

[0028] Optionally, after matching the target impedance to the node at the target location, the method further includes:

[0029] The electrical performance of each link is tested based on the target impedance corresponding to each link.

[0030] When the test results do not meet the target conditions, obtain the optimal impedance of the link;

[0031] Based on the optimal impedance of the link and the target impedance, the parameters of the target model are corrected.

[0032] Optionally, obtaining the S-parameter samples corresponding to each of the sample links included in the sample memory bar includes:

[0033] Set the start frequency, cutoff frequency, and frequency interval of the sample link so that different sample links correspond to the same start frequency, cutoff frequency, and frequency interval;

[0034] Based on the start frequency, cutoff frequency, and frequency interval of each sample link, simulation software is used to simulate each sample link in the sample memory bar to obtain the normalized S-parameter samples corresponding to each of the sample links.

[0035] In a second aspect of the present invention, an impedance determination system is provided, the system comprising:

[0036] The S-parameter acquisition module is used to acquire the S-parameters corresponding to each of the multiple links in the memory module; wherein, one of the links is the link where a data line of one byte is located in one memory chip of the memory module;

[0037] The parameter input module is used to input the S-parameters into the target model. The target model is obtained by training a preset neural network based on the S-parameter samples of multiple sample links as input and the optimal impedance corresponding to the node at the target position in each sample link as the label.

[0038] The target impedance determination module is used to obtain the target impedances corresponding to each of the multiple links output by the target model; wherein, the target impedance is the impedance corresponding to the node located at the target position in the link;

[0039] A target impedance matching module is used to match the target impedance to a node at the target location in order to improve the electrical performance of each link, wherein the electrical performance includes at least the signal transmission quality of the link.

[0040] In a third aspect of the embodiments of the present invention, a training platform is also provided, such as Figure 4 As shown, it includes a simulation module 401 and a test module 402. The simulation module is used to determine the S-parameters of the link to provide sample link S-parameters and link S-parameters required for model training. The test module is used to test the signal quality of the link transmission to provide optimal impedance.

[0041] In a fourth aspect of the present invention, an electronic device is also provided, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus.

[0042] Memory, used to store computer programs;

[0043] When a processor executes a program stored in a memory, it implements the steps of the impedance determination method described in the first aspect of the present invention.

[0044] In a fifth aspect of the present invention, a computer-readable storage medium is also provided, having stored thereon a computer program that, when executed by a processor, implements an impedance determination method as described in the first aspect of the present invention.

[0045] Compared with prior art, the present invention has the following advantages:

[0046] This invention provides an impedance determination method that obtains the S-parameters corresponding to multiple links in a memory module. Each link is a data line of a single byte within a memory chip of the memory module. The S-parameters are input to a target model, which is trained on a preset neural network using S-parameter samples from multiple sample links as input and the optimal impedance corresponding to a node at a target position in each sample link as a label. The target impedance is then obtained from the output of the target model, corresponding to the target impedance of each of the multiple links. The target impedance is the impedance corresponding to a node at the target position in the link. The target impedance is matched to the node at the target position to improve the electrical performance of each link, including at least the signal transmission quality of the link. Thus, by determining the target impedance of a large number of links in the entire memory module through the target model, a better-performing impedance value can be set for each node at the target position in each link. When the node is an ODT (Optical Dependency Transmission Parameter), a better-performing ODT value can be set for the ODT, thereby improving the efficiency and precision of setting ODT values ​​in the memory module. At the same time, the impedance value for each node at the target location in each link is set to a value that provides better performance, enabling the memory module to exhibit optimal board-level performance.

[0047] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0049] Figure 1 A flowchart of an impedance determination method provided in an embodiment of the present invention;

[0050] Figure 2 This is a schematic diagram of the link structure in an impedance determination method provided by an embodiment of the present invention;

[0051] Figure 3A schematic diagram of an impedance determination system provided in an embodiment of the present invention;

[0052] Figure 4 This is a schematic diagram of a training platform in an impedance determination method provided in an embodiment of the present invention. Detailed Implementation

[0053] Exemplary embodiments of the present invention will now be described in more detail with reference to the accompanying drawings.

[0054] Figure 1 A flowchart of an impedance determination method provided in an embodiment of the present invention is shown below. Figure 1 As shown, the method includes:

[0055] Step S11: Obtain the S-parameters corresponding to each of the multiple links in the memory module; wherein, one of the links is the link containing a data line of one byte in one memory chip of the memory module;

[0056] Step S12: Input the S-parameters into the target model. The target model is obtained by training a preset neural network based on the S-parameter samples of multiple sample links as input and the optimal impedance corresponding to the node at the target position in each sample link as the label.

[0057] Step S13: Obtain the target impedance corresponding to each of the multiple links output by the target model; wherein, the target impedance is the impedance corresponding to the node located at the target position in the link;

[0058] Step S14: Match the target impedance to the node at the target location to improve the electrical performance of each link, the electrical performance including at least the signal transmission quality of the link.

[0059] In this embodiment, the core component of the memory module is the memory chip. Each memory chip includes multiple memory banks, also called banks. These banks are arranged in a matrix of numerous byte storage units. Each byte storage unit in the matrix corresponds to one byte, and one byte corresponds to 8 bits. Each byte storage unit is connected to the outside via 8 DQ data lines corresponding to the bits, forming 8 links to enable the transmission of the byte data stored in that byte storage unit. During the transmission of byte data through these links, the byte storage unit passes through multiple nodes, and the byte data can be transmitted to any node on the link. Each link in the memory module has S-parameters that characterize its data transmission properties. S-parameters, or scattering parameters, describe the frequency domain characteristics of the data transmission channel. Many characteristics of the data transmission channel can be determined through the S-parameters of the data transmission channel. Figure 2As shown, Figure 2 A schematic diagram of a link structure is shown. The diagram exemplifies a memory bank consisting of 20 bytes arranged in a matrix. Each byte is shown to consist of 8 bits, as illustrated by the dashed lines dividing a rectangle into 8 parts, each corresponding to one bit. Each bit is connected to the motherboard via a DQ data line for byte data transmission. Each DQ data line includes multiple nodes... Figure 2 The original circle is represented in the diagram.

[0060] In this embodiment, the S-parameters corresponding to each link in the memory module are first obtained, with each link having its own set of S-parameters. A single link is the data transmission link where a DQ data line connected to a bit in a byte storage unit within a memory chip of the memory module is located. Then, the obtained S-parameters of each link in the memory module are input into a target model for identification. This target model is obtained by training a preset neural network using a large number of sample links' S-parameter samples as labels, with the optimal impedance corresponding to the node at the target location in these sample links as the label. Finally, the target model processes the input S-parameters of each link in the memory module and outputs the target impedance corresponding to each link. Since the target model is trained based on S-parameter samples labeled with the optimal impedance corresponding to the node at the target location in the sample links, the target impedance determined by the target model based on the input S-parameters will also be the target impedance corresponding to the node at the target location in the link. Finally, the obtained target impedances corresponding to each link in the memory module are matched to the nodes at the target locations of the corresponding links to improve the electrical performance of the multiple links in the memory module when transmitting byte data to the nodes at the target locations. The electrical performance includes at least the signal transmission quality of the links. It should be understood that the multiple links in the memory module can be all the links included in the memory module, or it can be some of the links included in the memory module.

[0061] For example, a memory module contains multiple links, including links L1, L2, L3, ..., Ln. The S-parameters corresponding to each of these links are obtained and input into the target model for processing. The target model outputs the target impedances K1, K2, K3, ..., Kn corresponding to each of the links L1, L2, L3, ..., Ln. The target model is trained using S-parameter samples labeled with the optimal impedance corresponding to node a at the target location in the sample links. Based on the input S-parameters of the links, the target impedance determined by the target model will also be the target impedance corresponding to node a at the target location in the link. Therefore, the obtained target impedance K1 belongs to the target impedance at node a of link L1, the obtained target impedance K2 belongs to the target impedance at node a of link L2, the obtained target impedance K3 belongs to the target impedance at node a of link L3, ..., the obtained target impedance Kn belongs to the target impedance at node a of link Ln. When transmitting byte data to node a via link L1, the ODT value of link L1 is set to the target impedance K1 at node a, thereby improving the electrical performance of transmitting byte data to node a at the target location of link L1. Similarly, when transmitting byte data to node a via link L2, the target impedance K2 is set at node a, thereby improving the electrical performance of transmitting byte data to node a at the target location of link L2. Likewise, when transmitting byte data to node a via link L3, the target impedance K3 is set at node a, thereby improving the electrical performance of transmitting byte data to node a at the target location of link L3.

[0062] The nodes may include the ODTs connected to the DQ data lines in the link.

[0063] This invention provides an impedance determination method that obtains the S-parameters corresponding to multiple links in a memory module. Each link is a data line of a single byte within a memory chip of the memory module. The S-parameters are input into a target model, which is trained on a preset neural network using S-parameter samples from multiple sample links as input and the optimal impedance corresponding to a node at a target location in each sample link as a label. The target impedance is then obtained from the output of the target model, corresponding to the target impedance of each of the multiple links. The target impedance is the impedance corresponding to a node at the target location within the link. The target impedance is matched to the node at the target location to improve the electrical performance of each link, including at least the signal transmission quality of the link. Thus, the target impedance of a large number of links in the entire memory module is determined using the target model, and the ODT value of each link is set to the corresponding target impedance. This ensures that each link is set to an ODT value with better electrical performance, thereby improving the efficiency and precision of ODT value setting in the memory module. At the same time, setting the corresponding ODT value for each link to achieve better electrical performance enables the memory module to exhibit optimal board-level electrical performance.

[0064] In conjunction with the above embodiments, in one implementation, the present invention also provides an impedance determination method. In this impedance determination method, the training of the target model includes: Step S21: Obtaining S-parameter samples corresponding to all sample links included in the sample memory module; wherein, a sample link is the link containing a data line of one byte in a memory chip of the sample memory module; Step S22: Obtaining the optimal impedance corresponding to the node at the target position in each sample link, and using the optimal impedance as a label; Step S23: Inputting the S-parameter samples into a preset neural network, obtaining the predicted impedance output by the preset neural network corresponding to the node at the target position in each sample link; Step S24: Based on the label and the predicted impedance, updating the preset neural network multiple times to obtain the target model.

[0065] In this embodiment, one method for training the target model is as follows: Obtain the S-parameter samples corresponding to each of the sample links included in the sample memory strip used for training the preset neural network. A sample link is the data transmission link where a DQ data line connected to a bit in a byte storage unit within a memory chip of the sample memory strip is located. Then, obtain the optimal impedance of the node at the target location in each sample link of the sample memory strip, and use the obtained optimal impedance as the label of the corresponding S-parameter sample of the sample link. Input the S-parameter samples corresponding to each of the sample links included in the sample memory strip into the preset neural network to train the preset neural network, obtaining the predicted impedance value output by the preset neural network during training, corresponding to the node at the target location in each sample link. Then, compare the obtained predicted impedance value corresponding to the node at the target location in each sample link with the label of the corresponding S-parameter sample of the sample link, construct a loss function based on the predicted impedance value and the label, determine the loss value, and then adjust the various parameters of the preset neural network based on the loss value.

[0066] Then, using the S-parameter samples corresponding to each of the sample links included in the aforementioned sample memory bar, the pre-set neural network with adjusted parameters is trained and updated again. The predicted impedance value output during the current training process, corresponding to the node at the target position in each sample link, is compared with the label of the corresponding S-parameter sample of that sample link. Based on the comparison results, the parameters of the pre-set neural network with adjusted parameters are adjusted again. This process continues until the final comparison result meets the pre-set neural network training termination condition, at which point the target model is obtained.

[0067] The training termination condition can be: the difference between the predicted impedance value and the impedance value corresponding to the label is less than a preset difference, or the training has reached a preset number of times.

[0068] For example, all sample links in the sample memory bar include sample links XL1, XL2, XL3, ..., XLn. The S-parameter samples corresponding to each sample link in the sample memory bar are obtained, namely S-parameter samples C1, C2, C3, ..., Cn. At the same time, the optimal impedances Z1, Z2, Z3, ..., Zn corresponding to node b at the target position in each sample link are obtained. Z1 is used as the label of S-parameter sample C1, Z2 is used as the label of S-parameter sample C2, Z3 is used as the label of S-parameter sample C3, ..., Zn is used as the label of S-parameter sample Cn.

[0069] Then, the S-parameter samples C1, C2, C3, ..., Cn are input into a preset neural network for training, and the predicted impedance corresponding to node b at the target position in each sample link output by the preset neural network is obtained. These are the predicted impedance Y11 corresponding to node b at the target position in sample link XL1 predicted based on S-parameter sample C1, the predicted impedance Y21 corresponding to node b at the target position in sample link XL2 predicted based on S-parameter sample C2, the predicted impedance Y31 corresponding to node b at the target position in sample link XL3 predicted based on S-parameter sample C3, ..., the predicted impedance Yn1 corresponding to node b at the target position in sample link XLn predicted based on S-parameter sample Cn.

[0070] The predicted impedances are compared with the labels of the S-parameter samples of their respective sample links to obtain comparison results. Specifically, the predicted impedance Y11 corresponding to node b at the target position in sample link XL1 is compared with the label Z1 of the S-parameter sample of sample link XL1; the predicted impedance Y21 corresponding to node b at the target position in sample link XL2 is compared with the label Z2 of the S-parameter sample of sample link XL2; the predicted impedance Y31 corresponding to node b at the target position in sample link XL3 is compared with the label Z3 of the S-parameter sample of sample link XL3; and so on. The predicted impedance Yn1 corresponding to node b at the target position in sample link XLn is compared with the label Zn of the S-parameter sample of sample link XLn. This yields the comparison results for all sample links XL1, XL2, XL3, ... XLn. Based on these comparison results, the parameters of the preset neural network are adjusted.

[0071] Then, using all S-parameter samples C1, C2, C3, ..., Cn, the preset neural network with adjusted parameters is trained and updated to obtain the output results of a new round of training and updating. These results include the predicted impedance Y12 corresponding to node b at the target position in sample link XL1 predicted based on S-parameter sample C1, the predicted impedance Y22 corresponding to node b at the target position in sample link XL2 predicted based on S-parameter sample C2, the predicted impedance Y32 corresponding to node b at the target position in sample link XL3 predicted based on S-parameter sample C3, ..., the predicted impedance Yn2 corresponding to node b at the target position in sample link XLn predicted based on S-parameter sample Cn.

[0072] The predicted impedances are compared with the labels of the S-parameter samples of their respective sample links to obtain comparison results. Specifically, the predicted impedance Y12 at node b at the target position in sample link XL1 is compared with the label Z1 of the S-parameter sample of sample link XL1; the predicted impedance Y22 at node b at the target position in sample link XL2 is compared with the label Z2 of the S-parameter sample of sample link XL2; the predicted impedance Y32 at node b at the target position in sample link XL3 is compared with the label Z3 of the S-parameter sample of sample link XL3; and so on, until the predicted impedance Yn2 at node b at the target position in sample link XLn is compared with the label Zn of the S-parameter sample of sample link XLn. This yields the comparison results for all sample links XL1, XL2, XL3, ..., XLn. Based on these comparison results, the parameters of the preset neural network are adjusted again. Then, using all S-parameter samples C1, C2, C3, ..., Cn, the preset neural network with these adjusted parameters is trained and updated until the comparison results obtained after one round of training and updating meet the preset neural network training termination condition. At this point, the target model is obtained.

[0073] In this embodiment, the present application first prepares a large number of sample links' S-parameter samples and determines the optimal impedance corresponding to the node at its target position in each of the large number of sample links. Then, the S-parameter samples of each sample link are labeled with the determined optimal impedance. The labeled S-parameter samples of the large number of sample links are used as input to train a preset neural network to obtain the target model.

[0074] In conjunction with the above embodiments, in one implementation, the present invention also provides an impedance determination method. In this impedance determination method, step S22 specifically includes: step S221: setting the operating environment parameters of the sample memory module, wherein the operating environment parameters include at least temperature and humidity parameters; step S222: obtaining the optimal impedance of the node at the target location in each sample link corresponding to different operating environment parameters; inputting the S-parameters into the target model, including: inputting the S-parameters and the target operating environment parameters of the memory module into the target model to obtain the target impedance of each link of the memory module under the target operating environment parameters.

[0075] In this embodiment, this application discovers that the optimal impedance of a node at a target location in a sample link is related not only to the S-parameters characterizing the data transmission properties of the sample link itself, but also to the operating environment of the link during data transmission. Therefore, one implementation method for obtaining the optimal impedance corresponding to a node at a target location in each sample link is as follows: before obtaining the optimal impedance corresponding to a node at a target location in each sample link, the operating environment parameters of the sample memory module are set, and then the optimal impedance corresponding to a node at a target location in each sample link of the sample memory module under different operating environment parameters is obtained. The optimal impedance corresponding to a node at a target location in each sample link of the sample memory module under different operating environments is used as a label for the S-parameter sample of each sample link.

[0076] When the working environment parameters of the memory module are considered in the process of determining the label of the S-parameter sample, that is, when the working environment parameters of the memory module are considered in determining the optimal impedance of the node at the target position of the sample link corresponding to the S-parameter sample, one implementation of the above steps S23 and S24 is as follows: input the S-parameter samples corresponding to each of the sample links included in the sample memory module and the working environment parameters of the sample memory module into a preset neural network to train the preset neural network, and obtain the predicted impedance value corresponding to the node at the target position in each sample link output during the training process of the preset neural network.

[0077] Then, the predicted impedance value corresponding to the node at the target position in each sample link is compared with the label of the S-parameter sample of the corresponding sample link. The optimal impedance corresponding to the label in the comparison is determined considering the working environment parameters of the sample memory. For example, if the working environment parameter of the sample memory input to the prediction network is x1, then the label is also the optimal impedance determined when the memory is in working environment parameter x1. Based on the comparison results, the parameters of the preset neural network are adjusted. Then, the preset neural network is trained and updated again using the S-parameter samples corresponding to all sample links included in the sample memory and the working environment parameters of the sample memory. The predicted impedance value output during the current training process corresponding to the node at the target position in each sample link is again compared with the label of the S-parameter sample of the corresponding sample link, and the parameters of the preset neural network are adjusted based on the comparison results. Then, the preset neural network is trained and updated again using the S-parameter samples corresponding to each of the sample links included in the above sample memory and the working environment parameters of the above sample memory until the final comparison result meets the preset neural network training termination condition. At this point, the target model is obtained.

[0078] In this embodiment, when training a preset neural network based on any one of the sample links in the sample memory module, the S-parameters input to that sample link in the preset neural network can be different, and the operating environment parameters of the sample memory module corresponding to the S-parameters input to that sample link in the preset neural network can also be different. However, when the operating environment parameters of the sample memory module corresponding to that sample link in the preset neural network are determined, the label used when updating the parameters in the preset neural network is the optimal impedance of that sample link determined under the determined operating environment parameters of the memory module. For example, the S-parameter sample C1 of the sample link XL1 and the working environment parameter x1 of the sample memory module are input into a preset neural network for training. The preset neural network outputs the predicted impedance of the sample link XL1. This predicted impedance is compared with the corresponding label z1 to obtain the comparison result, where label z1 is the optimal impedance of the sample link XL1 when the working environment parameter of the sample memory module is x1. The S-parameter sample C1 of the sample link XL1 and the working environment parameter x2 of the sample memory module are input into the preset neural network for training. The preset neural network outputs the predicted impedance of the sample link XL1. This predicted impedance is compared with the corresponding label z2 to obtain the comparison result, where label z2 is the optimal impedance of the sample link XL1 when the working environment parameter of the sample memory module is x1.

[0079] In this embodiment, when the target model is trained based on the S-parameter samples corresponding to each of the sample links included in this memory module and the operating environment parameters of the sample memory module, step S12 includes step S121: inputting the S-parameters and the target operating environment parameters of the memory module into the target model to obtain the target impedance corresponding to each link of the memory module under the target operating environment parameters. In step S121, the parameters input into the target model include the obtained S-parameters corresponding to each of the multiple links in the memory module and the target operating environment parameters of the memory module. Therefore, the target model will predict and output the target impedance corresponding to each of the multiple links of the memory module under the target operating environment parameters. The operating environment parameters include at least temperature and humidity parameters.

[0080] In conjunction with the above embodiments, in one implementation, the present invention also provides an impedance determination method. In this implementation, the trained target model can be used to independently determine the target impedance of nodes at the target location of each link, thereby ensuring that each link operates in an optimal state. Of course, since there is some signal interference between links, in some examples, the optimal impedance corresponding to multiple links can also be determined as a whole. For example, the target impedance combination corresponding to multiple links of a memory module can be determined. This target impedance combination includes the target impedance of the nodes at the target location of each link. Specifically, under this target impedance combination, the motherboard where the memory module is located can exhibit optimal board-level performance.

[0081] Accordingly, step S22 may specifically include: testing the electrical performance of the sample link under different impedances to obtain the optimal impedance corresponding to the node at the target location of the sample link; or, obtaining the optimal impedance by following these steps: connecting the sample memory module to the motherboard; testing the electrical performance of the motherboard under different impedance combinations to obtain the test results of the motherboard under each impedance combination; wherein, the impedance combination includes the impedance corresponding to the node at the target location in each sample link of the sample memory module; and, based on the test results, selecting the optimal impedance combination corresponding to the memory module from multiple impedance combinations.

[0082] In this embodiment, one way to obtain the optimal impedance corresponding to the node at the target location in each sample link is as follows: Since the method of obtaining the optimal impedance corresponding to the node at the target location in all sample links is the same, the method of obtaining the optimal impedance corresponding to the node at the target location in one sample link is taken as an example. The electrical performance of the node at the target location in the sample link is tested under different impedances, so as to find the best electrical performance for transmitting byte data to the node at the target location in the sample link, and the optimal impedance corresponding to the best electrical performance is determined as the optimal impedance corresponding to the node at the target location in the sample link.

[0083] In this embodiment, due to the large number of sample links included in the sample memory module, to improve the determination of the optimal impedance corresponding to the node at the target location in each sample link of the sample memory module, for the step of obtaining the optimal impedance corresponding to the node at the target location in each sample link, the present invention proposes another implementation method: connect the sample memory module to the motherboard, and then test the electrical performance of the sample memory module for data transmission on the motherboard under multiple different impedance combinations, and obtain the data transmission test results for each impedance combination. Based on the obtained test results, the optimal impedance combination corresponding to the memory module is selected from the multiple different impedance combinations, and then each optimal impedance in the impedance combination is assigned to the optimal impedance corresponding to the node at the target location in its respective sample link. The impedance combination includes the impedance corresponding to the node at the target location in each sample link of the sample memory module. After determining the optimal impedance combination to the sample memory module, the optimal impedance combination includes the optimal impedance corresponding to the node at the target location in each sample link of the sample memory module. Based on this optimal impedance combination, the optimal impedance corresponding to the node at the target location in each sample link of the memory module can be determined.

[0084] In conjunction with the above embodiments, in one implementation, the present invention also provides an impedance determination method. In this impedance determination method, the node at the target location includes at least one of the following: an on-chip resistor terminated with the data line, an address line of the memory chip, and a control line of the memory chip.

[0085] In this embodiment, the target impedance of the node at the target location is the target impedance of a specified node in the byte data transmission link that the decision-maker wants to determine. The node at the target location can be the node corresponding to the on-chip resistor terminated by the DQ data line, the node corresponding to the address line of the memory chip, or the node corresponding to the control line of the memory chip.

[0086] In conjunction with the above embodiments, in one implementation, the present invention also provides an impedance determination method. In this impedance determination method, after step S14, the method may further include: testing the electrical performance of each link based on the target impedance corresponding to that link; when the test results do not meet the target conditions, obtaining the optimal impedance of the link; and correcting the parameters of the target model based on the optimal impedance of the link and the target impedance.

[0087] In this embodiment, to improve the prediction accuracy of the trained target model, after the target model predicts the target impedance of each link, the electrical performance of byte data transmission through each link is tested to obtain the test results for each link. If a test result does not meet the target condition, it is determined that although the target model has been trained to meet the preset neural network training termination condition, its prediction accuracy for the target impedance of the link corresponding to the link whose test result does not meet the target condition is insufficient. That is, after setting the ODT of that link as its target impedance, the electrical performance of byte data transmission through that link does not meet the target condition. In this case, the present invention will further modify and optimize the target model to enable it to make more accurate target impedance predictions for that link. Therefore, when it is determined that the test result does not meet the target condition, the optimal impedance of the link corresponding to that test result is obtained. Based on the optimal impedance of that link and the target impedance currently predicted by the target model, the parameters of the target model are modified.

[0088] Since the focus on signal transmission performance varies under different circumstances—for example, signal transmission quality in some cases and signal transmission speed in others—testing byte data transmission performance can be conducted by testing a specific electrical performance characteristic to determine the byte data transmission behavior under that characteristic, by testing eye diagram results to determine the byte data transmission behavior in the eye diagram, or by testing waveform effects to determine the byte data transmission behavior in the eye diagram. S-parameters are generally only used to characterize the performance of components in a link, such as how the input and output signals change with frequency, and are generally not used to evaluate the signal quality of a link. Signal quality is higher when all components are impedance matched. However, the signal quality of the link in this application is related to the impedance of the components. Therefore, a network structure simulating the components is constructed using S-parameters, and the target impedance refers to the value corresponding to the optimal signal quality under this network structure.

[0089] In conjunction with the above embodiments, in one implementation, the present invention also provides an impedance determination method. In this impedance determination method, step S21 specifically includes: setting the start frequency, cutoff frequency, and frequency interval of the sample links so that different sample links correspond to the same start frequency, cutoff frequency, and frequency interval; based on the start frequency, cutoff frequency, and frequency interval of each sample link, using simulation software to simulate each sample link in the sample memory module, obtaining the normalized S-parameter samples corresponding to each of the entire sample link.

[0090] In this embodiment, to ensure the normalization of the S-parameter samples used in training the preset neural network, when obtaining the S-parameter samples through simulation software, the start frequency, cutoff frequency, and frequency interval of the sample links are set by the simulation software so that different sample links have the same S-parameter sample acquisition start frequency, cutoff frequency, and frequency interval. Based on the start frequency, cutoff frequency, and frequency interval of each sample link, the simulation software is used to simulate each sample link in the sample memory to obtain the normalized S-parameter samples corresponding to each sample link.

[0091] In this embodiment, since electrical components may exhibit different electrical behaviors at different frequencies, and S-parameters describe the electrical behavior of electrical components at a certain frequency, serving as a tool to describe the electrical behavior of components under high-frequency signal excitation exhibiting radio frequency characteristics, this invention introduces S-parameters to determine the optimal impedance corresponding to each link in the memory module. Specifically, S-parameters describe the characteristics of the link, i.e., the characteristics of the link composed of multiple electrical components. Using S-parameters as input and the optimal impedance of the node at the target location in the link as a label, a CNN network is trained. The CNN network is used to predict the predicted impedance of the node at the target location based on the S-parameters. Then, the parameters of the CNN network are updated according to the predicted impedance and the optimal impedance corresponding to the label. After training the CNN network, a target model is obtained. Through the target model, the corresponding target impedance can be predicted for each link. By setting the corresponding target impedance for each link, the electrical performance of each link can be improved.

[0092] In this embodiment, firstly, the S-parameter samples corresponding to each of the sample links included in the sample memory bar required for training the preset neural network are obtained. Then, the optimal impedance of the node at the target position in each sample link of the sample memory bar is obtained, and the obtained optimal impedance is used as the label of the corresponding S-parameter sample of the sample link. The S-parameter samples corresponding to each of the sample links of the sample memory bar are input into the preset neural network to train the preset neural network, and the predicted impedance value corresponding to the node at the target position in each sample link is obtained as output during the training process. Then, the obtained predicted impedance value corresponding to the node at the target position in each sample link is compared with the label of the corresponding S-parameter sample of the sample link. For example, a loss function is constructed based on the predicted impedance value and the label to determine the loss value. Afterwards, the parameters of the preset neural network are adjusted according to the loss value.

[0093] Then, using the S-parameter samples corresponding to each of the sample links included in the aforementioned sample memory bar, the pre-set neural network with adjusted parameters is trained and updated again. The predicted impedance value output during the current training process, corresponding to the node at the target position in each sample link, is compared with the label of the corresponding S-parameter sample of that sample link. Based on the comparison results, the parameters of the pre-set neural network with adjusted parameters are adjusted again. This process continues until the final comparison result meets the pre-set neural network training termination condition, at which point the target model is obtained.

[0094] After obtaining the target model, the S-parameters corresponding to each link in the memory module whose impedance needs to be determined are acquired. All the acquired S-parameters corresponding to each link in the memory module are input into the target model for identification, and the target model outputs the target impedance corresponding to each link in the memory module. After the target model predicts the target impedance corresponding to each link, the electrical performance of byte data transmission through each link is tested, and the test results for each link are obtained. If the test results do not meet the target conditions, it is determined that although the target model has been trained to meet the preset neural network training termination conditions, the accuracy of the target impedance prediction for the link whose test results do not meet the target conditions is insufficient. That is, after setting the ODT of that link to the target impedance, the electrical performance of byte data transmission through that link does not meet the target conditions. In this case, the present invention will further modify and optimize the target model to enable the target model to make more accurate target impedance predictions for that link. Therefore, when a test result fails to meet the target conditions, the optimal impedance of the link corresponding to that test result is obtained. Based on this optimal impedance and the target impedance predicted by the target model, the parameters of the target model are corrected. Conversely, when all test results meet the target conditions, it is determined that board-level optimization exists for byte data transfer from the memory module, and the target model's identification accuracy is sufficiently high, eliminating the need for further correction or optimization.

[0095] In a second aspect of the present invention, an impedance determination system is provided, such as... Figure 3 As shown, the system 300 includes:

[0096] S-parameter acquisition module 301 is used to acquire the S-parameters corresponding to each of the multiple links in the memory module; wherein, one of the links is the link where a data line of one byte is located in one memory chip of the memory module;

[0097] The parameter input module 302 is used to input the S-parameters into the target model. The target model is obtained by training a preset neural network based on the S-parameter samples of multiple sample links as input and the optimal impedance corresponding to the node at the target position in each sample link as the label.

[0098] The target impedance determination module 303 is used to obtain the target impedances corresponding to each of the multiple links output by the target model; wherein, the target impedance is the impedance corresponding to the node located at the target position in the link;

[0099] The target impedance matching module 304 is used to match the target impedance to the node at the target location in order to improve the electrical performance of each link, the electrical performance including at least the signal transmission quality of the link.

[0100] Optionally, the system further includes a module for training to obtain the target model, comprising:

[0101] The S-parameter sample acquisition module is used to acquire the S-parameter samples corresponding to each of the sample links included in the sample memory module; wherein, a sample link is the link where a data line of one byte is located in a memory chip of the sample memory module;

[0102] The optimal impedance acquisition module is used to acquire the optimal impedance corresponding to the node at the target location in each sample link, and use the optimal impedance as a label;

[0103] The model training module is used to input the S-parameter samples into a preset neural network and obtain the predicted impedance output by the preset neural network corresponding to the node at the target position in each of the sample links.

[0104] The model parameter update module is used to update the preset neural network multiple times based on the label and the predicted impedance to obtain the target model.

[0105] Optionally, the optimal impedance acquisition module includes:

[0106] The working environment parameter setting module is used to set the working environment parameters of the sample memory stick, wherein the working environment parameters include at least temperature parameters and humidity parameters;

[0107] The first optimal impedance acquisition module is used to acquire the optimal impedance of the node at the target location in each sample link for different working environment parameters;

[0108] The parameter input module includes:

[0109] The parameter input submodule is used to input the S-parameters and the target operating environment parameters of the memory module into the target model to obtain the target impedance of each link of the memory module under the target operating environment parameters.

[0110] Optionally, the optimal impedance acquisition module includes:

[0111] The second optimal impedance acquisition module is used to test the electrical performance of the sample link under different impedances and obtain the optimal impedance corresponding to the node at the target location of the sample link.

[0112] A unit connection module is used to connect the sample memory module to the motherboard;

[0113] An electrical performance testing module is used to test the electrical performance of the motherboard under different impedance combinations, and obtain the test results of the motherboard under each impedance combination; wherein, the impedance combination includes the impedance corresponding to the node at the target position in each sample link of the sample memory module;

[0114] The third optimal impedance acquisition module is used to select the optimal impedance combination corresponding to the memory module from multiple impedance combinations based on the test results.

[0115] Optionally, the node at the target location in the target impedance matching module includes at least one of the following: an on-chip resistor terminated with the data line, an address line of the memory chip, and a control line of the memory chip.

[0116] Optionally, the system further includes:

[0117] The electrical performance testing submodule is used to test the electrical performance of each link based on the target impedance corresponding to each link.

[0118] The fourth optimal impedance acquisition module is used to acquire the optimal impedance of the link when the test results do not meet the target conditions.

[0119] The model parameter correction module is used to correct the parameters of the target model based on the optimal impedance of the link and the target impedance.

[0120] Optionally, the S-parameter sample acquisition module includes:

[0121] The parameter setting submodule is used to set the start frequency, cutoff frequency, and frequency interval of the sample link so that different sample links correspond to the same start frequency, cutoff frequency, and frequency interval.

[0122] The S-parameter sample acquisition submodule is used to simulate each sample link in the sample memory bar based on the start frequency, cutoff frequency and frequency interval of each sample link, and obtain the normalized S-parameter samples corresponding to each of the sample links.

[0123] In a third aspect of the present invention, a training platform is also provided, including a simulation module and a testing module. The simulation module is used to determine the S-parameters of the link to provide sample link S-parameters and link S-parameters required for model training. The testing module is used to test the signal quality of the link transmission to provide optimal impedance.

[0124] In a fourth aspect of the present invention, an electronic device is also provided, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus.

[0125] Memory, used to store computer programs;

[0126] When a processor executes a program stored in a memory, it implements the steps of the impedance determination method described in the first aspect of the present invention.

[0127] In a fifth aspect of the present invention, a computer-readable storage medium is also provided, having stored thereon a computer program that, when executed by a processor, implements an impedance determination method as described in the first aspect of the present invention.

[0128] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0129] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0130] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0131] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A method for determining impedance, characterized in that, The method includes: Obtain the S-parameters corresponding to each of the multiple links in the memory module; wherein, one of the links is the link containing a data line of one byte in one memory chip of the memory module; The S-parameters are input into the target model, which is obtained by training a preset neural network based on the S-parameter samples of multiple sample links as input and the optimal impedance corresponding to the node at the target position in each sample link as the label. Obtain the target impedance corresponding to each of the multiple links output by the target model; wherein, the target impedance is the impedance corresponding to the node located at the target position in the link; The target impedance is matched to the node at the target location to improve the electrical performance of each link, the electrical performance including at least the signal transmission quality of the link.

2. The method according to claim 1, characterized in that, The training of the target model includes: Obtain the S-parameter samples corresponding to each of the sample links included in the sample memory module; wherein, a sample link is the link containing a data line of one byte in a memory chip of the sample memory module; Obtain the optimal impedance corresponding to the node at the target location in each sample link, and use the optimal impedance as a label; The S-parameter samples are input into a preset neural network to obtain the predicted impedance output by the preset neural network corresponding to the node at the target position in each sample link; Based on the label and the predicted impedance, the preset neural network is updated multiple times to obtain the target model.

3. The method according to claim 2, characterized in that, Obtain the optimal impedance corresponding to the node at the target location in each sample link, including: The working environment parameters of the sample memory module are set, wherein the working environment parameters include at least temperature parameters and humidity parameters; Obtain the optimal impedance of the node at the target location in each sample link for different working environment parameters; Inputting the S-parameters into the target model includes: The S-parameters and the target operating environment parameters of the memory module are input into the target model to obtain the target impedance of each link of the memory module under the target operating environment parameters.

4. The method according to claim 2 or 3, characterized in that, The step of obtaining the optimal impedance corresponding to the node at the target location in each sample link includes: The electrical performance of the sample link under different impedances is tested to obtain the optimal impedance corresponding to the node at the target location of the sample link. Alternatively, the optimal impedance can be obtained by following these steps: Connect the sample memory module to the motherboard; The electrical performance of the motherboard is tested under different impedance combinations to obtain the test results of the motherboard under each impedance combination; wherein, the impedance combination includes the impedance corresponding to the node at the target position in each sample link of the sample memory module; Based on the test results, the optimal impedance combination corresponding to the memory module is selected from multiple impedance combinations.

5. The method according to claim 1, characterized in that, The node at the target location includes at least one of the following: an on-chip resistor terminated with the data line, an address line of the memory chip, or a control line of the memory chip.

6. The method according to claim 1, characterized in that, After matching the target impedance to the node at the target location, the method further includes: The electrical performance of each link is tested based on the target impedance corresponding to each link. When the test results do not meet the target conditions, obtain the optimal impedance of the link; Based on the optimal impedance of the link and the target impedance, the parameters of the target model are corrected.

7. The method according to claim 2, characterized in that, The acquisition of the S-parameter samples corresponding to each of the sample links included in the sample memory bar includes: Set the start frequency, cutoff frequency, and frequency interval of the sample link so that different sample links correspond to the same start frequency, cutoff frequency, and frequency interval; Based on the start frequency, cutoff frequency, and frequency interval of each sample link, simulation software is used to simulate each sample link in the sample memory bar to obtain the normalized S-parameter samples corresponding to each of the sample links.

8. An impedance determination system, characterized in that, The system includes: The S-parameter acquisition module is used to acquire the S-parameters corresponding to each of the multiple links in the memory module; wherein, one of the links is the link where a data line of one byte is located in one memory chip of the memory module; The parameter input module is used to input the S-parameters into the target model. The target model is obtained by training a preset neural network based on the S-parameter samples of multiple sample links as input and the optimal impedance corresponding to the node at the target position in each sample link as the label. The target impedance determination module is used to obtain the target impedances corresponding to each of the multiple links output by the target model; wherein, the target impedance is the impedance corresponding to the node located at the target position in the link; A target impedance matching module is used to match the target impedance to a node at the target location in order to improve the electrical performance of each link, wherein the electrical performance includes at least the signal transmission quality of the link.

9. A training platform, characterized in that, It includes a simulation module and a testing module. The simulation module is used to determine the S-parameters of the link to provide sample S-parameters of the link and the S-parameters of the link required for the model training step in the impedance determination method according to any one of claims 1-7. The testing module is used to test the signal quality of the link transmission to provide the optimal impedance required for the model training step in the impedance determination method according to any one of claims 1-7.

10. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; When a processor executes a program stored in memory, it implements the steps of an impedance determination method according to any one of claims 1-7.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements an impedance determination method as described in any one of claims 1 to 7.

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