A method for improving the efficiency of power network PDN impedance simulation

Abstract

The application relates to a method for improving power network PDN impedance simulation efficiency, all capacitor ports are proposed, a multi-port s parameter file containing the capacitor ports is generated, a multi-port cascade model is formed by combining the s parameters of the load chip ports, and the power network is equivalently formed; and the capacitor ports are replaced to optimize the PDN impedance. In the application, all capacitor models integrated in the load chip are extracted to the outside of the load port, in the PDN curve optimization process, the s parameters of each capacitor port are directly replaced, the capacitor model library does not need to be called again, the capacitor package name does not need to be modified, and a new capacitor model does not need to be given to the load chip; in the application, the s parameter position of the reserved capacitor port is directly adjusted, the simulation speed is very fast in each iteration, and the simulation can be completed in less than one minute, so that the power network PDN impedance simulation efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of circuit design, and more specifically, to a method for improving the impedance simulation efficiency of power supply network (PDN). Background Technology

[0002] Power delivery can be understood as a power distribution network (PDN), from the source-side voltage regulator module (VRM) to the load chip. The power distribution network provides the required power to the load chip and needs to be managed. PCB-level PDN design focuses on the target impedance of the power distribution network, i.e., the power network PDN impedance.

[0003] Power supply PDN simulation can obtain PDN curves. By comparing the PDN curves with the target impedance curves, it can be determined whether the PCB power network design meets the performance requirements. Initial results are usually difficult to meet the requirements, requiring multiple iterations and modifications to the capacitance of the simulation network until the PDN curve meets the target impedance within the target frequency range.

[0004] Traditional PDN simulation methods treat the load chip as a single port for simulation, assuming the chip integrates multiple capacitors. This approach involves retrieving capacitor model files from a library within the simulation software, assigning a corresponding package model to each capacitor, and creating a model. The observable port is only the chip side, meaning the simulation only yields a single-port S-parameter file. If the simulated PDN curves do not meet requirements and capacitor values ​​need to be changed, the capacitor model library must be retrieved again, the capacitor package name modified, and a new capacitor model assigned to the chip. This process is extremely time-consuming, especially with a large number of capacitors.

[0005] The above problems are worth solving. Summary of the Invention

[0006] To overcome the shortcomings of existing technologies, this invention provides a method for improving the impedance simulation efficiency of power supply network (PDN).

[0007] The technical solution of this invention is as follows:

[0008] A method for improving the simulation efficiency of power supply network (PDN) impedance is characterized by proposing each capacitor port, generating a multi-port S-parameter file containing multiple capacitor ports, and forming a multi-port cascade model with the S-parameters of the load chip ports to form an equivalent power supply network; and iteratively replacing the capacitor ports to optimize the PDN impedance.

[0009] According to the above-described scheme, the present invention is characterized by comprising the following steps:

[0010] Step 1: Remove all capacitor ports, making them independent of the load chip.

[0011] Step 2: Extract the S-parameters of the load chip port;

[0012] Step 3: Generate a multi-port S-parameter file containing multiple capacitor ports;

[0013] Step 4: Use the multi-port S-parameter file to establish a multi-port cascade model, equivalent power network;

[0014] Step 5: Simulate PDN impedance;

[0015] Step 6: Compare the PDN curve with the target impedance curve within the observation frequency band. If the comparison result does not meet the impedance performance requirements, proceed to step 7. If the comparison result meets the impedance performance requirements, proceed to step 8.

[0016] Step 7: Modify the S-parameter at the capacitor port in the multi-port cascaded model to change the capacitance value, complete the model iteration and replacement, and repeat steps 5 and 6.

[0017] Step 8: Obtain the optimized PDN curve and end the simulation.

[0018] According to the present invention based on the above scheme, the feature is that, in step 1, the extracted capacitor port s parameter includes the capacitance value.

[0019] According to the present invention based on the above scheme, the characteristic of the present invention is that, in step 2, the load chip port s parameters include the power network routing and planar information.

[0020] According to the present invention based on the above scheme, the feature is that, in step 3, the format of the multi-port s-parameter file is: S(n+1)P file, where n equals the number of capacitor ports.

[0021] According to the above-described scheme, the present invention is characterized in that, in step 4, a multi-port cascade model is generated by importing the multi-port s-parameter file into the ADS software.

[0022] According to the present invention based on the above scheme, the feature is that, in step 5, ADS software is used to perform PDN simulation on the multi-port cascaded model.

[0023] According to the present invention based on the above scheme, the characteristic is that, in step 6, the range of the observation frequency band is 100KHz-10MHz.

[0024] According to the present invention based on the above scheme, the impedance performance requirement in step 6 is that, within the observation frequency band, the PDN curve is located below the target impedance curve.

[0025] According to the present invention based on the above scheme, the characteristic is that, in step 6, the impedance value of the target impedance curve is 0.062 ohms.

[0026] According to the present invention based on the above scheme, the feature is that, between step 5 and step 6, a step is further included to verify the feasibility of the PDN impedance simulation method for the multi-port cascaded model, specifically:

[0027] Simulate the single-port power supply model of the load chip with multiple integrated capacitors to obtain the first PDN curve; define the PDN curve obtained from the simulation in step 5 as the second PDN curve, and compare the consistency between the second PDN curve and the first PDN curve.

[0028] According to the above-described solution, the beneficial effects of this invention are as follows:

[0029] This invention extracts all capacitor ports and generates a multi-port S-parameter file containing multiple capacitor ports. This file, along with the S-parameters of the load chip ports, forms a multi-port cascaded model to represent an equivalent power network. This isolates all capacitor ports, allowing for the placement of each capacitor's S-parameters in the ADS (Advanced Device Management) module. This enables iterative replacement of capacitor ports to optimize PDN impedance. Furthermore, all capacitor models integrated within the load chip are extracted and brought out to the outside of the load ports. During PDN curve optimization, the capacitance value is modified in the corresponding capacitor port's S-parameters to complete the iterative replacement without needing to call the capacitor model library again, modify the capacitor package name, or assign a new capacitor model to the load chip.

[0030] Therefore, this invention enables direct adjustment of parameters by reserving the S-parameter position of the capacitor port, resulting in very fast simulation speed for each iteration and improving the efficiency of power network (PDN) impedance simulation. Attached Figure Description

[0031] Figure 1 This is a flowchart of the method of the present invention;

[0032] Figure 2 This is a schematic diagram of the capacitor model library in POWER SI software.

[0033] Figure 3 This is a schematic diagram of a single-port power supply model in the prior art;

[0034] Figure 4 PDN curves for existing single-port power supply models;

[0035] Figure 5 This is a schematic diagram of the multi-port cascade model of the present invention;

[0036] Figure 6 The PDN curve of the multi-port cascaded model of the present invention;

[0037] Figure 7 This is the optimized PDN curve. Detailed Implementation

[0038] To better understand the purpose, technical solution, and technical effects of this invention, the invention will be further explained and described below in conjunction with the accompanying drawings and embodiments. It should be noted that similar reference numerals and letters in the following drawings indicate similar items; therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. It is also stated that the embodiments described below are only for explaining this invention and are not intended to limit this invention.

[0039] It should be noted that the term "multiple" means two or more, unless otherwise explicitly specified. POWER SI software is an RF circuit simulation software developed by Ansoft Corporation, capable of simulating various types of RF circuits, including microwave integrated circuits, antennas, filters, power amplifiers, etc., and can extract and analyze the S-parameters of circuits. S-parameters refer to scattering parameters, which are one of the important parameters describing the signal transmission characteristics in a circuit. They reflect the reflection and transmission of signals when they propagate between different ports, and therefore can be used to evaluate circuit performance. ADS software is a leading electronic design automation software suitable for RF, microwave, and signal integrity applications.

[0040] like Figure 1 As shown, a method to improve the simulation efficiency of power supply network (PDN) impedance is proposed. For each capacitor port, a multi-port S-parameter file containing multiple capacitor ports is generated. This file is then combined with the S-parameters of the load chip ports to form a multi-port cascaded model to represent the equivalent power supply network. Iterative replacements are performed on the capacitor ports to optimize the PDN impedance.

[0041] This invention extracts all capacitor models integrated within the load chip to the outside of the load ports by proposing all capacitor ports, thereby obtaining the s-parameters of capacitor ports that can be directly replaced. During the optimization of the power network (PDN) curve, the capacitance value of the corresponding capacitor port's s-parameter is modified to complete the replacement without having to call the capacitor model library again, modify the capacitor package name, or assign a new capacitor model to the load chip.

[0042] Therefore, this invention eliminates the need for iterations in full-board simulation, which is extremely slow and inefficient, potentially taking fifteen minutes or more per iteration. This invention allows for capacitor parameter adjustment simply by reserving the S-parameter positions of the capacitor ports, resulting in very fast simulation iterations that can be completed in less than a minute, thus improving the efficiency of power supply network (PDN) impedance simulation.

[0043] To better understand this technical solution, let's take the simulation of a VDD_CPU_AVS power supply as an example. First, let's understand the traditional simulation method, specifically:

[0044] Open the POWER SI software and assign the corresponding capacitor model to each package of capacitors associated with the power network. The capacitor models are retrieved from the capacitor model library. Please refer to the capacitor model library for details. Figure 2 Establish a power network, with only the load chip U1 remaining as the simulation port. All capacitor models are integrated within the load chip. Please refer to the model structure section. Figure 3 When the load chip is configured as a single port for simulation, the simulation will only produce a single-port S-parameter file, i.e., an S1P file, in the following format:

[0045] Port1_U1::VDD_CPU_AVS 0.1 1

[0046] Please refer to the PDN simulation results. Figure 4 Within the observation frequency band of 100kHz-10MHz, the PDN curve was not completely below the target impedance line (Y = 0.062 (Ohm)), indicating that the result did not meet the requirements and capacitor replacement was necessary.

[0047] In the POWER SI software, the capacitor model library is called again, the capacitor package name is modified, a new capacitor model is assigned to the load chip, a new model is created, and the full board simulation is performed again. However, the commonly used boards are now relatively large, and each time the model is changed and the PDN curve is simulated, the speed is very slow, requiring fifteen minutes or even more. That is, each iteration is very time-consuming and inefficient.

[0048] Secondly, the method of this invention patent is as follows, specifically:

[0049] Before simulation, each capacitor port and the load chip port are generated to obtain several capacitor port S-parameter models, resulting in a multi-port S-parameter file, i.e., an S(n+1)P file, where n equals the number of capacitor ports, in the following format:

[0050]

[0051] The table in the document only lists a portion of the capacitors, specifically including: C68, C70, C71, C74, C75, C247, C252, C256, C261, C267, C270, C276, C280, C286, C292, C298, C303, C308, C313, C318, C43, C68, C196, C198, C200, C202, C340, and C349, totaling 29 capacitors, which is a relatively large number.

[0052] Next, import the S(n+1)P file into ADS (Advanced Design system) software, place the corresponding capacitor model for each capacitor port, and combine it with the load chip to form a multi-port cascaded model containing multiple capacitor ports and one load port. Please refer to [link / reference]. Figure 5 This is used to replace the traditional single-port power supply model, equivalent power network.

[0053] Based on the multi-port cascaded model, a PDN curve (which can be defined as the second PDN curve) is obtained by simulating the PDN. Please refer to [link / reference]. Figure 6 By comparing the second PDN curve obtained from the initial simulation using this method with the first PDN curve obtained from the simulation using the traditional method, it can be determined that the second PDN curve obtained from the initial simulation using the method of this invention is consistent with the first PDN curve obtained from the initial simulation using the traditional single-port power supply model, indicating that the optimization method of extracting the capacitor port in this invention is feasible.

[0054] Similar to traditional methods, the PDN curve (curve A) is compared with the target impedance curve within the observation frequency range (100kHz-10MHz). If the impedance value of the PDN curve is higher than that of the target impedance curve in some frequency bands, the S-parameters are directly modified at the capacitor ports in the multi-port cascaded model to change the capacitor values. For example, the following capacitors C276, C280, C292, C298, C303, C308, C313, and C318 are replaced with 0.47uf, capacitor C286 is replaced with 1uf, capacitor C270 is replaced with 2.2uf, capacitors C256 and C267 are replaced with 4.7uf, and capacitor C198 is replaced with 100uf.

[0055] Resimulate the PDN impedance and compare the PDN curve (curve B) with the target impedance curve. Continue this process until the simulation results satisfy the condition that the PDN curve is below the target impedance curve. Please refer to [link to relevant documentation]. Figure 7 .

[0056] As can be seen, when replacements are needed, this invention can be performed at the capacitor ports in the multi-port cascaded model, requiring only a change in the capacitance value of the capacitor port's S-parameter. The same S-parameter can also be copied and pasted. Traditional methods, however, require returning to the modeling stage, retrieving the capacitor model from the capacitor model library, assigning a new capacitor model to the load chip, and remodeling. Therefore, this invention allows direct parameter adjustment via reserved capacitor ports, resulting in very fast simulation iterations and effectively improving the efficiency of power supply network (PDN) impedance simulation.

[0057] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0058] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for improving the impedance simulation efficiency of power supply network (PDN), characterized in that, For each capacitor port, a multi-port S-parameter file containing multiple capacitor ports is generated. This file, along with the S-parameters of the load chip ports, forms a multi-port cascade model to represent the equivalent power network. Iterative replacements are performed on the capacitor ports to optimize the PDN impedance. Specifically, the steps include: Step 1: Extract all capacitor ports. The extracted capacitor port s-parameters include the capacitance value, making the capacitor port independent of the load chip. Step 2: Extract the S-parameters of the load chip port; Step 3: Generate a multi-port S-parameter file containing multiple capacitor ports; Step 4: Use the multi-port S-parameter file to establish a multi-port cascade model, equivalent power network; Step 5: Simulate PDN impedance; Step 6: Compare the PDN curve with the target impedance curve within the observation frequency band. If the comparison result does not meet the impedance performance requirements, proceed to step 7. If the comparison result meets the impedance performance requirements, proceed to step 8. Step 7: Modify the S-parameter at the capacitor port in the multi-port cascaded model to change the capacitance value, complete the model iteration and replacement, and repeat steps 5 and 6. Step 8: Obtain the optimized PDN curve and end the simulation.

2. The method for improving the impedance simulation efficiency of a power supply network (PDN) according to claim 1, characterized in that, In step 2, the load chip port s parameters include the power network routing and planar information.

3. The method for improving the impedance simulation efficiency of a power supply network (PDN) according to claim 1, characterized in that, In step 3, the format of the multi-port s-parameter file is: S(n+1)P file, where n equals the number of capacitor ports.

4. The method for improving the impedance simulation efficiency of a power supply network (PDN) according to claim 1, characterized in that, In step 4, a multi-port cascade model is generated by importing the multi-port s-parameter file into the ADS software.

5. The method for improving the impedance simulation efficiency of a power supply network (PDN) according to claim 1, characterized in that, In step 6, the observation frequency band ranges from 100kHz to 10MHz.

6. The method for improving the impedance simulation efficiency of a power supply network (PDN) according to claim 1, characterized in that, In step 6, the impedance performance requirement is that, within the observation frequency band, the PDN curve is located below the target impedance curve.

7. The method for improving the impedance simulation efficiency of a power supply network (PDN) according to claim 1, characterized in that, In step 6, the impedance value of the target impedance curve is 0.062 ohms.

8. The method for improving the impedance simulation efficiency of a power supply network (PDN) according to claim 1, characterized in that, Between steps 5 and 6, there is also a step to verify the feasibility of the PDN impedance simulation method for the multi-port cascaded model, specifically: Simulate the single-port power supply model of the load chip with multiple integrated capacitors to obtain the first PDN curve; define the PDN curve obtained from the simulation in step 5 as the second PDN curve, and compare the consistency between the second PDN curve and the first PDN curve.

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