Electronic device

Abstract

The present disclosure provides an electronic device, which includes a substrate, a data line, an insulating layer, a metal layer and a transparent conductive layer. The data line is disposed on the substrate. The insulating layer is disposed on the data line. The metal layer is disposed on the insulating layer. The transparent conductive layer is disposed on the metal layer and electrically connected to the metal layer. The electronic device of the present disclosure can reduce the impedance of the transparent conductive layer, can improve the visual visibility problem caused by metal reflection, can reduce the probability of light entering the transistor semiconductor layer or can increase the aperture ratio.

Description

[0001] Related divisional application

[0002] This disclosure is a divisional application of the invention patent application filed on September 4, 2020, with application number 202010922405.6 and the invention title "Electronic Device". Technical Field

[0003] This disclosure relates to an electronic device, and more particularly to an electronic device that can reduce the impedance of a transparent conductive layer, improve visual visibility problems caused by metallic reflection, or increase the aperture ratio. Background Technology

[0004] Flat panel displays are widely used in electronic devices such as mobile phones, televisions, monitors, tablets, automotive displays, wearable devices, and desktop computers. With the rapid development of electronic products, the demands for display quality are increasing, leading to continuous improvements in electronic devices towards larger and higher resolution displays. Summary of the Invention

[0005] This disclosure provides an electronic device that can reduce the impedance of a transparent conductive layer, improve visual visibility problems caused by metallic reflection, or increase the aperture ratio.

[0006] According to embodiments disclosed herein, an electronic device includes a substrate, a data line, an insulating layer, a metal layer, and a transparent conductive layer. The data line is disposed on the substrate. The insulating layer is disposed on the data line. The metal layer is disposed on the insulating layer. The transparent conductive layer is disposed on the metal layer and electrically connected to the metal layer.

[0007] According to embodiments disclosed herein, an electronic device includes a substrate, a data line, and a metal layer. The data line is disposed on the substrate. The metal layer is disposed on and overlaps the data line. The material of the metal layer includes molybdenum, titanium, chromium, or oxides thereof. The metal layer and the data line have a first overlap region extending along a first direction and a second overlap region extending along a second direction, wherein the first direction is different from the second direction. Attached Figure Description

[0008] The accompanying drawings are included to further illustrate the present disclosure, and are incorporated in and form a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0009] Figure 1A This is a top view schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0010] Figure 1B for Figure 1A An enlarged diagram of region AA;

[0011] Figure 1C for Figure 1B A cross-sectional view of the electronic device along section line A-A';

[0012] Figure 1D for Figure 1B A cross-sectional schematic diagram of the electronic device along section line B-B';

[0013] Figure 1E for Figure 1A A cross-sectional schematic diagram of the electronic device along section line C-C';

[0014] Figure 2 This is a top view schematic diagram of an electronic device according to another embodiment of the present disclosure;

[0015] Figure 3 This is a top view schematic diagram of an electronic device according to another embodiment of the present disclosure;

[0016] Figure 4 This is a schematic cross-sectional view of an electronic device according to another embodiment of the present disclosure;

[0017] Figure 5 This is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure.

[0018] Explanation of icon numbers

[0019] 100, 100a, 100b, 100c, 100d: Electronic devices;

[0020] 101: Display area;

[0021] 102: Non-display area;

[0022] 1021: Demultiplexer circuit section;

[0023] 1022: Electrostatic discharge protection circuit area;

[0024] 1023: Fan-out area;

[0025] 1024: Driver chip area;

[0026] 110: substrate;

[0027] 120, 280: Transistors;

[0028] 130, 230, 231: First transparent conductive layer;

[0029] 140, 162, 164, 165: Insulation layer;

[0030] 150, 150a, 150b, 150c, 250: Metal layer;

[0031] 160: Buffer layer;

[0032] 161: Shielding layer;

[0033] 163: Dielectric layer;

[0034] 163a, 163b, 164a, 165a, 165b, 165c, 180c1, 180d1: Openings;

[0035] 170, 270: Second transparent conductive layer;

[0036] 180, 180c, 180d: Black matrix layer;

[0037] 190: Another substrate;

[0038] 191, 192, 193: Color filter layer;

[0039] 194, 195: Boundary;

[0040] 210, 211: Metal pads;

[0041] 220, 221: Adapter pads;

[0042] AA, BB: Regions;

[0043] DL: Data cable;

[0044] DLa: Partial;

[0045] GE: Gate;

[0046] GI: Gate insulating layer;

[0047] GIa, GIb: Openings;

[0048] SD1: Source;

[0049] SD2: Drain;

[0050] SE: Semiconductor layer;

[0051] SL: Scan line;

[0052] W1, W2, W3, W4: Width;

[0053] W5: Another width;

[0054] X, Y, Z: Direction. Detailed Implementation

[0055] This disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of brevity, many of the drawings in this disclosure depict only a portion of the electronic device, and certain components in the drawings are not drawn to scale. Furthermore, the number and dimensions of the components in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0056] In the following description and claims, the words “containing” and “including” are open-ended terms, and therefore should be interpreted as “containing but not limited to…”.

[0057] It should be understood that when an element or membrane is referred to as being "on" or "connected" to another element or membrane, it can be directly on or directly connected to that other element or membrane, or there may be an inserted element or membrane between them (indirect cases). Conversely, when an element is referred to as being "directly" on or "directly connected" to another element or membrane, there may be no inserted element or membrane between them.

[0058] Although the terms first, second, third… can be used to describe multiple components, the components are not limited to these terms. These terms are used only to distinguish a single component from other components in the specification. The same terms may not be used in the claims, but rather replaced by first, second, third… in the order of the elements declared in the claims. Therefore, in the following description, a first component may be a second component in the claims.

[0059] In some embodiments disclosed herein, terms such as “connection” and “interconnection”, unless specifically defined, may refer to two structures in direct contact, or to two structures not in direct contact, wherein another structure is disposed between the two structures. Furthermore, these terms regarding engagement and connection may also include situations where both structures are movable or both structures are fixed. In addition, the term “coupled” includes any direct and indirect electrical connection means.

[0060] In this disclosure, length and width can be measured using an optical microscope, and thickness can be measured from cross-sectional images using an electron microscope, but these methods are not limited to these. Furthermore, any two values ​​or directions used for comparison may contain a certain degree of error.

[0061] The electronic devices disclosed herein may include, but are not limited to, display devices, antenna devices, sensing devices, touch displays, curved displays, or free-shape displays. The electronic devices may be bendable or flexible. The electronic devices may include, for example, light-emitting diodes (LEDs), liquid crystals, fluorescent, phosphorescent, quantum dot (QD) displays, other suitable display media, or combinations thereof, but are not limited to these. Light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), inorganic light-emitting diodes (LEDs), mini LEDs, micro LEDs, or quantum dot LEDs (e.g., QLEDs, QDLEDs), or other suitable materials or any arrangement or combination thereof, but are not limited to these. Display devices may include, for example, video wall displays, but are not limited to these. Antenna devices may be, for example, liquid crystal antennas, but are not limited to these. Antenna devices may include, for example, antenna splicing devices, but are not limited to these. It should be noted that the electronic device can be any of the aforementioned arrangements and combinations, but is not limited thereto. Furthermore, the electronic device can be rectangular, circular, polygonal, have curved edges, or other suitable shapes. The electronic device may have peripheral systems such as drive systems, control systems, light source systems, and shelving systems to support display devices, antenna devices, or splicing devices. The following description will use electronic devices to illustrate the contents of this disclosure, but this disclosure is not limited thereto.

[0062] It should be understood that the features in the following embodiments can be replaced, recombined, or mixed to complete other embodiments without departing from the spirit of this disclosure. Features between embodiments can be arbitrarily mixed and combined as long as they do not violate the spirit of the invention or conflict with it.

[0063] Reference will now be made in detail to the exemplary embodiments disclosed herein, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0064] Figure 1A This is a top view schematic diagram of an electronic device according to an embodiment of the present disclosure. Figure 1B for Figure 1A An enlarged diagram of region AA. Figure 1C for Figure 1B A cross-sectional schematic diagram of the electronic device along section line A-A'. Figure 1D for Figure 1B A schematic cross-sectional view of the electronic device along section line B-B'. Figure 1E for Figure 1A A cross-sectional view of the electronic device along section line C-C'. For clarity and ease of explanation, the accompanying drawings are provided. Figure 1A , Figure 1B Several components of the electronic device are omitted.

[0065] Please refer to the following at the same time Figures 1A to 1E The electronic device 100 of this embodiment can be divided into a display area 101 and a non-display area 102, and the electronic device 100 includes a substrate 110, a transistor 120, a data line DL, a first transparent conductive layer 130, an insulating layer 140, and a metal layer 150. The substrate 110 may include a rigid substrate, a flexible substrate, or a combination thereof. For example, the material of the substrate 110 may include glass, quartz, sapphire, ceramic, polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), other suitable substrate materials, or combinations thereof, but is not limited thereto.

[0066] In this embodiment, transistor 120 is disposed on substrate 110. Transistor 120 includes a gate GE, a portion of gate insulating layer GI, source SD1, drain SD2, and semiconductor layer SE, but is not limited thereto. Gate insulating layer GI may have openings GIa and GIb to expose a portion of semiconductor layer SE. In this embodiment, the material of source SD1 and / or drain SD2 may include transparent conductive materials or non-transparent conductive materials, such as indium tin oxide, indium zinc oxide, indium oxide, zinc oxide, tin oxide, metallic materials (e.g., aluminum, molybdenum, copper, silver, etc.), other suitable materials, or combinations thereof, but is not limited thereto. The material of semiconductor layer SE may include amorphous silicon, low-temperature polycrystalline silicon (LTPS), metal oxides (e.g., indium gallium zinc oxide IGZO), other suitable materials, or combinations thereof, but is not limited thereto. In some embodiments, the structure of transistor 120 is not limited thereto, and may also be, for example, a bottom-gate type transistor, or may be changed to a dual-gate transistor or other suitable transistor as needed. In this embodiment, electronic device 100 also includes scan line SL. The scan line SL extends along the X direction, and the data line DL extends along the Y direction. The normal direction of the substrate 110 is the Z direction. Directions X, Y, and Z are different from each other and are perpendicular to each other. The scan line SL is disposed on the substrate 110 and electrically connected to the transistor 120, and the data line DL is disposed on the substrate 110 and electrically connected to the transistor 120. Specifically, the scan line SL is electrically connected to the transistor 120 through its gate GE, and the data line DL is electrically connected to the transistor 120 through its source SD1.

[0067] In this embodiment, the electronic device 100 further includes a buffer layer 160, a shielding layer 161, an insulating layer 162, a dielectric layer 163, an insulating layer 164, an insulating layer 165, a second transparent conductive layer 170, a black matrix layer 180, another substrate 190, and a plurality of color filter layers 191, 192, and 193. The insulating layer 140, buffer layer 160, insulating layer 162, dielectric layer 163, insulating layer 164, and insulating layer 165 may be single-layer or multi-layer structures, and may include, for example, organic materials, inorganic materials, or combinations thereof, but are not limited thereto. In this embodiment, the material of the shielding layer 161 may be, for example, a metallic material or other light-shielding material. In some embodiments, the electronic device 100 may also omit the shielding layer (not shown).

[0068] In this embodiment, both the buffer layer 160 and the shielding layer 161 are disposed between the transistor 120 and the substrate 110, and the shielding layer 161 is disposed corresponding to the gate GE. An insulating layer 162 is disposed between the gate GE and the gate insulating layer GI, and the insulating layer 162 is disposed corresponding to the gate GE. A dielectric layer 163 is disposed between the source SD1 (or drain SD2) and the gate insulating layer GI to cover the gate GE and the gate insulating layer GI. The dielectric layer 163 may have openings 163a and 163b. Opening 163a connects to opening GIa to expose a portion of the semiconductor layer SE, and opening 163b connects to opening GIb to expose a portion of the semiconductor layer SE.

[0069] In this embodiment, the source electrode SD1 and the drain electrode SD2 are respectively disposed on the dielectric layer 163. The source electrode SD1 may also be disposed within the opening 163a of the dielectric layer 163 and the opening GIa of the gate insulating layer GI, so that the source electrode SD1 can be electrically connected to the semiconductor layer SE through the opening 163a and the opening GIa. The drain electrode SD2 may also be disposed within the opening 163b of the dielectric layer 163 and the opening GIb of the gate insulating layer GI, so that the drain electrode SD2 can be electrically connected to the semiconductor layer SE through the opening 163b and the opening GIb.

[0070] In this embodiment, an insulating layer 164 is disposed on the transistor 120. The insulating layer 164 covers the source electrode SD1, the drain electrode SD2, and the dielectric layer 163. The insulating layer 164 and the substrate 110 are respectively disposed on opposite sides of the transistor 120. The insulating layer 164 has an opening 164a to expose a portion of the drain electrode SD2.

[0071] In this embodiment, an insulating layer 165 is disposed on an insulating layer 164. The insulating layer 165 and the transistor 120 are respectively disposed on opposite sides of the insulating layer 164. The insulating layer 165 has an opening 165a. The opening 165a communicates with the opening 164a to expose a portion of the drain SD2.

[0072] In this embodiment, the first transparent conductive layer 130 is disposed on the data line DL, and the first transparent conductive layer 130 may be, for example, a pixel electrode or a common electrode, but is not limited thereto. For example, in this embodiment, when the first transparent conductive layer 130 is a pixel electrode, the first transparent conductive layer 130 is disposed on the insulating layer 165 and located between the insulating layers 140 and 165. The first transparent conductive layer 130 may also be disposed within the openings 165a and 164a, so that the first transparent conductive layer 130 can be electrically connected to the drain SD2 of the transistor 120 through the openings 165a and 164a of the insulating layers 165 and 164a.

[0073] In this embodiment, the insulating layer 140 is disposed on the first transparent conductive layer 130 and within the opening 165a. The insulating layer 140 covers the first transparent conductive layer 130 and the insulating layer 165a.

[0074] In this embodiment, the second transparent conductive layer 170 is disposed on the insulating layer 140, and the second transparent conductive layer 170 may be, for example, a pixel electrode or a common electrode, but is not limited thereto. For example, in this embodiment, when the second transparent conductive layer 170 is a common electrode, the second transparent conductive layer 170 may also be disposed within the opening 165a, so that the insulating layer 140 is located between the second transparent conductive layer 170 and the first transparent conductive layer 130. In this embodiment, the material of the second transparent conductive layer 170 may include, for example, a transparent conductive material, but is not limited thereto.

[0075] In this embodiment, the metal layer 150 is disposed, for example, on the insulating layer 140 of the substrate 110, such that the metal layer 150 is located between the second transparent conductive layer 170 and the first transparent conductive layer 130, but is not limited thereto. In this embodiment, since the metal layer 150 can also directly contact the second transparent conductive layer 170, the metal layer 150 can be electrically connected to the second transparent conductive layer 170, thereby reducing the impedance of the second transparent conductive layer 170 and improving signal uniformity. Furthermore, in this embodiment, the thickness T of the metal layer 150, measured in the normal direction (i.e., direction Z) of the substrate 110, is, for example, less than 2000 angstroms. The metal layer 150 can be used to block 99% of light transmission, but is not limited thereto. In some embodiments, if there are other electrical considerations (e.g., as a trace), the thickness of the metal layer 150 may be, for example, less than 5000 angstroms to achieve better electrical transmission characteristics.

[0076] Furthermore, in the top view of the electronic device 100 (e.g.) Figure 1B As shown, since the metal layer 150 is disposed on and overlaps the data line DL (or source SD1), when the material of the metal layer 150 is a low-reflection metal material, the metal layer 150 can be used to shield the metallic reflection of the data line DL (or source SD1) to improve the visual visibility problem caused by metallic reflection. In this embodiment, the material of the metal layer 150 may include a low-reflection metal material or a non-low-reflection metal material, but is not limited thereto. For example, low-reflection metal materials may include molybdenum, titanium, chromium, the above-mentioned oxides, the above-mentioned nitrides, other suitable materials, or combinations thereof, but are not limited thereto. Low-reflection metal materials may include silver, aluminum, gold, copper, the above-mentioned oxides, the above-mentioned nitrides, other suitable materials, or combinations thereof, but are not limited thereto. In this embodiment, the metal layer 150 may be a single-layer metal structure or a multi-layer film stacked metal structure.

[0077] In this embodiment, in the top view of the electronic device 100 (e.g.) Figure 1B As shown, measured in the extension direction (i.e., direction X) of the scan line SL, the width W1 of the metal layer 150 is, for example, greater than the width W2 of the data line DL, to shield the data line DL. In some embodiments, the width W1 of the metal layer 150 is, for example, less than 3 micrometers (μm), but is not limited thereto. Furthermore, in this embodiment, since the metal layer 150 is disposed on the data line DL (or source SD1), the width W1 of the metal layer 150 is greater than the width W2 of the data line DL, and the material of the metal layer 150 is a low-reflection metal material, the metal layer 150 can be used to replace the existing black matrix layer to shield the data line DL (or source SD1). That is, by setting the metal layer 150, it is not necessary to set an additional black matrix layer to shield the data line DL (or source SD1), thereby avoiding the problems of residue and rounded corners in the existing black matrix layer which needs to shield both the data line DL and the scan line SL at the same time, and thus also avoiding the problem of aperture ratio loss. Furthermore, since the existing black matrix layer cannot achieve a fine linewidth (e.g., less than 3 micrometers), replacing the existing black matrix layer with a metal layer 150 with a width W1 less than 3 micrometers also has the effect of increasing the aperture ratio.

[0078] In this embodiment, in the top view of the electronic device 100 (e.g.) Figure 1B As shown, the metal layer 150 may overlap the entire data line DL, but is not limited thereto. In some embodiments, the metal layer 150 may also overlap only a portion of the data line DL, such as... Figure 2 As shown.

[0079] In this embodiment, although the first transparent conductive layer 130 is used as a pixel electrode and the second transparent conductive layer 170 is used as a common electrode, so that the metal layer 150 can directly contact the common electrode without contacting the pixel electrode (i.e., the metal layer 150 can directly contact the second transparent conductive layer 170 without contacting the first transparent conductive layer 130), or the metal layer 150 can directly contact the pixel electrode without contacting the common electrode (i.e., the metal layer 150 can directly contact the first transparent conductive layer 130 without contacting the second transparent conductive layer 170), this is not a limitation. Direct contact between the metal layer 150 and the first transparent conductive layer 130 can reduce the probability of light entering the transistor semiconductor layer SE. In some embodiments, the first transparent conductive layer may also be a common electrode and the second transparent conductive layer may be a pixel electrode (not shown). Therefore, when the first transparent conductive layer 130 is a common electrode and the second transparent conductive layer 170 is a pixel electrode, the metal layer 150 can also directly contact the common electrode without contacting the pixel electrode. That is, the metal layer 150 can directly contact the first transparent conductive layer 130 without contacting the second transparent conductive layer 170 (not shown). Direct contact between the metal layer 150 and the first transparent conductive layer 130 can reduce the probability of light entering the transistor semiconductor layer SE. Alternatively, the metal layer 150 can directly contact the pixel electrode without contacting the common electrode. That is, the metal layer 150 can directly contact the second transparent conductive layer 170 without contacting the first transparent conductive layer 130, but this is not a limitation.

[0080] In this embodiment, the black matrix layer 180 is disposed on the scan line SL and overlaps the entire scan line SL. Specifically, the black matrix layer 180 and the metal layer 150 are different layers. For example, the black matrix layer 180 is disposed on another substrate 190 and located between the other substrate 190 and the multiple color filter layers 191, 192, and 193, but this is not a limitation. In some embodiments, the black matrix layer 180 may also be disposed on the substrate 110 and be a different layer from the metal layer 150, such as... Figure 4 as well as Figure 5 As shown. Furthermore, in this embodiment, measured in the extension direction (i.e., direction Y) of the data line DL, the width W3 of the black matrix layer 180 is, for example, greater than the width W4 of the scan line SL, in order to mask the scan line SL.

[0081] In this embodiment, multiple color filter layers 191, 192, and 193 are disposed on another substrate 190. The color filter layers 191, 192, and 193 can be, for example, blue, red, and green filter layers, respectively, but are not limited thereto. The boundaries 194 between color filter layers 191 and 192, 195 between color filter layers 192 and 193, and 191 and 193 (not shown) are parallel to the extension direction of the scan line SL (i.e., direction X) and can be considered as mixed or pale color regions. In this embodiment, since the metal layer 150 can be disposed corresponding to the boundaries 194 and 195 between two adjacent color filter layers, mixed or pale color regions can be masked to improve contrast. For example, the metal layer 150 may be disposed corresponding to the boundary 194 between adjacent color filter layers 191 and 192, and the metal layer 150 may also be disposed corresponding to the boundary 195 between adjacent color filter layers 192 and 193.

[0082] In this embodiment, although the metal layer 150 is disposed on the substrate 110 and the black matrix layer 180 is disposed on another substrate 190, this disclosure does not limit the placement of the metal layer 150 and the black matrix layer 180, as long as the metal layer 150 is disposed on the data line DL (or the source SD1) and the black matrix layer 180 is disposed on the scan line SL. That is, in some embodiments, the metal layer may be disposed on another substrate and the black matrix layer may be disposed on the substrate, such as... Figure 4 As shown. In some embodiments, both the metal layer and the black matrix layer may be disposed on the substrate, such as... Figure 5 As shown. In some embodiments, the metal layer and the black matrix layer may also be disposed on another substrate (not shown).

[0083] Please refer to the following at the same time: Figure 1A and Figure 1E In this embodiment, the non-display area 102 may include a de-multiplexer circuit area 1021, an electrostatic discharge protection circuit area 1022, a fanout area 1023, and a driver chip area 1024. A metal layer 250 may also be disposed in the multiplexer circuit area 1021, the electrostatic discharge protection circuit area 1022, and the fanout area 1023 in the non-display area 102, thereby enabling the transmission of signals from the driver chip area 1024 to the display area 101.

[0084] Specifically, please refer to Figure 1EIn this embodiment, the electronic device 100 further includes metal pads 210 and 211, adapter pads 220 and 221, a first transparent conductive layer 230 and 231, a metal layer 250, and a second transparent conductive layer 270. Region BB can be considered as an enlarged schematic diagram of the multiplexer circuit region 1021, the electrostatic discharge protection circuit region 1022, and the fan-out region 1023, and is schematically shown as a transistor 280, but is not limited thereto. Metal pads 210 and 211 are disposed on the dielectric layer 163 and are on the same layer as the source SD1 (or drain SD2). Adapter pads 220 and 221 are disposed on the insulating layer 164 and are electrically connected to metal pads 210 and 211, respectively. The first transparent conductive layer 230 and 231 are disposed on the insulating layer 165. The first transparent conductive layer 230 and the first transparent conductive layer 231 are respectively disposed within the openings 165b and 165c of the insulating layer 165, so that the first transparent conductive layer 230 and the first transparent conductive layer 231 can be electrically connected to the transition pad 220 and the transition pad 221, respectively. The metal layer 250 is disposed on the insulating layer 140 and is also disposed within the openings 165b and 165c of the insulating layer 165, so that the metal layer 250 can be electrically connected to the transparent conductive layer 230 and the transparent conductive layer 231. The second transparent conductive layer 270 is disposed on the metal layer 250 and can directly contact and be electrically connected to the metal layer 250.

[0085] Therefore, when the metal pad 211 receives a signal from the driver chip area 1024, it can be transmitted to the display area 101 through the adapter pad 221, the first transparent conductive layer 231, the metal layer 250, the transparent conductive layer 230, the adapter pad 220, and the metal pad 210. Thus, in this embodiment, the metal layer 250 disposed in the non-display area 102 can be a transfer layer structure to transmit the signal from the driver chip area 1024 to the display area 101, thereby reducing the load on the signal transmission of the second transparent conductive layer 270.

[0086] In this embodiment, although the aforementioned region BB can be considered as an enlarged schematic diagram of the multiplexer circuit region 1021, the electrostatic discharge protection circuit region 1022, and the fan-out region 1023, it is not limited thereto. That is, in some embodiments, region BB can also be considered as an enlarged schematic diagram of the multiplexer circuit region 1021 and the electrostatic discharge protection circuit region 1022. In some embodiments, region BB can also be considered as an enlarged schematic diagram of the multiplexer circuit region 1021.

[0087] In summary, in the electronic device 100 of this disclosed embodiment, by disposing a metal layer 150 on and overlapping the data line DL, the metal layer 150 can be used to shield the data line DL, thereby improving visual visibility issues caused by metallic reflection from the data line DL. Furthermore, since the metal layer 150 can replace the existing black matrix layer to shield the data line DL, the residual and rounded corner issues caused by the existing black matrix layer during its placement are avoided, thus preventing aperture loss. Moreover, since the width W1 of the metal layer 150 can be smaller than the line width of the black matrix layer, using the metal layer 150 to replace the existing black matrix layer also increases the aperture ratio. Additionally, by electrically connecting the metal layer 150 to the second transparent conductive layer 170, the impedance of the second transparent conductive layer 170 can be reduced, improving signal uniformity. In addition, by placing the metal layer 250 in the non-display area 102 of the electronic device 100 and making the metal layer 250 electrically connected to the second transparent conductive layer 270, the metal layer 250 can be used as a transfer structure to reduce the load on the second transparent conductive layer 270.

[0088] Other embodiments will be listed below for illustration. It must be noted that the following embodiments use the component reference numerals and some content from the foregoing embodiments, with the same reference numerals representing the same or similar components, and descriptions of identical technical content omitted. For explanations of the omitted parts, please refer to the foregoing embodiments; these will not be repeated in the following embodiments.

[0089] Figure 2 This is a top view schematic diagram of an electronic device according to another embodiment of this disclosure. Please also refer to... Figure 1B and Figure 2 The electronic device 100a in this embodiment is generally similar to Figure 1B The electronic device 100 is described in the same way as the other two embodiments, so the same and similar components will not be repeated here. In the top view of the electronic device 100a in this embodiment, the metal layer 150a overlaps only a portion of the data line DL, DLa. In detail, the metal layer 150a overlaps at least the portion of the data line DL exposed by the black matrix layer 180, thereby shielding the metallic reflection of the data line DL and reducing visual visibility problems caused by metallic reflection.

[0090] Figure 3 This is a top view schematic diagram of an electronic device according to another embodiment of this disclosure. Please also refer to... Figure 1B and Figure 3 The electronic device 100b in this embodiment is generally similar to Figure 1BThe electronic device 100 is described in both embodiments, and therefore, the same and similar components will not be repeated here. In the top view of the electronic device 100b in this embodiment, the metal layer 150b may also be disposed on the scan line SL and the data line DL, so that the metal layer 150b may also overlap the scan line SL and the data line DL. That is, in the top view of the electronic device 100b in this embodiment, the metal layer 150b has a grid-like structure to simultaneously overlap and shield the data line DL and the scan line SL. Furthermore, measured in the extension direction (i.e., direction Y) of the data line DL, another width W5 of the metal layer 150b is greater than the width W4 of the scan line SL, and the width W3 of the black matrix layer 180 is greater than the other width W5 of the metal layer 150b.

[0091] Figure 4 This is a cross-sectional schematic diagram of an electronic device according to another embodiment of this disclosure. Please also refer to... Figure 1D and Figure 4 The electronic device 100c in this embodiment is generally similar to Figure 1D The electronic device 100c of this embodiment has the same and similar components described in both embodiments, so they will not be repeated here. In the electronic device 100c of this embodiment, the metal layer 150c is disposed on another substrate 190, and the black matrix layer 180c is disposed on the substrate 110.

[0092] In detail, in this embodiment, the metal layer 150c is disposed on the source electrode SD1 (or data line DL) and between another substrate 190 and the color filter layers 191, 192, and 193. The metal layer 150c may be disposed corresponding to the boundary 194 between adjacent color filter layers 191 and 192, and the metal layer 150c may also be disposed corresponding to the boundary 195 between adjacent color filter layers 192 and 193.

[0093] In this embodiment, the black matrix layer 180c is disposed on the gate GE (or scan line SL) and between the transistor 120 and the insulating layer 165. The black matrix layer 180c may have an opening 180c1. The opening 180c1 connects to the opening 164a of the insulating layer 164 to expose a portion of the drain SD2. Furthermore, since the opening 165a of the insulating layer 165 can connect to the openings 180c1 and 164a, the first transparent conductive layer 130 can also be disposed within the openings 165a, 180c1, and 164a.

[0094] Figure 5 This is a cross-sectional schematic diagram of an electronic device according to another embodiment of this disclosure. Please also refer to... Figure 1C and Figure 5 The electronic device 100d in this embodiment is generally similar to Figure 1CThe electronic device 100d of this embodiment has the same and similar components, so they will not be repeated here. In the electronic device 100d of this embodiment, the black matrix layer 180d is disposed on the substrate 110.

[0095] In detail, in this embodiment, the black matrix layer 180d is disposed on the gate GE (or scan line SL) and between the transistor 120 and the insulating layer 165. The black matrix layer 180d may have an opening 180d1. The opening 180d1 connects to the opening 164a of the insulating layer 164 to expose a portion of the drain SD2. Furthermore, since the opening 165a of the insulating layer 165 can connect to the openings 180d1 and 164a, the first transparent conductive layer 130 can also be disposed within the openings 165a, 180d1, and 164a.

[0096] In summary, in the electronic device of this disclosed embodiment, by placing a metal layer on the data line and overlapping it with the data line, the metal layer can be used to shield the data line, thus improving visual visibility issues caused by metallic reflection from the data line. Furthermore, since the metal layer can replace the existing black matrix layer to shield the data line, the residual and rounded corner problems caused by the existing black matrix layer during placement are avoided, thereby preventing aperture ratio loss. Moreover, since the linewidth of the metal layer can be smaller than the linewidth of the black matrix layer, using a metal layer to replace the existing black matrix layer also increases the aperture ratio. In addition, by electrically connecting the metal layer to the transparent conductive layer, the impedance of the transparent conductive layer can be reduced, improving signal uniformity and reducing the probability of light entering the transistor semiconductor layer. Furthermore, by placing the metal layer in the non-display area of ​​the electronic device and electrically connecting it to the transparent conductive layer, the metal layer can be used as a signal transfer layer, reducing the load on the transparent conductive layer.

[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions disclosed herein, and are not intended to limit them. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments disclosed herein.

Claims

1. An electronic device, characterized in that, include: substrate; Data cables are disposed on the substrate; An insulating layer is disposed on the data line and has an opening; A metal layer is disposed on the insulating layer; as well as A transparent conductive layer is disposed on the metal layer and electrically connected to the metal layer. In this configuration, at least a portion of the transparent conductive layer is in direct contact with at least a portion of the metal layer, and the at least a portion of the transparent conductive layer and the at least a portion of the metal layer are disposed within the opening.

2. The electronic device according to claim 1, characterized in that, Also includes: A scan line is disposed on the substrate, wherein a portion of the metal layer overlaps the scan line, and the portion of the metal layer extends along the extension direction of the scan line.

3. The electronic device according to claim 1, characterized in that, Also includes: A scan line is disposed on the substrate, wherein, measured in the extension direction of the data line, the width of the metal layer is greater than the width of the scan line.

4. The electronic device according to claim 1, characterized in that, Also includes: A scan line is disposed on the substrate, wherein, measured in the extension direction of the scan line, another width of the metal layer is greater than the width of the data line.

5. The electronic device according to claim 1, characterized in that, The material of the metal layer includes molybdenum, titanium, chromium, or oxides of molybdenum, oxides of titanium-molybdenum, or oxides of chromium-molybdenum.

6. The electronic device according to claim 1, characterized in that, Also includes: Two adjacent scan lines are disposed on the substrate, wherein the portion of the data line located between the two adjacent scans has a bend.

7. The electronic device according to claim 1, characterized in that, Also includes: Scan lines are disposed on the substrate and intersect with the data lines.

8. The electronic device according to claim 7, characterized in that, The opening overlaps with the scan line.

9. An electronic device, characterized in that, include: substrate; Data cables are disposed on the substrate; An insulating layer is disposed on the data line and has an opening; A metal layer is disposed on the data line and overlaps the data line, wherein the material of the metal layer includes molybdenum, titanium, chromium or an oxide of molybdenum, an oxide of titanium-molybdenum or an oxide of chromium-molybdenum; A transparent conductive layer is disposed on the metal layer and electrically connected to the metal layer; and Two adjacent scan lines are disposed on the substrate, wherein the portion of the data line located between the two adjacent scans has a turning portion; The metal layer and the data line have a first overlapping area extending along a first direction and a second overlapping area extending along a second direction, wherein the first direction is different from the second direction. In this configuration, at least a portion of the transparent conductive layer is in direct contact with at least a portion of the metal layer, and the at least a portion of the transparent conductive layer and the at least a portion of the metal layer are disposed within the opening.

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