Display panel, driving method thereof, and display device

Abstract

The application discloses a display panel and a driving method thereof, and a display device, and belongs to the technical field of display. The display area of the display panel comprises a plurality of pixel units and a plurality of gate lines, the non-display area comprises a boosting circuit, and a boosting unit is electrically connected with at least one gate line. The boosting unit comprises a charging module, a bootstrap module and an initialization module. The bootstrap module comprises a first module and a first capacitor. The first end of the first module is electrically connected with a second control signal line. The control end of the initialization module is electrically connected with a first control signal line. The first end of the initialization module is respectively electrically connected with the second end of the first module and the second pole of the first capacitor. The second end of the initialization module is electrically connected with a first negative potential signal line. The voltage value provided by the second control signal line is greater than the voltage value provided by the first negative potential signal line. The driving method of the display panel is applied to the above-mentioned display panel. The display device comprises the above-mentioned display panel. The application can reduce the driving power consumption and ensure the display quality.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a display panel and its driving method and display device. Background Technology

[0002] In the field of display technology, the pixel array of a display panel typically includes multiple rows of gate lines and multiple columns of data lines that cross and are insulated from them. Generally, the driving of the gate lines can be achieved through a bonded integrated driver circuit (IC).

[0003] Currently, the gate line voltage of some display devices can generally be directly provided by the IC. As customers' demand for high voltage for writing data becomes stronger, the upper and lower voltages of the gate line voltage have to be further increased and decreased. As a result, the voltage difference that the IC needs to provide is getting larger and larger, which makes the driving capability required by the IC higher and the power consumption higher and higher.

[0004] Therefore, how to avoid power waste during panel driving is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of this, the present invention provides a display panel and its driving method and display device to solve the problem of power consumption waste during panel driving in the prior art.

[0006] This invention discloses a display panel, comprising: a display area and a non-display area; the display area includes multiple pixel units and multiple gate lines, the gate lines being electrically connected to the pixel units; the non-display area includes a boost circuit, the boost circuit including multiple boost units, the boost units being electrically connected to at least one gate line; each boost unit includes a charging module, a bootstrap module, and an initialization module electrically connected, the bootstrap module including at least a first module and a first capacitor; the control terminal of the charging module is electrically connected to a first control signal line, the first end of the charging module is electrically connected to the control terminal of the charging module, and the second end of the charging module is electrically connected to the gate line, the control terminal of the first module, and the first electrode of the first capacitor; the first end of the first module is electrically connected to a second control signal line, and the second end of the first module is electrically connected to the second electrode of the first capacitor; the control terminal of the initialization module is electrically connected to the first control signal line, the first end of the initialization module is electrically connected to the second electrode of the first capacitor, and the second end of the initialization module is electrically connected to a first negative potential signal line; wherein the voltage value provided by the second control signal line is greater than the voltage value provided by the first negative potential signal line.

[0007] Based on the same inventive concept, this invention discloses a display panel, comprising: a display area and a non-display area; the display area includes multiple pixel units and multiple gate lines, the gate lines being electrically connected to the pixel units; the non-display area includes a boost circuit, the boost circuit including multiple boost units, each boost unit being electrically connected to at least one gate line; each boost unit includes a first transistor, a second transistor, a third transistor, and a first capacitor, all electrically connected; the gate of the first transistor is electrically connected to a first control signal line, the source of the first transistor is electrically connected to its gate, and the drain of the first transistor is electrically connected to the gate line, the gate of the second transistor, and the first electrode of the first capacitor, respectively; the source of the second transistor is electrically connected to a second control signal line, and the drain of the second transistor is electrically connected to the second electrode of the first capacitor; the gate of the third transistor is electrically connected to the first control signal line, the source of the third transistor is electrically connected to the drain of the second transistor, and the drain of the third transistor is electrically connected to a first negative potential signal line; wherein, the voltage value provided by the second control signal line is greater than the voltage value provided by the first negative potential signal line.

[0008] Based on the same inventive concept, the present invention also discloses a driving method for a display panel, which is applied to the aforementioned display panel. The driving method includes a charging stage and a bootstrap stage. In the charging stage, a first control signal value provided by a first control signal line controls the first and second terminals of the charging module to be turned on, and the first control signal value provided by the first control signal line controls the first and second terminals of the initialization module to be turned on. The first control signal value is transmitted to the gate line, the control terminal of the first module, and the first electrode of the first capacitor, respectively. At this time, the second electrode of the first capacitor is the first negative potential signal value transmitted by the first negative potential signal line. In the bootstrap stage, the first control signal value controls the first and second terminals of the first module to be turned on.

[0009] Based on the same inventive concept, the present invention also discloses a display device, which includes the above-described display panel.

[0010] Compared with the prior art, the display panel, driving method, and display device provided by the present invention achieve at least the following beneficial effects:

[0011] The display panel provided by this invention includes a display area and a non-display area. The display area includes multiple pixel units and multiple gate lines, and the non-display area includes a boost circuit. Each boost unit in the boost circuit is used to increase the voltage transmitted on the gate lines. When the boost unit is working, the potential signal on the second terminal of the first capacitor is a smaller negative first negative potential signal value provided by the first negative potential signal line, and the potential signal on the first terminal of the first capacitor is a first control signal value provided by the first control signal line. After the first control signal value provided by the first control signal line further controls the conduction between the first and second terminals of the first module, the second control signal value provided by the second control signal line can be transmitted to the second terminal of the first capacitor electrically connected to the second terminal of the first module. This makes the potential signal on the second terminal of the first capacitor larger than the second control signal value provided by the second control signal line. Since the second control signal value is greater than the first negative potential signal value, and the first capacitor itself has a bootstrap coupling effect, when the potential signal on the second terminal of the first capacitor rises from a smaller first negative potential signal value to a larger second control signal value, the second terminal of the first capacitor is charged again. The potential signal on the first terminal of the first capacitor is also further raised due to the bootstrap effect. This allows the potential signal on the first terminal of the first capacitor to be transmitted to the gate line after the first control signal value is raised. This enables the input of a low-voltage first control signal value to the boost unit, the input of a low-voltage second control signal value to the boost unit, and the output of a high voltage from the boost unit to the gate line. Even if the voltage value written by the data line is very high, the boost circuit can ensure that the voltage value transmitted to the pixel unit on the gate line is also relatively high, ensuring the normal transmission of the drive signal of the pixel unit. This invention can achieve low voltage input and high voltage output by setting up a boost circuit, thereby reducing the power consumption of the panel drive and ensuring that the drive signal drives the panel normally.

[0012] Of course, any product implementing this invention need not necessarily achieve all of the technical effects described above at the same time.

[0013] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0015] Figure 1 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present invention;

[0016] Figure 2 yes Figure 1 A schematic diagram of an electrical connection structure between a boost unit and a pixel unit;

[0017] Figure 3 yes Figure 2 A schematic diagram of an electrical connection structure;

[0018] Figure 4 yes Figure 3 The timing diagram of the input signals when the circuit structure is working;

[0019] Figure 5 yes Figure 2 A schematic diagram of another electrical connection structure;

[0020] Figure 6 yes Figure 5 The timing diagram of the input signals when the circuit structure is working;

[0021] Figure 7 yes Figure 1 A schematic diagram of another electrical connection structure between the boost unit and the pixel unit;

[0022] Figure 8 yes Figure 7 A schematic diagram of an electrical connection structure;

[0023] Figure 9 yes Figure 8 A schematic diagram of a signal transmission scenario in a circuit structure;

[0024] Figure 10 yes Figure 8 A schematic diagram of another signal transmission scenario in the circuit structure;

[0025] Figure 11 yes Figure 8 A schematic diagram of another signal transmission scenario in the circuit structure;

[0026] Figure 12 yes Figure 7 A schematic diagram of another electrical connection structure;

[0027] Figure 13 yes Figure 1 A schematic diagram of another electrical connection structure between the boost unit and the pixel unit;

[0028] Figure 14 yes Figure 13 A schematic diagram of an electrical connection structure;

[0029] Figure 15 yes Figure 14 The timing diagram of the input signals when the circuit structure is working;

[0030] Figure 16 yes Figure 13 A schematic diagram of another electrical connection structure;

[0031] Figure 17 yes Figure 16 The timing diagram of the input signals when the circuit structure is working;

[0032] Figure 18 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of the present invention;

[0033] Figure 19 yes Figure 18 A schematic diagram of an electrical connection structure between the first driving circuit, the boost unit, and the pixel unit;

[0034] Figure 20 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of the present invention;

[0035] Figure 21 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of the present invention;

[0036] Figure 22 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of the present invention;

[0037] Figure 23 yes Figure 14 A simulation diagram of the driving signals for the circuit structure;

[0038] Figure 24 This is a schematic diagram of the planar structure of the display device provided in an embodiment of the present invention. Detailed Implementation

[0039] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0040] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0041] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0042] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0043] Various modifications and variations can be made to this invention without departing from its spirit or scope, as will be apparent to those skilled in the art. Therefore, this invention is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this invention can be combined with each other without contradiction.

[0044] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0045] Please refer to the reference. Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present invention. Figure 2 yes Figure 1 A schematic diagram of an electrical connection structure between a boost unit and a pixel unit. The display panel 000 provided in this embodiment includes: a display area AA and a non-display area NA. The display area AA includes multiple pixel units 10 and multiple gate lines G. The gate lines G are electrically connected to the pixel units 10.

[0046] The non-display area NA includes a boost circuit 20, which includes a plurality of boost units 200, and each boost unit 200 is electrically connected to at least one gate line G.

[0047] The boost unit 200 includes a charging module 201, a bootstrap module, and an initialization module 203 that are electrically connected. The bootstrap module includes at least a first module 202 and a first capacitor C1.

[0048] The control terminal 201A of the charging module 201 is electrically connected to the first control signal line L1. The first terminal 201B of the charging module 201 is electrically connected to the control terminal 201A of the charging module 201. The second terminal 201C of the charging module 201 is electrically connected to the gate line G, the control terminal 202A of the first module 202, and the first electrode C11 of the first capacitor C1, respectively.

[0049] The first terminal 202B of the first module 202 is electrically connected to the second control signal line L2, and the second terminal 202C of the first module 202 is electrically connected to the second terminal C12 of the first capacitor C1.

[0050] The control terminal 203A of the initialization module 203 is electrically connected to the first control signal line L1, the first terminal 203B of the initialization module 203 is electrically connected to the second terminal C12 of the first capacitor C1, and the second terminal 203C of the initialization module 203 is electrically connected to the first negative potential signal line L0.

[0051] The voltage value provided by the second control signal line L2 is greater than the voltage value provided by the first negative potential signal line L0.

[0052] Specifically, the display panel 000 provided in this embodiment includes a display area AA and a non-display area NA. The display area AA includes multiple pixel units 10 and multiple gate lines G. The gate lines G are electrically connected to the pixel units 10. Optionally, the display area AA of the display panel 000 may also include multiple data lines S that are insulated from the gate lines G. The pixel unit 10 may generally include a switching transistor. The voltage transmitted on the gate line G can control the switching transistors in the corresponding row of pixel units 10 to turn on sequentially. At the same time, the data lines S provide data signals to the corresponding row of pixel units 10 to form the grayscale voltage required for each grayscale level of the displayed image in each pixel unit 10, thereby realizing the display of a frame of image.

[0053] Currently, in some display devices, such as electronic paper displays, the gate line driving can be achieved through an integrated driver circuit (IC, not shown in the figure) subsequently bonded to the display panel 000. That is, the gate line voltage can generally be directly provided by the IC. For example, if the IC provides an upper voltage of 25V and a lower voltage of -25V, then the gate line voltage is also 25V and -25V. Due to the influence of the transistor's voltage drop and threshold voltage, the on-state voltage of the switching transistor gate in pixel unit 10 always needs to be higher than the positive voltage of the data line. For example, for an N-type switching transistor, the gate voltage of the switching transistor needs to be greater than the voltage provided by the data line at its source / drain to turn it on. The off-state voltage always needs to be lower than the negative voltage of the data line. For example, for an N-type switching transistor, the gate voltage of the switching transistor needs to be less than the voltage provided by the data line at its source / drain to turn it off. Therefore, when the data line is positive, the gate voltage of the switching transistor in pixel unit 10 needs to be higher than the positive voltage of the data line to be in the on state; when the data line is negative, the gate voltage of the transistor in the pixel array needs to be lower than the negative voltage of the data line to be in the off state. Therefore, as customers demand higher voltage for writing data lines (S), the voltage provided on the gate line has to be increased and decreased further. As a result, the voltage difference that the IC needs to provide becomes larger and larger, which makes the driving capability required by the IC higher and the power consumption higher and higher.

[0054] To address the aforementioned issues, this embodiment includes a boost circuit 20 in the non-display area NA. The placement of the boost circuit 20 in the non-display area NA prevents it from affecting the display image in the display area AA. The boost circuit 20 includes multiple boost units 200, each boost unit 200 being electrically connected to at least one gate line G. Each boost unit 200 in the boost circuit 20 is used to increase the voltage transmitted on the gate line G, thus enabling low-voltage input to the boost unit 200 and high-voltage output from the boost unit 200 to the gate line G.

[0055] Specifically, the boost unit 200 may include at least a charging module 201, a bootstrap module, and an initialization module 203 that are electrically connected. The bootstrap module may include at least a first module 202 and a first capacitor C1. The control terminal 203A of the initialization module 203 is electrically connected to the first control signal line L1. The first terminal 203B of the initialization module 203 is electrically connected to the second terminal C12 of the first capacitor C1. The second terminal 203C of the initialization module 203 is electrically connected to the first negative potential signal line L0. Under the first control signal value provided by the first control signal line L1, the conduction between the first terminal 203B and the second terminal 203C of the initialization module 203 can be controlled. When the first terminal 203B and the second terminal 203C of the initialization module 203 are connected under the control of the first control signal value provided by the first control signal line L1, the first negative potential signal value VGL provided by the first negative potential signal line L0 can be transmitted to the second terminal C12 of the first capacitor C1. This ensures that when the boost unit 200 of the boost circuit 20 is in the charging state, the potential signal on the second terminal C12 of the first capacitor C1 is equal to the voltage value provided by the first negative potential signal line L0, which is the first negative potential signal value VGL. Optionally, the first negative potential signal value VGL can be negative.

[0056] The control terminal 201A of the charging module 201 is electrically connected to the first control signal line L1. The first terminal 201B of the charging module 201 is electrically connected to the control terminal 201A of the charging module 201. The second terminal 201C of the charging module 201 is electrically connected to the gate line G. Under the first control signal value provided by the first control signal line L1, the conduction between the first terminal 201B and the second terminal 201C of the charging module 201 can be controlled. When the first terminal 201B and the second terminal 201C of the charging module 201 are connected under the control of the first control signal value provided by the first control signal line L1, the first control signal value provided by the first control signal line L1 can be transmitted to the gate line G.

[0057] The second terminal 201C of the charging module 201 is also electrically connected to the first terminal C11 of the first capacitor C1. Under the first control signal value provided by the first control signal line L1, the conduction between the first terminal 201B and the second terminal 201C of the charging module 201 can be controlled. When the first terminal 201B and the second terminal 201C of the charging module 201 are connected under the control of the first control signal value provided by the first control signal line L1, the first control signal value provided by the first control signal line L1 can be transmitted to the first terminal C11 of the first capacitor C1, so that the potential signal on the first terminal C11 of the first capacitor C1 is the first control signal value provided by the first control signal line L1. Optionally, in this embodiment, the magnitude of the first control signal value is not limited. When the transistor included in the charging module 201 is an N-type transistor, the first control signal value can be positive; when the transistor included in the charging module 201 is a P-type transistor, the first control signal value can be negative. In specific implementation, the setting can be selected according to the actual situation.

[0058] The second terminal 201C of the charging module 201 is also electrically connected to the control terminal 202A of the first module 202. Under the first control signal value provided by the first control signal line L1, the conduction between the first terminal 201B and the second terminal 201C of the charging module 201 can be controlled. When the first terminal 201B and the second terminal 201C of the charging module 201 are connected under the control of the first control signal value provided by the first control signal line L1, the first control signal value provided by the first control signal line L1 can be transmitted to the control terminal 202A of the first module 202. That is, the first control signal value provided by the first control signal line L1 can control the conduction between the first terminal 202B and the second terminal 202C of the first module 202. The first terminal 202B of the first module 202 is electrically connected to the second control signal line L2, and the second terminal 201C of the first module 202... C is electrically connected to the second terminal C12 of the first capacitor C1; therefore, under the control of the first control signal value provided by the first control signal line L1, the first terminal 201B and the second terminal 201C of the charging module 201 are connected, and the first control signal value provided by the first control signal line L1 can be transmitted to the control terminal 202A of the first module 202. The first control signal value provided by the first control signal line L1 can further control the connection between the first terminal 202B and the second terminal 202C of the first module 202, and then the second control signal value provided by the second control signal line L2 electrically connected to the first terminal 202B of the first module 202 can be transmitted to the second terminal C12 of the first capacitor C1 electrically connected to the second terminal 202C of the first module 202, so that the potential signal on the second terminal C12 of the first capacitor C1 is the second control signal value provided by the second control signal line L2. Optionally, in this embodiment, the magnitude of the second control signal value provided by the second control signal line L2 is not limited. When the transistor included in the first module 202 is an N-type transistor, the second control signal value can be positive. When the transistor included in the first module 202 is a P-type transistor, the second control signal value can be negative. In specific implementation, the setting can be selected according to the actual situation.

[0059] In this embodiment, the voltage value provided by the second control signal line L2 is greater than the voltage value provided by the first negative potential signal line L0. That is, regardless of whether the voltage value of the second control signal provided by the second control signal line L2 is positive or negative, it must be greater than the negative voltage value provided by the first negative potential signal line L0.

[0060] Optional, such as Figure 1 and Figure 2As shown, when the display panel 000 is driven, the boost circuit 20 works, the first control signal line L1 provides the first control signal value, and under the control of the first control signal value, the first terminal 201B and the second terminal 201C of the charging module 201 are turned on, the first terminal 203B and the second terminal 203C of the initialization module 203 are turned on, the first control signal value is transmitted to the gate line G, the control terminal 202A of the first module 202, and the first terminal C11 of the first capacitor C1 respectively, and the voltage value provided by the first negative potential signal line L0 is transmitted to the second terminal C12 of the first capacitor C1.

[0061] Under the control of the first control signal value, the first terminal 202B and the second terminal 202C of the first module 202 are turned on.

[0062] The second control signal line L2 provides the second control signal value, which is transmitted to the second terminal C12 of the first capacitor C1. The voltage of the second terminal C12 of the first capacitor C1 is raised, and the voltage of the first terminal C11 of the first capacitor C1 is raised by coupling the second terminal C12 of the first capacitor C1.

[0063] Therefore, when the boost unit 200 of the boost circuit 20 is in the charging state, the potential signal on the second terminal C12 of the first capacitor C1 is a smaller first negative potential signal value VGL provided by the first negative potential signal line L0, and the potential signal on the first terminal C11 of the first capacitor C1 is the first control signal value provided by the first control signal line L1. After the first control signal value provided by the first control signal line L1 further controls the conduction between the first terminal 202B and the second terminal 202C of the first module 202, the second control signal value provided by the second control signal line L2 can be transmitted to the second terminal C12 of the first capacitor C1 electrically connected to the second terminal 202C of the first module 202. This makes the potential signal on the second terminal C12 of the first capacitor C1 larger than the second control signal value provided by the second control signal line L2. Since the voltage value provided by the second control signal line L2 is greater than the voltage value provided by the first negative potential signal line L0, that is, the second control signal value is greater than the first negative potential signal value VGL, and the first capacitor C1 itself has a bootstrap coupling effect, when the potential signal on the second terminal C12 of the first capacitor C1 rises from the smaller first negative potential signal value VGL to the larger second control signal value, the second terminal C12 of the first capacitor C1 is recharged, and the potential signal on the first terminal C11 of the first capacitor C1 is also further raised due to the bootstrap effect, thereby making the first capacitor C12 more capable of generating a higher potential signal. The potential signal on the first electrode C11 of 1 is boosted from the first control signal value and transmitted to the gate line G. This boost circuit 20 allows for the input of a low-voltage first control signal value to the boost unit 200, a low-voltage second control signal value to the boost unit 200, and a high-voltage output from the boost unit 200 to the gate line G. Even if the panel display requires a high voltage for writing data to the S line (i.e., the voltage value written to the S line is very high), the boost circuit 20 ensures that the voltage value transmitted from the gate line G to the pixel unit 10 is also relatively high. For example, when the switching transistor in the pixel unit 10 is an N-type switching transistor, the voltage provided by the gate line G to the gate of the switching transistor in the pixel unit 10 is greater than the voltage value written to the data line (the voltage provided by the gate line G to the gate of the switching transistor in the pixel unit 10 is greater than the voltage value written to the source / drain of the switching transistor in the pixel unit 10), ensuring the normal opening and conduction of the switching transistor in the pixel unit 10 and the normal transmission of the driving signal of the pixel unit 10. This embodiment can achieve low voltage input and high voltage output by setting the boost circuit 20, thereby reducing the driving power consumption of the panel, ensuring the normal driving of the panel by the driving signal, and ensuring display quality.

[0064] Optionally, in this embodiment, the signal lines that are electrically connected to the boost circuit 20, such as the first control signal line L1, the second control signal line L2, and the first negative potential signal line L0, can all be set within the non-display area NA of the display panel 000, thereby avoiding affecting the display quality of the display area AA.

[0065] It is understood that the diagram in this embodiment is only an example of the structure of the display panel 000. In specific implementation, the structure of the display panel 000 includes, but is not limited to, this, and may also include other structures that can realize the display function. This embodiment will not elaborate on these details.

[0066] It should be noted that this embodiment does not limit the specific structure of the pixel unit 10. The design structure of the pixel unit 10 can be understood by referring to the structure of the display panel in related technologies. It is only necessary to satisfy that the pixel unit 10 can be driven to open by the driving voltage provided by the gate line G, so as to realize the structure of the data line S providing the data voltage to the pixel unit 10 and realize image display.

[0067] Optionally, in this embodiment, the signal lines that are electrically connected to the boost circuit 20, such as the first control signal line L1, the second control signal line L2, and the first negative potential signal line L0, can all be set within the non-display area NA of the display panel 000, thereby avoiding affecting the display quality of the display area AA.

[0068] In some alternative embodiments, please refer to the references. Figure 1 , Figure 2 and Figure 3 , Figure 3 yes Figure 2 A schematic diagram of an electrical connection structure is shown. In this embodiment, the charging module 201 includes a first transistor T1, the first module 202 includes a second transistor T2, and the initialization module 203 includes a third transistor T3.

[0069] The gate of the first transistor T1 is electrically connected to the first control signal line L1, the source of the first transistor T1 is electrically connected to the gate of the first transistor T1, and the drain of the first transistor T1 is electrically connected to the gate line G, the gate of the second transistor T2, and the first terminal C11 of the first capacitor C1.

[0070] The source of the second transistor T2 is electrically connected to the second control signal line L2, and the drain of the second transistor T2 is electrically connected to the second terminal C12 of the first capacitor C1.

[0071] The gate of the third transistor T3 is electrically connected to the first control signal line L1, the source of the third transistor T3 is electrically connected to the drain of the second transistor T2, and the drain of the third transistor T3 is electrically connected to the first negative potential signal line L0.

[0072] This embodiment explains that a boost circuit 20 is set in the non-display area NA of the display panel 000. This circuit is used to input a low-voltage first control signal value to each boost unit 200 of the boost circuit 20, input a low-voltage second control signal value to each boost unit 200 of the boost circuit 20, and output a high voltage from each boost unit 200 of the boost circuit 20 to the gate line G, thereby saving the driving power consumption of the panel. The circuit structure of each boost unit 200 of the boost circuit 20 can include a structure comprising multiple transistors. Specifically, the charging module 201 includes a first transistor T1, the first module 202 includes a second transistor T2, and the initialization module 203 includes a third transistor T3. Optionally, this embodiment uses N-type transistors as an example, where the gate of an N-type transistor is connected between its source and drain under high voltage control. In some other alternative embodiments, the first transistor T1, the second transistor T2, and the third transistor T3 can all be P-type transistors. In this case, the gate of the P-type transistor is connected between its source and drain under low voltage control. This embodiment does not limit this. The gate of the third transistor T3 of the initialization module 203 (i.e., the control terminal 203A of the initialization module 203) is electrically connected to the first control signal line L1, the source of the third transistor T3 (i.e., the first terminal 203B of the initialization module 203) is electrically connected to the second terminal C12 of the first capacitor C1, and the drain of the third transistor T3 (i.e., the second terminal 203C of the initialization module 203) is electrically connected to the first negative potential signal line L0. The gate of the first transistor T1 in the charging module 201 (i.e., the control terminal 201A of the charging module 201) is electrically connected to the first control signal line L1. The source of the first transistor T1 (i.e., the first terminal 201B of the charging module 201) is electrically connected to the gate of the first transistor T1. The drain of the first transistor T1 (i.e., the second terminal 201C of the charging module 201) is electrically connected to the gate line G, the gate of the second transistor T2 (i.e., the control terminal 202A of the first module 202), and the first terminal C11 of the first capacitor C1. The source of the second transistor T2 in the first module 202 (i.e., the first terminal 202B of the first module 202) is electrically connected to the second control signal line L2. The drain of the second transistor T2 (i.e., the second terminal 202C of the first module 202) is electrically connected to the second terminal C12 of the first capacitor C1. Figure 3 and Figure 4 As shown, Figure 4 yes Figure 3 The timing diagram of the input signal during the operation of the circuit structure in the circuit, taking the first transistor T1, the second transistor T2, and the third transistor T3 as N-type transistors as an example, shows that the operation process of each boost unit 200 of the boost circuit 20 can be as follows:

[0073] During charging phase J1: The first control signal value VL1 provided by the first control signal line L1 is a high-level signal, and the second control signal value VL2 provided by the second control signal line L2 is a low-level signal. The first transistor T1 and the third transistor T3 are turned on under the control of the high-level first control signal value VL1. The high-level first control signal value VL1 is gradually transmitted to the gate line G, at which point the signal on the gate line G gradually rises to the high-level first control signal value VL1. The signal on the first terminal C11 of the first capacitor C1 also gradually rises to the high-level first control signal value VL1. The low-level first negative potential signal value VGL provided by the first negative potential signal line L0 is transmitted to the second terminal C12 of the first capacitor C1, and the signal on the second terminal C12 of the first capacitor C1 is the low-level first negative potential signal value VGL. Simultaneously, the high-level first control signal value VL1 is transmitted through the first transistor T1 to the gate of the second transistor T2, causing the gate voltage of the second transistor T2 to gradually increase, and the second transistor T2 gradually begins to conduct.

[0074] Bootstrapping Phase J2: The first control signal value VL1 provided by the first control signal line L1 is a low-level signal, and the second control signal value VL2 provided by the second control signal line L2 is a high-level signal. The first transistor T1 and the third transistor T3 are cut off under the control of the low-level first control signal value VL1, while the gate of the second transistor T2 is already at the high-level signal provided by the charging phase J1. Therefore, the second transistor T2 remains on, and the high-level second control signal value VL2 is transmitted to the second terminal C12 of the first capacitor C1 through the second transistor T2. The voltage at the second terminal C12 of the first capacitor C1 rises from the low-level first negative potential signal value VGL to the high-level second control signal value VL2. The first terminal C11 of the first capacitor C1 is coupled and raised to a higher voltage. Since the first terminal C11 of the first capacitor C1 is electrically connected to the gate line G, the potential transmitted on the gate line G is also raised to a higher voltage value. This allows for the input of a low-voltage first control signal value VL1 to each boost unit 200 of the boost circuit 20, and a low-voltage second control signal value VL2 to each boost unit 200 of the boost circuit 20. Meanwhile, a high voltage is output from each boost unit 200 of the boost circuit 20 to the gate line G. This saves power consumption in the panel's drive. Even if the voltage value written by the data line S during panel display is high, the boost circuit 20 can ensure that the voltage value transmitted to the pixel unit 10 via the gate line G is also relatively high. For example, if the switching transistor in the pixel unit 10 is also an N-type switching transistor, the voltage provided by the gate line G to the gate of the switching transistor in the pixel unit 10 can be high enough and exceed the high voltage value written by the data line. This ensures that the switching transistor in the pixel unit 10 can be turned on normally, the drive signal of the pixel unit 10 is transmitted normally, and the drive signal drives the panel normally, ensuring the display quality during display.

[0075] It is understood that in this embodiment Figure 3 and Figure 4 This example illustrates the situation using the case where the first transistor T1, the second transistor T2, and the third transistor T3 are all N-type transistors, and the switching transistor included in the pixel unit 10 is also an N-type transistor. The gates of the first transistor T1, the second transistor T2, and the third transistor T3 are turned on under a high-potential first control signal value VL1. The high-potential second control signal value VL2 is greater than the low-potential first negative potential signal value VGL, achieving a bootstrap effect. This ensures that the voltage provided by the gate line G in the pixel unit 10 to the gate of the switching transistor in the pixel unit 10 is greater than the voltage value written to the source / drain of the switching transistor in the pixel unit 10 via the data line, thus satisfying the requirement for normal high-potential writing to the pixel unit 10. When the first transistor T1, the second transistor T2, and the third transistor T3 are all P-type transistors, and the switching transistor included in the pixel unit 10 is also a P-type transistor, as... Figure 5 and Figure 6 As shown, Figure 5 yes Figure 2 Another electrical connection structure diagram, Figure 6 yes Figure 5 The timing diagram of the input signal when the circuit structure is working is shown. The gates of the first transistor T1, the second transistor T2, and the third transistor T3 are turned on under the low-potential first control signal value VL1. At this time, although the second control signal value VL2 is a low-potential signal, the low-potential second control signal value VL2 still needs to be greater than the low-potential first negative potential signal value VGL in order to achieve the bootstrap effect. This makes the voltage provided by the gate line G in the pixel unit 10 to the gate of the switching transistor in the pixel unit 10 greater than the voltage value written to the source / drain of the switching transistor in the pixel unit 10, so as to satisfy the normal writing of the high potential on the data line to the pixel unit 10.

[0076] It is understood that in the above embodiments, low potential and low level can be understood as the voltage value of the signal being negative, and high potential and high level can be understood as the voltage value of the signal being positive. Subsequent embodiments will not be further explained.

[0077] In some alternative embodiments, please refer to the references. Figure 1 and Figure 7 , Figure 7 yes Figure 1 A schematic diagram of another electrical connection structure between the boost unit and the pixel unit; the display panel 000 also includes multiple data lines S.

[0078] The boost unit 200 also includes a gating module 204. The control terminal 204A of the gating module 204 is electrically connected to the data line S, the first terminal 204B of the gating module 204 is electrically connected to the second control signal line L2, and the second terminal 204C of the gating module 204 is electrically connected to the first terminal 202B of the first module 202.

[0079] This embodiment explains that in the boost circuit 20 set in the non-display area NA of the display panel 000, each boost unit 200 also includes a gating module 204. Whether the first terminal 204B and the second terminal 204C of the gating module 204 are turned on or off can be controlled by the potential signal provided on the data line S in the display panel 000. Specifically, the control terminal 204A of the gating module 204 is electrically connected to the data line S, the first terminal 204B of the gating module 204 is electrically connected to the second control signal line L2, and the second terminal 204C of the gating module 204 is electrically connected to the first terminal 202B of the first module 202. The potential signal provided on the data line S controls whether the second control signal value VL2 provided by the second control signal line L2 is transmitted to the first terminal 202B of the first module 202. When the display panel 000 is driven to display, the potential signal transmitted on the data line S includes both positive and negative voltage signals. When the potential signal transmitted on the data line S is a positive voltage signal, the voltage transmitted on the gate line G (i.e., the gate-on voltage of the switching transistor in the pixel unit 10) must be higher than the positive voltage transmitted on the data line S (i.e., the source / drain voltage of the switching transistor in the pixel unit 10) in order to complete the writing of the data voltage signal to the pixel unit 10. For example, when the pixel unit 10 includes a switching transistor and a pixel electrode, the gate of the switching transistor is connected to the gate line G, the source of the switching transistor is connected to the data line S, and the drain of the switching transistor is connected to the pixel electrode. In this case, the voltage transmitted on the gate line G must be higher than the positive voltage transmitted on the data line S in order to complete the charging of the pixel electrode in the pixel unit 10 by the switching transistor in the pixel unit 10. However, when the potential signal transmitted on data line S is a negative voltage signal, it is equivalent to a relatively low source / drain voltage of the switching transistor in pixel unit 10. In this case, the voltage transmitted on the gate line G of the switching transistor does not need to be as high as when the potential signal transmitted on data line S is a positive voltage signal. It only needs to satisfy the requirement that the gate-on voltage of the switching transistor in pixel unit 10, i.e., the voltage transmitted on gate line G, is greater than the negative voltage signal value transmitted on data line S, to complete the charging of the pixel electrode in pixel unit 10 by the switching transistor. For example, if the positive voltage signal transmitted on data line S is +5V, the voltage transmitted on gate line G needs to be 25V, with a voltage difference of 20V, to ensure that the switching transistor in pixel unit 10 is turned on, thus completing the charging of the pixel electrode in pixel unit 10 by the switching transistor. If the negative voltage signal transmitted on the data line S is -5V, and the voltage difference between the two is 20V, the switching transistor in the pixel unit 10 can be turned on. Therefore, the voltage transmitted on the gate line G only needs to be 15V. At this time, there is no need to raise the potential of the gate line G through the bootstrap effect of the first capacitor C1.In this embodiment, the control terminal 204A of the gating module 204 is electrically connected to the data line S, the first terminal 204B of the gating module 204 is electrically connected to the second control signal line L2, and the second terminal 204C of the gating module 204 is electrically connected to the first terminal 202B of the first module 202. The voltage transmitted on the data line S controls whether the second control signal value provided by the second control signal line L2 is transmitted to the first terminal 202B of the first module 202. When a negative voltage is transmitted on the data line S, the first terminal 204B and the second terminal 204C of the gating module 204 are not turned on. That is, the boost unit 200 does not need to raise the potential of the gate line G through the bootstrap effect of the first capacitor C1 to ensure that the switching transistor in the pixel unit 10 can be turned on normally and the driving signal of the pixel unit 10 can be transmitted normally, thereby further saving the driving power consumption of the panel.

[0080] Optional, such as Figure 7 and Figure 8 As shown, Figure 8 yes Figure 7 A schematic diagram of an electrical connection structure is shown. In this embodiment, the gating module 204 includes a fourth transistor T4; the gate of the fourth transistor T4 is electrically connected to the data line S, the source of the fourth transistor T4 is electrically connected to the second control signal line L2, and the drain of the fourth transistor T4 is electrically connected to the first terminal 202B of the first module 202.

[0081] This embodiment explains that a boost circuit 20 is set in the non-display area NA of the display panel 000. This circuit is used to input a low-voltage first control signal value to each boost unit 200 of the boost circuit 20, input a low-voltage second control signal value to each boost unit 200 of the boost circuit 20, and output a high voltage from each boost unit 200 of the boost circuit 20 to the gate line G, thereby saving the panel's driving power consumption. The circuit structure of each boost unit 200 of the boost circuit 20 can include multiple transistors. Specifically, the charging module 201 includes a first transistor T1, the first module 202 includes a second transistor T2, the initialization module 203 includes a third transistor T3, and the selection module 204 includes a fourth transistor T4. Optionally, this embodiment uses N-type transistors as an example, where the gate of an N-type transistor is connected between its source and drain under high voltage control. In some other alternative embodiments, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor can all be P-type transistors. In this case, the gate of the P-type transistor is connected between its source and drain under low voltage control. This embodiment does not limit this. The gate of the fourth transistor T4 of the gating module 204 (i.e., the control terminal 204A of the gating module 204) is electrically connected to the data line S, the source of the fourth transistor T4 (i.e., the first terminal 204B of the gating module 204) is electrically connected to the second control signal line L2, and the drain of the fourth transistor T4 (i.e., the second terminal 204C of the gating module 204) is electrically connected to the first terminal 202B of the first module 202. Figure 4 and Figure 8 As shown ( Figure 8 The timing diagram of the input signals during the operation of the schematic circuit structure can be referenced. Figure 4 As shown, taking the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor as N-type transistors as an example, the operation process of each boost unit 200 of the boost circuit 20 can be as follows:

[0082] During the charging phase J1: The first control signal value VL1 provided by the first control signal line L1 is a high-potential signal (e.g., +5V), and the second control signal value VL2 provided by the second control signal line L2 is a low-potential signal. The first transistor T1 and the third transistor T3 are turned on under the control of the high-potential first control signal value VL1. The high-potential first control signal value VL1 (e.g., +5V) is gradually transmitted to the gate line G. At this time, the signal on the gate line G gradually rises to the high-potential first control signal value VL1 (e.g., +5V), and the signal on the first terminal C11 of the first capacitor C1 also gradually rises to the high-potential first control signal value VL1 (e.g., +5V). The low-potential first negative potential signal value VGL (e.g., -25V) provided by the first negative potential signal line L0 is transmitted to the second terminal C12 of the first capacitor C1. The signal on the second terminal C12 of the first capacitor C1 is the low-potential first negative potential signal value VGL. At the same time, the high-potential first control signal value VL1 is transmitted to the gate of the second transistor T2 through the first transistor T1, causing the gate voltage of the second transistor T2 to gradually increase, and the second transistor T2 gradually begins to conduct.

[0083] Bootstrapping phase J2:

[0084] If the voltage signal transmitted on data line S is a negative voltage signal (e.g., -15V), the fourth transistor T4 is turned off; the first control signal value VL1 provided by the first control signal line L1 is a low-level signal, and the second control signal value VL2 provided by the second control signal line L2 is a high-level signal. The first transistor T1 and the third transistor T3 are turned off under the control of the low-level first control signal value VL1, while the gate of the second transistor T2 is already at the high-level signal provided by the charging stage J1 (e.g., +5V). Therefore, the second transistor T2 continues to be turned on. However, since the fourth transistor T4 is turned off, the high-level second control signal value VL2 cannot be transmitted to the second terminal C12 of the first capacitor C1 through the second transistor T2. The voltage of the second terminal C12 of the first capacitor C1 is still at the charging stage J12. The first negative potential signal line L0 provides a low-potential first negative potential signal value VGL (e.g., -25V), while the first terminal C11 of the first capacitor C1 is still the high-potential first control signal value VL1 (e.g., +5V) provided by the first control signal line L1. That is, the first capacitor C1 does not need to bootstrap, and does not need to raise the potential of the first terminal C11 of the first capacitor C1 through coupling. At this time, the gate line G still transmits the high-potential first control signal value VL1 (e.g., +5V) provided by the first control signal line L1 of the charging stage J1. Since the high-potential first control signal value VL1 (e.g., +5V) is necessarily greater than the negative voltage signal (e.g., -15V) transmitted on the data line S, it is not necessary to raise the potential of the gate line G to ensure that the switching transistor in the pixel unit 10 can be turned on normally.

[0085] If the voltage signal transmitted on data line S is a positive voltage signal (e.g., +15V), the fourth transistor T4 is turned on. The first control signal value VL1 provided by the first control signal line L1 is a low-level signal, and the second control signal value VL2 provided by the second control signal line L2 is a high-level signal (e.g., +5V). The first transistor T1 and the third transistor T3 are turned off under the control of the low-level first control signal value VL1, while the gate of the second transistor T2 is already at the high-level signal (e.g., +5V) provided by the charging stage J1. Therefore, the second transistor T2 continues to be turned on. Since the fourth transistor T4 is turned on, the high-level second control signal value VL2 (e.g., +5V) is transmitted through the second transistor T2 to the second terminal C12 of the first capacitor C1. The voltage of C12 is raised from a low-potential first negative potential signal value VGL (e.g., -25V) to a high-potential second control signal value VL2 (e.g., +5V). The potential of the first terminal C11 of the first capacitor C1 is coupled up to a higher voltage (e.g., from +5V in the charging stage J1 to +35V). The first terminal C11 of the first capacitor C1 is electrically connected to the gate line G. Therefore, the potential transmitted on the gate line G is also raised to a higher voltage value (e.g., +35V). At this time, the potential transmitted on the gate line G, which is raised to a higher voltage value (e.g., +35V), is greater than the positive voltage signal transmitted on the data line S (e.g., +15V). Therefore, by raising the potential of the gate line G through the bootstrap stage J2, it can be ensured that the switching transistor in the pixel unit 10 can be turned on normally.

[0086] In this embodiment, the setting of the fourth transistor T4 in the selection module 204 enables the input of a low-voltage first control signal value VL1 to each boost unit 200 of the boost circuit 20, the input of a low-voltage second control signal value VL2 to each boost unit 200 of the boost circuit 20, and the output of a high voltage from each boost unit 200 of the boost circuit 20 to the gate line G. This saves the driving power consumption of the panel, and even if the positive voltage value written by the data line S during panel display is very high, the boost circuit 20 can ensure that the voltage value transmitted to the pixel unit 10 on the gate line G is also higher than that of the pixel unit 10. For example, when the switching transistor in pixel unit 10 is also an N-type switching transistor, the voltage provided by the gate line G to the gate of the switching transistor in pixel unit 10 can be high enough and meet the requirement of being higher than the high voltage value written by the data line. This ensures that the switching transistor in pixel unit 10 can be turned on and conducted normally, and the driving signal of pixel unit 10 can be transmitted normally. Through the setting of the bootstrap module in boost unit 200, low voltage input and high voltage output to gate line G can be achieved, which helps to save the driving power consumption of the panel, ensure the normal driving of the panel by the driving signal, and ensure the display quality during display. Furthermore, the fourth transistor T4 included in the gating module 204 can prevent the second control signal value provided by the second control signal line L2 from being transmitted to the first terminal 202B of the first module 202 due to the negative voltage transmitted on the data line S. That is, when a negative voltage is transmitted on the data line S, the boost unit 200 does not need to raise the potential of the gate line G through the bootstrap effect of the first capacitor C1. The voltage on the gate line G that is not raised is sufficient to ensure that the switching transistor in the pixel unit 10 can be turned on normally and the driving signal of the pixel unit 10 can be transmitted normally. At this time, the switching transistor in the pixel unit 10 does not need to be driven on by high voltage, which can reduce the life loss of the switching transistor in the pixel unit 10 and improve the life and durability of the switching transistor.

[0087] It is understood that in this embodiment Figure 8This example illustrates the situation using the case where the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all N-type transistors, and the switching transistor included in the pixel unit 10 is also an N-type transistor. The gates of the first transistor T1, the second transistor T2, and the third transistor T3 are turned on under the high-potential first control signal value VL1, and the gate of the fourth transistor T4 is turned on under the potential signal provided by the positive-potential data line S. The high-potential second control signal value VL2 is greater than the low-potential first negative potential signal value VGL, which can achieve a bootstrap effect. This makes the voltage provided by the gate line G in the pixel unit 10 to the gate of the switching transistor in the pixel unit 10 greater than the voltage value written to the source / drain of the switching transistor in the pixel unit 10 by the data line, thus satisfying the requirement of normal writing of the pixel unit 10 at a high potential on the data line. When the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all P-type transistors, and the switching transistor included in the pixel unit 10 is also a P-type transistor, the gates of the first transistor T1, the second transistor T2, and the third transistor T3 are turned on under the low-potential first control signal value VL1, and the gate of the fourth transistor T4 is turned on under the potential signal provided by the negative-potential data line S. At this time, although the second control signal value VL2 is a low-potential signal, the low-potential second control signal value VL2 still needs to be greater than the low-potential first negative-potential signal value VGL in order to achieve the bootstrap effect, so that the voltage provided by the gate line G in the pixel unit 10 to the gate of the switching transistor in the pixel unit 10 is greater than the voltage value written by the source / drain of the switching transistor in the pixel unit 10, thus satisfying the normal writing of the pixel unit 10 at a high potential on the data line.

[0088] Optionally, in this embodiment, the fourth transistor T4 in the selection module 204 determines whether the gate potential of the switching transistor in the pixel unit 10 is bootstrapping up based on the voltage signal provided by the data line S. Taking the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 as N-type transistors, and the switching transistor in the pixel unit 10 as an example, bootstrapping through the boost unit 200 can alleviate the voltage drop when the N-type transistor transmits high voltage. If a negative voltage is transmitted, bootstrapping is not required because there is no voltage drop. For N-type transistors, when the gate is high-voltage, the signal is not lost when the low voltage (i.e., the negative voltage on the data line S) is transmitted between the source and drain, so there is no voltage drop. In other words, the gate potential of the switching transistor of pixel unit 10 does not need to be bootstrap, thus avoiding voltage drop. However, when the gate of an N-type transistor is high-voltage, if the high voltage (i.e., the potential signal on the data line S is positive) is transmitted between the source and drain, the transmitted high voltage will drop. Therefore, in this embodiment, after the fourth transistor T4 of the selection module 204 is turned on by the positive potential signal on the data line S, the gate potential of the switching transistor of pixel unit 10 can be made greater than the positive potential signal transmitted on the data line S through the bootstrap unit 200. This avoids charging voltage drop and prevents the positive potential signal on the transmitted data line S from dropping, thereby ensuring the normal operation of pixel unit 10 and further improving display quality.

[0089] Optional, such as Figure 1 , Figure 4 , Figure 7 and Figure 8 As shown, in this embodiment, the voltage value transmitted on the data line S includes a first data voltage value Vdata1 and a second data voltage value Vdata2.

[0090] The first data voltage value Vdata1 is negative, and the first data voltage value Vdata1 is less than the voltage value provided by the second control signal line L2 (i.e., the second control signal value VL2 of the bootstrap stage J2);

[0091] The second data voltage value Vdata2 is positive and is greater than the voltage value provided by the second control signal line L2 (i.e., the second control signal value VL2 of the bootstrap stage J2).

[0092] This embodiment explains that when the display panel 000 is driven to display, the potential signal transmitted on the data line S includes a positive voltage signal and a negative voltage signal. That is, the voltage value transmitted on the data line S includes a negative first data voltage value Vdata1 and a positive second data voltage value Vdata2. In the bootstrap phase J2, as... Figures 9-11 As shown, Figure 9 yes Figure 8A schematic diagram of a signal transmission scenario in a circuit structure. Figure 10 yes Figure 8 A schematic diagram of another signal transmission scenario in the circuit structure. Figure 11 yes Figure 8 A schematic diagram of another signal transmission scenario in the circuit structure ( Figures 9-11 A square "×" indicates that the transistor is off; no marking indicates that the transistor is on; and a dashed line with an arrow indicates the signal transmission path. Figure 9 It means Figure 8 The circuit structure in the diagram shows the signal transmission of J1 during the charging phase. Figure 10 It means Figure 8 The circuit structure in the diagram describes the signal transmission during the bootstrap phase J2, when the voltage transmitted on the data line S is negative. Figure 10 It means Figure 8 The circuit structure in the diagram describes the signal transmission during the bootstrap phase J2, when the voltage transmitted on the data line S is positive. Figure 9 The first data voltage value Vdata1 transmitted on the data line S is negative, and this first data voltage value Vdata1 is less than the voltage value provided by the second control signal line L2 (i.e., the second control signal value VL2 of the bootstrap stage J2). That is, for the N-type fourth transistor T4, it can be ensured that the gate potential of the fourth transistor T4 (the first data voltage value Vdata1) is less than the source potential of the fourth transistor T4 (the second control signal value VL2), so that the fourth transistor T4 is in the off state during the bootstrap stage J2, so that the first capacitor C1 does not need to bootstrap, does not need to be charged again, and does not need to raise the potential of the first terminal C11 of the first capacitor C1 through coupling. At this time, the first control signal value VL1 with a high potential provided by the first control signal line L1 of the charging stage J1 is still transmitted on the gate line G. Since the first control signal value VL1 with a high potential must be greater than the negative voltage signal transmitted on the data line S, it is not necessary to raise the potential of the gate line G at this time to ensure that the switching transistor in the pixel unit 10 can be turned on normally, which can save driving power consumption.

[0093] Figure 10The second data voltage value Vdata2 transmitted on the data line S is positive and is greater than the voltage value provided by the second control signal line L2 (i.e., the second control signal value VL2 in the bootstrap phase J2). This means that for the N-type fourth transistor T4, the gate potential (second data voltage value Vdata2) of the fourth transistor T4 is greater than the source potential (second control signal value VL2), ensuring that the fourth transistor T4 is in the on-state during the bootstrap phase J2. The high-potential second control signal value VL2 is transmitted through the second transistor T2 to the second terminal C12 of the first capacitor C1. The voltage at the second terminal C12 of the first capacitor C1 decreases from the low-potential... When the first negative potential signal value VGL of the first capacitor C1 is raised to the high potential second control signal value VL2, the potential of the first terminal C11 of the first capacitor C1 will be coupled up to a higher voltage for secondary charging. Since the first terminal C11 of the first capacitor C1 is electrically connected to the gate line G, the potential transmitted on the gate line G is also raised to a higher voltage value. At this time, the potential transmitted on the gate line G, which is raised to a higher voltage value, can also be greater than the positive second data voltage value Vdata2 transmitted on the data line S. Therefore, by raising the potential of the gate line G through the bootstrap stage J2, it can be ensured that the switching transistor in the pixel unit 10 can be turned on normally, realizing low voltage input and high voltage output, which is beneficial to saving power consumption and ensuring display quality.

[0094] Optional, such as Figure 1 , Figure 7 and Figure 12 As shown, Figure 12 yes Figure 7 Another electrical connection structure diagram is shown. In this embodiment, in the display area AA of the display panel 000, the pixel unit 10 includes a switching transistor T0, a pixel electrode 101, and a common electrode 102; the gate of the switching transistor T0 is electrically connected to the gate line G, the source of the switching transistor T0 is electrically connected to the data line S, the drain of the switching transistor T0 is electrically connected to the pixel electrode 101, and the pixel electrode 101 is coupled to the common electrode 102.

[0095] This embodiment explains that the display panel 000 can be an electronic paper display panel, and the voltage of the gate line G can be provided by an integrated circuit subsequently bonded to the display panel 000. In the display area AA, the pixel unit 10 includes a switching transistor T0, a pixel electrode 101, and a common electrode 102. The gate of the switching transistor T0 is electrically connected to the gate line G. The voltage signal transmitted on the gate line G controls the opening and closing of the switching transistor T0. When the switching transistor T0 is open, the source and drain of the switching transistor T0 are connected. The data voltage signal transmitted on the data line S can be written to the pixel electrode 101 to form the grayscale voltage required for each grayscale level of the displayed image in each pixel unit 10. The pixel electrode 101 is coupled to the common electrode 102, and a fixed common potential signal Vcom is on the common electrode 102. Thus, a driving electric field is formed between the pixel electrode 101 and the common electrode 102, thereby completing the display image. In this embodiment, the boost circuit 20 can input a low-voltage first control signal value to the boost unit 200, input a low-voltage second control signal value to the boost unit 200, and output a high voltage from the boost unit 200 to the gate line G. This satisfies the requirement that the voltage provided by the gate line G to the gate of the switching transistor T0 in the pixel unit 10 is greater than the voltage value written by the data line S (the voltage provided by the gate line G to the gate of the switching transistor T0 in the pixel unit 10 is greater than the voltage value written by the data line S to the source of the switching transistor T0 in the pixel unit 10). This ensures normal conduction between the source and drain of the switching transistor T0 in the pixel unit 10, completing the charging of the pixel electrode 101 in the pixel unit 10 by the data line S. In this way, the driving power consumption of the panel can be reduced by the low-voltage input, and the driving signal can also be used to drive the panel normally, thus ensuring display quality.

[0096] Optionally, the film structure of the display panel 000 includes a first substrate and a second substrate (not shown in the attached diagram) disposed opposite to each other. The first substrate includes a pixel electrode 101, a switching transistor T0, and a boost circuit 20. The second substrate includes a common electrode 102. The first substrate can be understood as an array substrate. The switching transistor T0, pixel electrode 101, and other circuit structures in the pixel unit 10 of the display area AA, as well as the boost circuit 20 in the non-display area NA, can all be fabricated in the array substrate. The second substrate can be understood as an opposing substrate to the array substrate. The common electrode 102, which couples with the pixel electrode 101 to form an electric field, can be fabricated on one side of the opposing substrate. The common electrode 102 can be a full-surface structure. The common potential signal Vcom on the common electrode 102 can be transmitted to the common electrode 102 through the conductive silver paste of the non-display area NA after the first and second substrates are aligned. This simplifies the structure and ensures stable signal transmission.

[0097] In some alternative embodiments, please refer to the references. Figure 1and Figure 13 , Figure 13 yes Figure 1 A schematic diagram of another electrical connection structure between the boost unit and the pixel unit. In this embodiment, each boost unit 200 of the boost circuit 20 further includes a reset module 205.

[0098] The control terminal 205A of the reset module 205 is electrically connected to the third control signal line L3, the first terminal 205B of the reset module 205 is electrically connected to the gate line G, and the second terminal 205C of the reset module 205 is electrically connected to the first negative potential signal line L0.

[0099] This embodiment explains that in the boost circuit 20 located in the non-display area NA of the display panel 000, each boost unit 200 also includes a reset module 205. Whether the first terminal 205B and the second terminal 205C of the reset module 205 are turned on or off can be controlled by the third control signal value VL3 provided on the third control signal line L3 in the display panel 000. Specifically, the control terminal 205A of the reset module 205 is electrically connected to the third control signal line L3, the first terminal 205B of the reset module 205 is electrically connected to the gate line G, and the second terminal 205C of the reset module 205 is electrically connected to the first negative potential signal line L0. The third control signal value VL3 provided on the third control signal line L3 controls whether the residual charge of the gate line G is discharged to the first negative potential signal line L0. When the bootstrap stage J2 of the boost circuit 20 is completed, the residual charge of the gate line G can be discharged to the first negative potential signal line L0, so that the switching transistor T0 of the pixel unit 10 is turned off, achieving the clearing effect of the pixel unit 10, which is beneficial to the display of the next frame.

[0100] Optional, such as Figure 13 , Figure 14 and Figure 15 As shown, Figure 14 yes Figure 13 A schematic diagram of an electrical connection structure. Figure 15 yes Figure 14 The timing diagram of the input signal when the circuit structure is working is shown in this embodiment. The charging module 201 includes a first transistor T1, the first module 202 includes a second transistor T2, the initialization module 203 includes a third transistor T3, the gating module 204 includes a fourth transistor T4, and the reset module 205 includes a fifth transistor T5.

[0101] The gate of the first transistor T1 is electrically connected to the first control signal line L1, the source of the first transistor T1 is electrically connected to the gate of the first transistor T1, and the drain of the first transistor T1 is electrically connected to the gate line, the source of the fifth transistor T5, the gate of the second transistor T2, and the first terminal C11 of the first capacitor C1.

[0102] The source of the second transistor T2 is electrically connected to the drain of the fourth transistor T4, and the drain of the second transistor T2 is electrically connected to the second terminal C12 of the first capacitor C1 and the source of the third transistor T3.

[0103] The gate of the third transistor T3 is electrically connected to the first control signal line L1, and the drain of the third transistor T3 is electrically connected to the first negative potential signal line L0.

[0104] The gate of the fourth transistor T4 is electrically connected to the data line S, and the source of the fourth transistor T4 is electrically connected to the second control signal line L2.

[0105] The gate of the fifth transistor T5 is electrically connected to the third control signal line L3, and the drain of the fifth transistor T5 is electrically connected to the first negative potential signal line L0.

[0106] Optionally, in this embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the switching transistor T0 are of the same type.

[0107] Taking the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the switching transistor T0 as examples, all of which are N-type transistors, the first control signal line L1, the second control signal line L2, and the third control signal line L3 all provide the same high-potential signal so that each transistor is turned on under the high-potential signal.

[0108] like Figure 14 and Figure 15 As shown, taking the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the switching transistor T0 as N-type transistors, the operation process of each boost unit 200 in the boost circuit 20 can be as follows:

[0109] During the charging phase J1: The first control signal value VL1 provided by the first control signal line L1 is a high-potential signal (e.g., +5V), the second control signal value VL2 provided by the second control signal line L2 is a low-potential signal, and the third control signal value VL3 provided by the third control signal line L3 is a low-potential signal. The first transistor T1 and the third transistor T3 are turned on under the control of the high-potential first control signal value VL1, and the fifth transistor T5 is turned off under the control of the low-potential third control signal value VL3. A high-potential first control signal value VL1 (e.g., +5V) is gradually transmitted to the gate line G. At this time, the signal on the gate line G gradually rises to the high-potential first control signal value VL1 (e.g., +5V), and the signal on the first terminal C11 of the first capacitor C1 also gradually rises to the high-potential first control signal value VL1 (e.g., +5V). A low-potential first negative potential signal value VGL (e.g., -25V) provided by the first negative potential signal line L0 is transmitted to the second terminal C12 of the first capacitor C1, and the signal on the second terminal C12 of the first capacitor C1 is the low-potential first negative potential signal value VGL. Simultaneously, the high-potential first control signal value VL1 is transmitted to the gate of the second transistor T2 through the first transistor T1, causing the gate voltage of the second transistor T2 to gradually increase, and the second transistor T2 gradually begins to conduct.

[0110] Bootstrapping phase J2:

[0111] If the voltage signal transmitted on data line S is a negative voltage signal (e.g., -15V), the fourth transistor T4 is turned off; the first control signal value VL1 provided by the first control signal line L1 is a low-level signal, the second control signal value VL2 provided by the second control signal line L2 is a high-level signal, and the third control signal value VL3 provided by the third control signal line L3 is a low-level signal. The first transistor T1 and the third transistor T3 are turned off under the control of the low-level first control signal value VL1, and the fifth transistor T5 remains turned off under the control of the low-level third control signal value VL3. The gate of the second transistor T2 is already supplied with a high-potential signal (e.g., +5V) by the charging phase J1, so the second transistor T2 remains on. However, because the fourth transistor T4 is off, the high-potential second control signal value VL2 cannot be transmitted to the second terminal C12 of the first capacitor C1 through the second transistor T2. The voltage at the second terminal C12 of the first capacitor C1 remains the low-potential first negative potential signal value VGL (e.g., -25V) supplied by the first negative potential signal line L0 of the charging phase J1, while the first terminal C11 of the first capacitor C1 remains the high-potential signal supplied by the first control signal line L1. The first control signal value VL1 (e.g., +5V) means that the first capacitor C1 does not need to bootstrap, and there is no need to raise the potential of the first terminal C11 of the first capacitor C1 through coupling. At this time, the first control signal value VL1 (e.g., +5V) with a high potential provided by the first control signal line L1 of the charging stage J1 is still transmitted on the gate line G. Since the first control signal value VL1 (e.g., +5V) with a high potential must be greater than the negative voltage signal (e.g., -15V) transmitted on the data line S, it is not necessary to raise the potential of the gate line G at this time to ensure that the switching transistor T0 in the pixel unit 10 can be turned on normally.

[0112] If the voltage signal transmitted on the data line S is a positive voltage signal (e.g., +15V), the fourth transistor T4 is turned on; the first control signal value VL1 provided by the first control signal line L1 is a low-level signal, the second control signal value VL2 provided by the second control signal line L2 is a high-level signal (e.g., +5V), and the third control signal value VL3 provided by the third control signal line L3 is a low-level signal. The first transistor T1 and the third transistor T3 are turned off under the control of the low-level first control signal value VL1, and the fifth transistor T5 remains turned off under the control of the low-level third control signal value VL3. The gate of the second transistor T2 has already been supplied with a high-potential signal (e.g., +5V) during the charging phase J1, so the second transistor T2 remains on. Since the voltage signal transmitted on the data line S is a positive voltage signal (e.g., +15V) and is greater than the second control signal value VL2 (a high-potential signal, e.g., +5V), the fourth transistor T4 is turned on. The high-potential second control signal value VL2 (e.g., +5V) is transmitted through the second transistor T2 to the second terminal C12 of the first capacitor C1. The voltage at the second terminal C12 of the first capacitor C1 rises from the low-potential first negative potential signal value VGL (e.g., -25V) to the high-potential second control signal value. VL2 (e.g., +5V), the potential of the first terminal C11 of the first capacitor C1 will be coupled up to a higher voltage (e.g., from +5V in the charging stage J1 to +35V). The first terminal C11 of the first capacitor C1 is electrically connected to the gate line G, so the potential transmitted on the gate line G is also raised to a higher voltage value (e.g., +35V). At this time, the potential transmitted on the gate line G, which is raised to a higher voltage value (e.g., +35V), is greater than the positive voltage signal transmitted on the data line S (e.g., +15V). Therefore, by raising the potential of the gate line G through the bootstrap stage J2, it can be ensured that the switching transistor T0 in the pixel unit 10 can be turned on normally.

[0113] In the clearing phase J3: the first control signal value VL1 provided by the first control signal line L1 is a low-level signal, the second control signal value VL2 provided by the second control signal line L2 is a low-level signal, and the third control signal value VL3 provided by the third control signal line L3 is a high-level signal. The first transistor T1 and the third transistor T3 are cut off under the control of the low-level first control signal value VL1, while the fifth transistor T5 is turned on under the control of the high-level third control signal value VL3. The residual charge on the gate line G is then discharged to the first negative-level signal line L0. After the bootstrap phase J2 of the boost circuit 20 is completed, the residual charge on the gate line G can be discharged to the first negative-level signal line L0, causing the switching transistor T0 of the pixel unit 10 to turn off, achieving the clearing effect on the pixel unit 10, preparing for the next frame, and facilitating the display of the next frame. In this embodiment, the fifth transistor T5 of the reset module 205 is configured to discharge the residual charge of the gate line G to the first negative potential signal line L0 after the bootstrap stage J2 of the boost circuit 20 is completed, thereby achieving the clearing effect of the pixel unit 10, which is beneficial to the display of the next frame.

[0114] It is understood that in this embodiment Figure 14 and Figure 15 This example only illustrates the case where the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, and fifth transistor T5 are N-type transistors, and the switching transistor T0 included in the pixel unit 10 is also an N-type transistor. When the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, and fifth transistor T5 are P-type transistors, and the switching transistor T0 included in the pixel unit 10 is both an N-type and a P-type transistor, as follows... Figure 16 and Figure 17 As shown, Figure 16 yes Figure 13 Another electrical connection structure diagram, Figure 17 yes Figure 16The timing diagram of the input signals during the operation of the circuit structure shows that the first control signal line L1, the second control signal line L2, and the third control signal line L3 all provide the same low-potential signal. The gates of the first transistor T1, the second transistor T2, and the third transistor T3 are turned on under the low-potential first control signal value VL1, and the gate of the fifth transistor T5 is turned on under the low-potential third control signal value VL3. At this time, although the second control signal value VL2 is a low-potential signal, the low-potential second control signal value VL2 still needs to be greater than the low-potential first negative potential signal value VGL to achieve the bootstrap effect. This ensures that the voltage provided by the gate line G in the pixel unit 10 to the gate of the switching transistor in the pixel unit 10 is greater than the voltage value written by the data line of the source / drain of the switching transistor in the pixel unit 10, so that the high potential on the data line S can be normally written to the pixel unit 10, thus guaranteeing the display quality.

[0115] In some alternative embodiments, please refer to the references. Figure 4 and Figure 15 , Figure 18 and Figure 19 , Figure 18 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of the present invention. Figure 19 yes Figure 18 A schematic diagram of an electrical connection structure of the first driving circuit, the boost unit and the pixel unit is shown. In this embodiment, the non-display area NA of the display panel 000 includes the first driving circuit 30. The first driving circuit 30 includes a low-potential signal terminal 30L, which is electrically connected to the first terminal 205B of the reset module 205.

[0116] This embodiment explains that the non-display area NA of the display panel 000 can also include other circuit structures, such as a first driving circuit 30. The first driving circuit 30 includes a low-potential signal terminal 30L. It is understood that this embodiment does not specifically limit the structure of the first driving circuit 30, as long as the first driving circuit 30 includes a low-potential signal terminal 30L. That is, the first driving circuit 30 can be any circuit structure in the display panel 000 that includes a low-potential signal terminal 30L. For example, the first driving circuit 30 can be a gate driving circuit, which includes a pull-down module, and the pull-down module includes a low-potential signal terminal 30L. Since the first driving circuit 30 includes a low-potential signal terminal 30L, the first driving circuit 30 also needs to be connected to the first negative potential signal value VGL provided by the low-potential signal terminal 30L. Generally, the signal input of the circuit in the display panel 000 can be provided by the integrated circuit subsequently bonded to the display panel. Therefore, in this embodiment, the low-potential signal terminal 30L of the first driving circuit 30 is electrically connected to the first terminal 205B of the reset module 205, so that the first negative potential signal value VGL of multiple circuit structures in the panel is connected together. The first negative potential signal value VGL can be transmitted to the low-potential signal terminal 30L of the first driving circuit 30. At the same time, it can also be transmitted to the gate line G of the first terminal 205B of the reset module 205 when the first terminal 205B and the second terminal 205C of the reset module 205 are turned on during the clearing stage J3 of the boost circuit 20. In this embodiment, the low-potential signal terminal 30L of the first driving circuit 30 is connected to the first terminal 205B of the reset module 205 during the clearing phase. When the boost circuit 20 does not need to boost, the charge on the gate line G can be effectively discharged to the low-potential signal terminal 30L of the first driving circuit 30 through the conduction of the first terminal 205B and the second terminal 205C of the reset module 205, thereby maintaining the potential stability of the gate line G and the continuous shutdown of the switching transistor T0 in the pixel unit 10.

[0117] Optionally, in this embodiment, the first driving circuit 30 can be a gate driving circuit. The output terminal of the gate driving circuit can be used as the input terminal of the boost circuit. The gate driving circuit can include multiple cascaded shift registers (not shown in the figure). The output terminals of each shift register can be connected to the input terminal of the boost unit 200 so as to realize the input signal to each boost unit 200 of the boost circuit 20 one by one through the shift register function of the shift register, thereby realizing the effect of driving the gate line G of the display panel 000 line by line.

[0118] In existing technologies, in display panels using gate drive circuits, each level of shift register circuit can generally only output two different voltage signals (e.g., when the gate drive circuit in the existing technology is used to provide a scan drive signal to the gate line, it can generally only output two different voltage values, +15V and -25V, with a voltage difference of 40V). When the voltage provided on the data line S connected to the source of the switching transistor T in the pixel unit 10 in the display area AA is negative (e.g., -15V), the voltage on the gate line G that controls the N-type switching transistor T0 to open can only be +15V. Although this satisfies that the gate voltage (+15V) of the switching transistor T0 is greater than the drain voltage (-15V) of the switching transistor T0, the driving power consumption required by the gate drive circuit is very large.

[0119] In this embodiment, after the gate driving circuit and the boost circuit are electrically connected, the driving power consumption can be greatly reduced by setting the boost circuit 20. For example, when the voltage provided on the data line S connected to the source of the switching transistor T0 in the pixel unit 10 in the display area AA is negative (e.g., -15V), the gate voltage of the switching transistor T0 in the pixel unit 10 only needs to be greater than -15V to turn on the switching transistor. If the shift register circuit in the gate driving circuit is electrically connected to the boost unit 200, the signal output to the gate line is +5V (which is lower than the high voltage value in the prior art). That is, the gate voltage of the first transistor T1 in the boost unit 200 can be +5V output by the gate driving circuit. At this time, when the voltage provided on the data line S is negative (e.g., -15V), the boost unit 200 does not perform boost operation through the setting of the fourth transistor T4, and the voltage provided on the first control signal line L1 is... A voltage value (e.g., +5V) can be directly provided to the gate line G, causing the switching transistor T0 of the pixel unit 10 to conduct. When the voltage provided on the data line S is positive (e.g., +15V), the boost unit 200, through the setting of the fourth transistor T4, can boost the voltage on the gate line G when the fourth transistor T4 is conducting. At this time, the voltage value provided by the first control signal line L1 (e.g., +5V) can be boosted to a value greater than the positive voltage provided on the data line S by the boost unit 200 and then transmitted to the gate line G (e.g., as exemplified in the above embodiment, +5V from the charging stage J1 is coupled up to +35V, and +35V is greater than the positive voltage +15V provided on the data line S), thus also satisfying the requirement for the switching transistor T0 of the pixel unit 10 to conduct. Therefore, the combination of the boost circuit 200 and the gate driving circuit in this embodiment can reduce the high voltage value output by the gate driving circuit (e.g., the high voltage output in the prior art is +15V, while the high voltage output in this embodiment can be reduced to +5V) while satisfying the normal driving of the pixel unit 10. This can greatly reduce the voltage difference between the high and low voltage output by the gate driving circuit, which is beneficial to further reduce the driving power consumption of the panel.

[0120] In some alternative embodiments, please refer to the references. Figure 14 , Figure 15 and Figure 20 , Figure 20 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of the present invention. In this embodiment, the non-display area NA includes a bonding area BA, the bonding area BA includes multiple conductive pads BA1, and the gate line G is electrically connected to the conductive pads BA.

[0121] This embodiment explains that the non-display area NA of the display panel includes a bonding area BA, which includes multiple conductive pads BA1. These conductive pads BA1 can be used to subsequently bond an integrated driver circuit (IC, not shown in the figure) to the display panel. The driving of the gate line G can be achieved through the integrated driver circuit subsequently bonded to the bonding area BA, i.e., the gate line G is electrically connected to the conductive pads BA. In this embodiment, the gate line G is electrically connected to the conductive pads BA through a boost circuit 20. For example, one end of the first control signal line L1, the second control signal line L2, and the third control signal line L3 of each boost unit 200 in the boost circuit 20 can be connected to different conductive pads BA1 in the bonding area BA, respectively. The other end of 3 is connected to the input terminal of each boost unit 200 in the boost circuit 20. The output terminal of each boost unit 200 in the boost circuit 20 can be connected to the gate line G, so that the voltage signal on the gate line G can be directly bound to the integrated driving circuit by the display panel 000. In this embodiment, the boost circuit 20 is configured so that when the voltage signal provided by the integrated driving circuit subsequently bound to the display panel 000 is low, the voltage transmitted to the gate line G is a high voltage signal, realizing low voltage input and high voltage output, which is beneficial to saving power consumption and ensuring display quality.

[0122] It is understood that, in the display panel 000 of this embodiment, when the boost unit 200 is electrically connected to the conductive pad BA1 through the first control signal line L1, so that the voltage signal on the gate line G can be directly provided by the integrated driving circuit of the display panel 000, in order to achieve the sequential driving of the gate line G in the display panel 000, different boost units 200 can be electrically connected to different first control signal lines L1, different boost units 200 can be electrically connected to different second control signal lines L2, and different boost units 200 can be electrically connected to different third control signal lines L3, thereby ensuring the sequential opening of the pixel unit 10. Figure 20 The image below is merely an example showing the number of signal lines in the non-display area NA. Figure 20 The diagram only uses lines of different thicknesses to distinguish the first control signal line L1, the second control signal line L2, and the third control signal line L3 (this does not mean that the three lines are actually different thicknesses). In actual implementation, the number of control signal lines included in the non-display area NA can be set according to actual needs.

[0123] In some alternative embodiments, please refer to the references. Figure 1 , Figure 14 , Figure 15 and Figure 21 and Figure 22 , Figure 21This is a schematic diagram of another planar structure of the display panel provided in an embodiment of the present invention. Figure 22 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of the present invention. In this embodiment, the gate line G of the display panel 000 extends along the first direction X. Along the first direction X, the non-display area NA includes a first non-display area NA1 and a second non-display area NA2 located on opposite sides of the display area AA.

[0124] The boost circuit 20 is located in the first non-display area NA1 and / or the second non-display area NA2.

[0125] This embodiment explains that the non-display area NA of the display panel 000 includes a first non-display area NA1 and a second non-display area NA2 located on opposite sides of the display area AA. The boost circuit 20 disposed in the non-display area NA of the display panel 000 can be located in the first non-display area NA1 (e.g., ...). Figure 1 (as shown), or, the boost circuit 20 can be located in the second non-display area NA2 (as shown). Figure 21 (as shown), or part of the boost circuit 20 is located in the first non-display area NA1, and part of the boost circuit 20 is located in the second non-display area NA2 (as shown). Figure 22 As shown), part of the boost circuit 20 is located in the first non-display area NA1, and part of the boost circuit 20 is located in the second non-display area NA2, as shown. Figure 22 As shown, the gate lines G in the odd-numbered rows are electrically connected to the boost circuit 20 in the first non-display area NA1, and the gate lines G in the even-numbered rows are electrically connected to the boost circuit 20 in the second non-display area NA2, which makes the signal transmission of the boost circuit 20 to the gate lines G more uniform.

[0126] It is understood that this embodiment does not specifically limit the location of the boost circuit 20, as long as there is sufficient space in the non-display area NA to accommodate the boost circuit 20 without affecting the other structures of the non-display area NA. It is understood that this embodiment is only included to clearly illustrate its structure. Figure 21 and Figure 22 The diagram only shows the first control signal line L2 and the second control signal line L2 connected to part of the boost unit 200. The control signal lines connected to the remaining boost units 200 can be found in the reference diagram. Figure 20 To understand.

[0127] Optional, such as Figure 1 , Figure 7 , Figure 14 , Figure 15 and Figure 23 As shown, Figure 23 yes Figure 14 A simulation diagram of the driving signals for the circuit structure. Figure 23The horizontal axis represents the working process, and the vertical axis represents the voltage magnitude. Curve K1 represents the change in the voltage value provided by the data line S in the display panel 000; curve K2 represents the change in the voltage value transmitted on the gate line G when the data line S in the display panel 000 provides a negative first data voltage value Vdata1; curve K3 represents the change in the voltage value written to the pixel electrode 101 of the pixel unit 10 when the data line S in the display panel 000 provides a negative first data voltage value Vdata1; curve K4 represents the change in the voltage value transmitted on the gate line G when the data line S in the display panel 000 provides a positive second data voltage value Vdata2; and curve K5 represents the change in the voltage value written to the pixel electrode 101 of the pixel unit 10 when the data line S in the display panel 000 provides a negative second data voltage value Vdata2. As shown by curves K2 and K4, when the data line S provides a negative first data voltage value Vdata1, there is no need to raise the voltage of the gate line G. The voltage value transmitted on the gate line G can be greater than the negative first data voltage value Vdata1 provided by the data line S, ensuring that the switching transistor T0 of the pixel unit 10 is turned on normally. The negative first data voltage value Vdata1 provided by the data line S can charge the pixel electrode 101 of the pixel unit 10, and the pixel electrode 101 of the pixel unit 10 is written with the voltage value that enables display. When the data line S provides a positive second data voltage value Vdata2, the voltage value transmitted on the gate line G can be raised, and the raised value can be greater than the positive second data voltage value Vdata2 provided by the data line S. This ensures that the switching transistor T0 of the pixel unit 10 is turned on normally, and the positive second data voltage value Vdata2 provided by the data line S can charge the pixel electrode 101 of the pixel unit 10, and the pixel electrode 101 of the pixel unit 10 is written with the voltage value that enables display. Thus, during the bootstrap stage J2, panel driving power consumption can be saved.

[0128] In some alternative embodiments, please continue to refer to the references. Figure 1 , Figure 2 , Figure 3 and Figure 4 This embodiment provides a driving method for a display panel, which is applied to the display panel 000 in the above embodiment to drive display operations;

[0129] The driving method includes a charging phase J1 and a bootstrapping phase J2;

[0130] During the charging phase J1, the first control signal value VL1 provided by the first control signal line L1 controls the first terminal 201B and the second terminal 201C of the charging module 201 to be turned on. The first control signal value VL1 provided by the first control signal line L1 controls the first terminal 203B and the second terminal 203C of the initialization module 203 to be turned on. The first control signal value VL1 is transmitted to the gate line G, the control terminal 202A of the first module 202, and the first terminal C11 of the first capacitor C1. At this time, the second terminal C12 of the first capacitor C1 is the first negative potential signal value VGL transmitted by the first negative potential signal line L0.

[0131] During the bootstrap phase J2, the first control signal value VL1 controls the first terminal 202B and the second terminal 202C of the first module 202 to be turned on.

[0132] In the driving method of the display panel 000 provided in this embodiment, during the driving process, in the charging stage J1, the boost circuit 20 works, the first control signal line L1 provides the first control signal value VL1, under the control of the first control signal value VL1, the first terminal 201B and the second terminal 201C of the charging module 201 are turned on, the first terminal 203B and the second terminal 203C of the initialization module 203 are turned on, the first control signal value is transmitted to the gate line G, the control terminal 202A of the first module 202, and the first terminal C11 of the first capacitor C1 respectively, and the first negative potential signal value VGL provided by the first negative potential signal line L0 is transmitted to the second terminal C12 of the first capacitor C1;

[0133] During the bootstrap phase J2, the first control signal value VL1 controls the first terminal 202B and the second terminal 202C of the first module 202 to conduct. The second control signal line L2 provides the second control signal value VL2, which is transmitted to the second terminal C12 of the first capacitor C1. The voltage at the second terminal C12 of the first capacitor C1 is raised, and the voltage at the first terminal C11 of the first capacitor C1 is also raised by coupling with the second terminal C12. Therefore, during the charging phase J1 of the boost unit 200 of the boost circuit 20, the potential signal on the second terminal C12 of the first capacitor C1 is a smaller negative first negative potential signal value VGL provided by the first negative potential signal line L0, and the potential signal on the first terminal C11 of the first capacitor C1 is the first control signal value provided by the first control signal line L1. During the bootstrap phase J2, after the first control signal value VL1 provided by the first control signal line L1 further controls the conduction between the first terminal 202B and the second terminal 202C of the first module 202, the second control signal value VL2 provided by the second control signal line L2 can be transmitted to the second terminal C12 of the first capacitor C1 electrically connected to the second terminal 202C of the first module 202. This makes the potential signal on the second terminal C12 of the first capacitor C1 larger than the second control signal value VL2 provided by the second control signal line L2. Since the second control signal value VL2 provided by the second control signal line L2 is greater than the first negative potential signal value VGL provided by the first negative potential signal line L0, and the first capacitor C1 itself has bootstrap capability... Due to the coupling effect, when the potential signal on the second terminal C12 of the first capacitor C1 rises from a smaller first negative potential signal value VGL to a larger second control signal value VL2, the second terminal C12 of the first capacitor C1 is charged again, and the potential signal on the first terminal C11 of the first capacitor C1 is also further raised due to the bootstrap effect and transmitted to the gate line G. This enables the input of a low-voltage first control signal value to the boost unit 200, the input of a low-voltage second control signal value to the boost unit 200, and the output of a high voltage from the boost unit 200 to the gate line G. Thus, the driving power consumption of the panel can be reduced by using low-voltage input and high-voltage output, ensuring the normal driving of the panel by the driving signal and ensuring display quality.

[0134] Optional, such as Figure 1 , Figure 4 , Figure 7 and Figure 12 As shown, the display panel 000 also includes multiple data lines S, and the pixel unit 10 includes a switching transistor T0, a pixel electrode 101 and a common electrode 102. The gate of the switching transistor T0 is electrically connected to the gate line G, the source of the switching transistor T0 is electrically connected to the data line S, the drain of the switching transistor T0 is electrically connected to the pixel electrode 101, and the pixel electrode 101 is coupled to the common electrode 102.

[0135] During the bootstrap phase J2, the voltage value transmitted on the gate line G controls the switching transistor T0 to turn on, and the voltage value transmitted on the data line S is transmitted to the pixel electrode 101.

[0136] In the driving method provided in this embodiment, during the bootstrap stage J2, the voltage value transmitted on the gate line G controls the switching transistor T0 to turn on, and the voltage value transmitted on the data line S is transmitted to the pixel electrode 101. The gate of the switching transistor T0 of the pixel unit 10 is electrically connected to the gate line G. The voltage signal transmitted on the gate line G controls the opening and closing of the switching transistor T0. When the switching transistor T0 is turned on, the source and drain of the switching transistor T0 are connected. The data voltage signal transmitted on the data line S can be written into the pixel electrode 101 to form the gray level voltage required for each gray level of the displayed image in each pixel unit 10. The pixel electrode 101 is coupled to the common electrode 102, and the common electrode 102 has a fixed common potential signal Vcom. Thus, a driving electric field is formed between the pixel electrode 101 and the common electrode 102, thereby completing the display of the image. In this embodiment, the boost circuit 20 can input a low-voltage first control signal value VL1 and a low-voltage second control signal value VL2 to the boost unit 200, while a high voltage is output from the boost unit 200 to the gate line G. This satisfies the requirement that the voltage provided by the gate line G to the gate of the switching transistor T0 in the pixel unit 10 is greater than the voltage written by the data line S, ensuring normal conduction between the source and drain of the switching transistor T0 in the pixel unit 10. This completes the charging of the pixel electrode 101 in the pixel unit 10 by the data line S. In this way, the driving power consumption of the panel can be reduced by the low-voltage input, and the normal driving of the panel by the driving signal can be ensured, thus guaranteeing the display quality.

[0137] Optional, such as Figure 1 , Figure 4 , Figures 7-10 As shown, in the driving method provided in this embodiment, the boost unit 200 of the display panel 000 using this driving method further includes a gating module 204. The control terminal 204A of the gating module 204 is electrically connected to the data line S, the first terminal 204B of the gating module 204 is electrically connected to the second control signal line L2, and the second terminal 204C of the gating module 204 is electrically connected to the first terminal 202B of the first module 202. The voltage values ​​transmitted on the data line S include a first data voltage value Vdata1 and a second data voltage value Vdata2. The first data voltage value Vdata1 is negative and is less than the second control signal value VL2. The second data voltage value Vdata2 is positive and is greater than the second control signal value VL2.

[0138] When the display panel 000 is driven to display, the potential signal transmitted on the data line S includes a positive voltage signal and a negative voltage signal. That is, the voltage value transmitted on the data line S includes a negative first data voltage value Vdata1 and a positive second data voltage value Vdata2. In the bootstrap stage J2, when the voltage value transmitted on the data line S is the first data voltage value Vdata1, under the control of the first data voltage value Vdata1 provided by the data line S, the first terminal 204B and the second terminal 204C of the gating module 204 are disconnected. At this time, the voltage value transmitted on the gate line G is equal to the first control signal value VL1. Therefore, it is not necessary to raise the potential of the gate line G to ensure that the switching transistor in the pixel unit 10 can be turned on normally, which can save driving power consumption. When the voltage value transmitted on the data line S is the second data voltage value Vdata2, under the control of the second data voltage value Vdata2 provided by the data line S, the first terminal 204B and the second terminal 204C of the gating module 204 are turned on, and the second control signal value VL2 is transmitted to the second terminal C12 of the first capacitor C1. The second control signal value VL2 is greater than the first negative potential signal value VGL, and the voltage of the second terminal C12 of the first capacitor C1 is raised. The voltage of the first terminal C11 of the first capacitor C1 is coupled by the second terminal C12 of the first capacitor C1, and the voltage of the first terminal C11 of the first capacitor C1 is further raised. At this time, the voltage value transmitted on the gate line G is further raised to the third voltage value, and the third voltage value is greater than the first control signal value VL1. The third voltage value is greater than the second data voltage value Vdata2. This ensures that the switching transistor T0 of the pixel unit 10 can be turned on. At the same time, the potential of the first terminal C11 of the first capacitor C1 will be coupled up to a higher voltage and recharged to the third voltage value. That is, the potential transmitted on the gate line G is also raised to a higher third voltage value. By raising the potential of the gate line G through the bootstrap stage J2, it can be ensured that the switching transistor in the pixel unit 10 can be turned on normally, realizing low voltage input and high voltage output, which is beneficial to saving power consumption and ensuring display quality.

[0139] Optional, such as Figure 1 , Figures 13-15 As shown, in the driving method provided in this embodiment, the boost unit 200 of the display panel 000 to which the driving method is applied also includes a reset module 205;

[0140] The control terminal 205A of the reset module 205 is electrically connected to the third control signal line L3, the first terminal 205B of the reset module 205 is electrically connected to the gate line G, and the second terminal 205C of the reset module 205 is electrically connected to the first negative potential signal line L0. The driving method provided in this embodiment also includes a clearing stage J3.

[0141] During the reset phase J3, the third control signal line L3 provides the third control signal value VL3. The third control signal value VL3 controls the first terminal 205B and the second terminal 205C of the reset module 205 to be turned on, and the first negative potential signal value VGL is transmitted to the gate line G, and the switching transistor T0 is turned off.

[0142] This embodiment explains that the driving method of the display panel 000 also includes a clearing stage J3. In the clearing stage J3, the first control signal value VL1 provided by the first control signal line L1 is a low-potential signal, the second control signal value VL2 provided by the second control signal line L2 is a low-potential signal, and the third control signal value VL3 provided by the third control signal line L3 is a high-potential signal. The charging module 201 and the initialization module 203 are not turned on under the control of the low-potential first control signal value VL1, and the first terminal 205B and the second terminal 205C of the reset module 205 are turned on under the control of the high-potential third control signal value VL3. The residual charge of the gate line G is discharged to the first negative potential signal line L0. After the bootstrap stage J2 of the boost circuit 20 is completed, the residual charge of the gate line G can be discharged to the first negative potential signal line L0, so that the switching transistor T0 of the pixel unit 10 is turned off, achieving the clearing effect of the pixel unit 10, preparing for the next frame, which is beneficial to the display of the next frame. In the driving method of this embodiment, the setting of the clearing stage J3 allows the residual charge of the gate line G to be discharged to the first negative potential signal line L0 after the bootstrap stage J2 of the boost circuit 20 is completed, thereby achieving the clearing effect on the pixel unit 10, which is beneficial to the display of the next frame.

[0143] Optional, such as Figure 1 , Figures 13-15 , Figure 18 and Figure 19 As shown, in the driving method provided in this embodiment, the non-display area NA of the display panel 000 to which the driving method is applied includes a first driving circuit 30. The first driving circuit 30 includes a low-potential signal terminal 30L, which is electrically connected to the first terminal 205B of the reset module 205.

[0144] During the zeroing phase J3, the first driving circuit 30 operates, and the low-potential signal terminal 30L outputs the first negative potential signal value VGL. During the charging phase J1 and the bootstrap phase J2, the low-potential signal terminal 30L outputs a floating signal.

[0145] This embodiment explains that the driving method of the display panel 000 also includes a reset stage J3. In the reset stage J3, the low-potential signal terminal 30L of the first driving circuit 30 is connected to the first terminal 205B of the reset module 205. When the boost circuit 20 does not need to perform boost operation (i.e., it does not need to charge or bootstrap operation), the charge on the gate line G is effectively discharged to the low-potential signal terminal 30L of the first driving circuit 30 through the conduction of the first terminal 205B and the second terminal 205C of the reset module 205, maintaining the potential stability of the gate line G and the continuous off-state of the switching transistor T0 in the pixel unit 10. During the charging stage J1 and the bootstrap stage J2 of the boost circuit 20, the low-potential signal terminal 30L outputs a floating signal, which can prevent the signal of the low-potential signal terminal 30L of the first driving circuit 30 from affecting the driving operation of the boost circuit 20.

[0146] In some alternative embodiments, please refer to Figure 24 , Figure 24 This is a schematic diagram of the planar structure of the display device provided in the embodiment of the present invention. The display device 111 provided in this embodiment includes the display panel 000 provided in the above embodiment of the present invention. Figure 24 This embodiment uses a mobile phone as an example to illustrate the display device 111. It is understood that the display device 111 provided in this embodiment can be any other display device 111 with display functions, such as a computer, television, or in-vehicle display device; this invention does not impose specific limitations on this. The display device 111 provided in this embodiment has the beneficial effects of the display panel 000 provided in this embodiment. For details, please refer to the specific descriptions of the display panel 000 in the above embodiments; these will not be repeated here.

[0147] As can be seen from the above embodiments, the display panel, driving method, and display device provided by the present invention achieve at least the following beneficial effects:

[0148] The display panel provided by this invention includes a display area and a non-display area. The display area includes multiple pixel units and multiple gate lines, and the non-display area includes a boost circuit. Each boost unit in the boost circuit is used to increase the voltage transmitted on the gate lines. When the boost unit is working, the potential signal on the second terminal of the first capacitor is a smaller negative first negative potential signal value provided by the first negative potential signal line, and the potential signal on the first terminal of the first capacitor is a first control signal value provided by the first control signal line. After the first control signal value provided by the first control signal line further controls the conduction between the first and second terminals of the first module, the second control signal value provided by the second control signal line can be transmitted to the second terminal of the first capacitor electrically connected to the second terminal of the first module. This makes the potential signal on the second terminal of the first capacitor larger than the second control signal value provided by the second control signal line. Since the second control signal value is greater than the first negative potential signal value, and the first capacitor itself has a bootstrap coupling effect, when the potential signal on the second terminal of the first capacitor rises from a smaller first negative potential signal value to a larger second control signal value, the second terminal of the first capacitor is charged again. The potential signal on the first terminal of the first capacitor is also further raised due to the bootstrap effect. This allows the potential signal on the first terminal of the first capacitor to be transmitted to the gate line after the first control signal value is raised. This enables the input of a low-voltage first control signal value to the boost unit, the input of a low-voltage second control signal value to the boost unit, and the output of a high voltage from the boost unit to the gate line. Even if the voltage value written by the data line is very high, the boost circuit can ensure that the voltage value transmitted to the pixel unit on the gate line is also relatively high, ensuring the normal transmission of the drive signal of the pixel unit. This invention can achieve low voltage input and high voltage output by setting up a boost circuit, thereby reducing the driving power consumption of the panel, ensuring the normal driving of the panel by the driving signal, and ensuring display quality.

[0149] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, characterized in that, include: The display area includes a display area and a non-display area. The display area includes multiple pixel units, multiple gate lines, and multiple data lines. The gate lines are electrically connected to the pixel units. The non-display area includes a boost circuit, which includes multiple boost units, and each boost unit is electrically connected to at least one of the gate lines. The boost unit includes an electrically connected charging module, a bootstrap module, an initialization module, and a gating module, wherein the bootstrap module includes at least a first module and a first capacitor; The control terminal of the charging module is electrically connected to the first control signal line, the first terminal of the charging module is electrically connected to the control terminal of the charging module, and the second terminal of the charging module is electrically connected to the gate line, the control terminal of the first module, and the first electrode of the first capacitor, respectively. The first terminal of the first module is electrically connected to the second control signal line, and the second terminal of the first module is electrically connected to the second electrode of the first capacitor. The control terminal of the initialization module is electrically connected to the first control signal line, the first terminal of the initialization module is electrically connected to the second electrode of the first capacitor, and the second terminal of the initialization module is electrically connected to the first negative potential signal line. Wherein, the voltage value provided by the second control signal line is greater than the voltage value provided by the first negative potential signal line; The control terminal of the gating module is electrically connected to the data line, the first terminal of the gating module is electrically connected to the second control signal line, and the second terminal of the gating module is electrically connected to the first terminal of the first module.

2. The display panel according to claim 1, characterized in that, The first control signal line provides a first control signal value. Under the control of the first control signal value, the first and second terminals of the charging module are turned on, the first and second terminals of the initialization module are turned on, the first control signal value is transmitted to the gate line, the control terminal of the first module, and the first terminal of the first capacitor, respectively, and the voltage value provided by the first negative potential signal line is transmitted to the second terminal of the first capacitor. Under the control of the first control signal value, the first terminal and the second terminal of the first module are turned on. The second control signal line provides a second control signal value, which is transmitted to the second terminal of the first capacitor. The voltage at the second terminal of the first capacitor is raised, and the voltage at the first terminal of the first capacitor is raised by coupling with the second terminal of the first capacitor.

3. The display panel according to claim 1, characterized in that, The charging module includes a first transistor, the first module includes a second transistor, and the initialization module includes a third transistor; The gate of the first transistor is electrically connected to the first control signal line, the source of the first transistor is electrically connected to the gate of the first transistor, and the drain of the first transistor is electrically connected to the gate line, the gate of the second transistor, and the first electrode of the first capacitor, respectively. The source of the second transistor is electrically connected to the second control signal line, and the drain of the second transistor is electrically connected to the second terminal of the first capacitor. The gate of the third transistor is electrically connected to the first control signal line, the source of the third transistor is electrically connected to the second terminal of the first capacitor, and the drain of the third transistor is electrically connected to the first negative potential signal line.

4. The display panel according to claim 1, characterized in that, The voltage values ​​transmitted on the data line include a first data voltage value and a second data voltage value; The first data voltage value is negative, and the first data voltage value is less than the voltage value provided by the second control signal line; The second data voltage value is positive and is greater than the voltage value provided by the second control signal line.

5. The display panel according to claim 1, characterized in that, The pixel unit includes a switching transistor, a pixel electrode, and a common electrode; the gate of the switching transistor is electrically connected to the gate line, the source of the switching transistor is electrically connected to the data line, the drain of the switching transistor is electrically connected to the pixel electrode, and the pixel electrode is coupled to the common electrode.

6. The display panel according to claim 5, characterized in that, The display panel includes a first substrate and a second substrate disposed opposite to each other. The first substrate includes the pixel electrode, the switching transistor, and the boost circuit. The second substrate includes the common electrode.

7. The display panel according to claim 1, characterized in that, The gating module includes a fourth transistor; The gate of the fourth transistor is electrically connected to the data line, the source of the fourth transistor is electrically connected to the second control signal line, and the drain of the fourth transistor is electrically connected to the first terminal of the first module.

8. The display panel according to claim 5, characterized in that, The boost unit also includes a reset module; The control terminal of the reset module is electrically connected to the third control signal line, the first terminal of the reset module is electrically connected to the gate line, and the second terminal of the reset module is electrically connected to the first negative potential signal line.

9. The display panel according to claim 8, characterized in that, The charging module includes a first transistor, the first module includes a second transistor, the initialization module includes a third transistor, the gating module includes a fourth transistor, and the reset module includes a fifth transistor; The gate of the first transistor is electrically connected to the first control signal line, the source of the first transistor is electrically connected to the gate of the first transistor, and the drain of the first transistor is electrically connected to the gate line, the source of the fifth transistor, the gate of the second transistor, and the first electrode of the first capacitor, respectively. The source of the second transistor is electrically connected to the drain of the fourth transistor, and the drain of the second transistor is electrically connected to the second terminal of the first capacitor and the source of the third transistor, respectively. The gate of the third transistor is electrically connected to the first control signal line, and the drain of the third transistor is electrically connected to the first negative potential signal line. The gate of the fourth transistor is electrically connected to the data line, and the source of the fourth transistor is electrically connected to the second control signal line. The gate of the fifth transistor is electrically connected to the third control signal line, and the drain of the fifth transistor is electrically connected to the first negative potential signal line.

10. The display panel according to claim 9, characterized in that, The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the switching transistor are of the same type.

11. The display panel according to claim 9, characterized in that, The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the switching transistor are all N-type transistors; The first control signal line, the second control signal line, and the third control signal line all provide the same high-potential signal.

12. The display panel according to claim 9, characterized in that, The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the switching transistor are all P-type transistors; the first control signal line, the second control signal line, and the third control signal line all provide the same low-potential signal.

13. The display panel according to claim 8, characterized in that, The non-display area includes a first driving circuit, which includes a low-potential signal terminal that is electrically connected to the first terminal of the reset module.

14. The display panel according to claim 13, characterized in that, The first driving circuit includes a gate driving circuit, the gate driving circuit includes a pull-down module, and the pull-down module includes the low-potential signal terminal.

15. The display panel according to claim 1, characterized in that, The non-display area includes a bonding area, which includes multiple conductive pads, and the gate line is electrically connected to the conductive pads.

16. The display panel according to claim 1, characterized in that, The gate line extends along a first direction, and along the first direction, the non-display area includes a first non-display area and a second non-display area located on opposite sides of the display area; The boost circuit is located in the first non-display area and / or the second non-display area.

17. A driving method for a display panel, characterized in that, The driving method is applied to the display panel according to any one of claims 1-16; the display panel further includes multiple data lines, the pixel unit includes a switching transistor, a pixel electrode, and a common electrode, the gate of the switching transistor is electrically connected to the gate line, the source of the switching transistor is electrically connected to the data line, the drain of the switching transistor is electrically connected to the pixel electrode, and the pixel electrode is coupled to the common electrode; the boost unit further includes a gating module, the control terminal of the gating module is electrically connected to the data line, the first terminal of the gating module is electrically connected to the second control signal line, the second control signal line provides a second control signal value, and the second terminal of the gating module is electrically connected to the first terminal of the first module; The driving method includes a charging phase and a bootstrapping phase; During the charging phase, the first control signal value provided by the first control signal line controls the first and second terminals of the charging module to be turned on, and the first control signal value provided by the first control signal line controls the first and second terminals of the initialization module to be turned on. The first control signal value is transmitted to the gate line, the control terminal of the first module, and the first electrode of the first capacitor, respectively. At this time, the second electrode of the first capacitor is the first negative potential signal value transmitted by the first negative potential signal line. During the bootstrap phase, the first control signal value controls the first and second terminals of the first module to be turned on. During the bootstrap phase, the voltage value transmitted on the gate line controls the switching transistor to turn on, and the voltage value transmitted on the data line is transmitted to the pixel electrode. The voltage values ​​transmitted on the data line include a first data voltage value and a second data voltage value. The first data voltage value is negative and is less than the second control signal value. The second data voltage value is positive and is greater than the second control signal value.

18. The driving method according to claim 17, characterized in that, When the voltage transmitted on the data line is the first data voltage value, during the bootstrap phase, under the control of the first data voltage value provided by the data line, the first and second terminals of the gating module are disconnected, and at this time the voltage transmitted on the gate line is equal to the first control signal value.

19. The driving method according to claim 17, characterized in that, When the voltage value transmitted on the data line is the second data voltage value, during the bootstrap phase, under the control of the second data voltage value provided by the data line, the first and second terminals of the gating module are turned on, the second control signal value is transmitted to the second terminal of the first capacitor, the second control signal value is greater than the first negative potential signal value, the voltage of the second terminal of the first capacitor is raised, the voltage of the first terminal of the first capacitor is coupled by the second terminal of the first capacitor, the voltage of the first terminal of the first capacitor is further raised, at this time the voltage value transmitted on the gate line is further raised to the third voltage value, the third voltage value is greater than the first control signal value.

20. The driving method according to claim 19, characterized in that, The third voltage value is greater than the second data voltage value.

21. The driving method according to claim 17, characterized in that, The boost unit also includes a reset module; The control terminal of the reset module is electrically connected to the third control signal line, the first terminal of the reset module is electrically connected to the gate line, and the second terminal of the reset module is electrically connected to the first negative potential signal line. The driving method also includes a zeroing phase; During the reset phase, the third control signal line provides a third control signal value, which controls the first and second terminals of the reset module to be turned on, the first negative potential signal value is transmitted to the gate line, and the switching transistor is turned off.

22. The driving method according to claim 21, characterized in that, The non-display area includes a first driving circuit, which includes a low-potential signal terminal, and the low-potential signal terminal is electrically connected to the first terminal of the reset module. During the zeroing phase, the first driving circuit operates, and the low-potential signal terminal outputs the first negative potential signal value.

23. The driving method according to claim 22, characterized in that, During the charging phase and the bootstrap phase, the low-potential signal terminal outputs a floating signal.

24. A display panel, characterized in that, include: The display area includes a display area and a non-display area. The display area includes multiple pixel units and multiple gate lines, and the gate lines are electrically connected to the pixel units. The non-display area includes a boost circuit, which includes multiple boost units, and each boost unit is electrically connected to at least one of the gate lines. The boost unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor that are electrically connected. The gate of the first transistor is electrically connected to the first control signal line, the source of the first transistor is electrically connected to the gate of the first transistor, and the drain of the first transistor is electrically connected to the gate line, the gate of the second transistor, and the first electrode of the first capacitor, respectively. The source of the second transistor is electrically connected to the second control signal line, and the drain of the second transistor is electrically connected to the second terminal of the first capacitor. The gate of the third transistor is electrically connected to the first control signal line, the source of the third transistor is electrically connected to the drain of the second transistor, and the drain of the third transistor is electrically connected to the first negative potential signal line; wherein, the voltage value provided by the second control signal line is greater than the voltage value provided by the first negative potential signal line. The gate of the fourth transistor is electrically connected to the data line, the source of the fourth transistor is electrically connected to the second control signal line, and the drain of the fourth transistor is electrically connected to the source of the second transistor.

25. The display panel according to claim 24, characterized in that, The boost unit also includes a fifth transistor; The gate of the fifth transistor is electrically connected to the third control signal line, the source of the fifth transistor is electrically connected to the drain of the first transistor, and the drain of the fifth transistor is electrically connected to the first negative potential signal line.

26. A display device, characterized in that, Includes the display panel as described in any one of claims 1-16.

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