Display panel and display device

Abstract

The present application relates to the technical field of display, in particular to a display panel and a display device; a pixel circuit comprises a driving module, a first light emitting control module and a second light emitting control module; the first light emitting control module and the second light emitting control module are used for jointly controlling the light emitting duration of the light emitting element; the first light emitting control module is electrically connected with a first light emitting control signal line, and the second light emitting control module is connected with a second light emitting control signal line; the present application adopts the first light emitting control module and the second light emitting control module to jointly control the light emitting duration of the light emitting element, the gray scale of the pixel can be adjusted by changing the control signals transmitted by the first light emitting control signal line and the second light emitting control signal line; in addition, the first light emitting control signal line and the second light emitting control signal line are intersected, which is helpful to simplify the number of the first light emitting control signal line and the second light emitting control signal line, and the control is simple, the structure is simple, and it is helpful to realize high ppi.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] Micro-LED is a next-generation display technology that offers higher brightness, better luminous efficiency, and lower power consumption than existing OLEDs. In Micro-LED, it's desirable to maximize the current, thus requiring control over grayscale brightness by adjusting the emission time. While some technologies use emission time to adjust Micro-LED grayscale, the pixel circuitry used for this adjustment is actively driven, resulting in a complex structure that makes it difficult to design high ppi (pixels per inch) pixels in practical applications. Summary of the Invention

[0003] In view of this, the present invention provides a display panel and display device, which aims to reduce the complexity of pixel circuits and control the grayscale of pixels by means of light emission time.

[0004] In a first aspect, the present invention provides a display panel, including pixel circuits, light-emitting elements, and signal lines; The pixel circuit is electrically connected to the light-emitting element, and the pixel circuit includes a driving module, a first light-emitting control module, and a second light-emitting control module. The driving module is used to drive the light-emitting element to emit light; The first light-emitting control module and the second light-emitting control module are used to jointly control the light-emitting duration of the light-emitting element; The signal lines include a first light-emitting control signal line and a second light-emitting control signal line. The first light-emitting control module is electrically connected to the first light-emitting control signal line. The first light-emitting control signal line extends along a first direction, which is parallel to the plane of the display panel. The second light-emitting control module is connected to the second light-emitting control signal line. The second light-emitting control signal line extends along a second direction, which is parallel to the plane of the display panel. The first direction and the second direction intersect.

[0005] Secondly, the present invention also provides a display device comprising a display panel with any of the above-described structures.

[0006] Compared with related technologies, the display panel and display device provided by the present invention achieve at least the following beneficial effects: This invention employs a first light-emitting control module and a second light-emitting control module to jointly control the light-emitting duration of the light-emitting element. The control signals of the first and second light-emitting control modules can be transmitted through the first and second light-emitting control signal lines, respectively. Therefore, the grayscale of the pixel can be adjusted by changing the control signals transmitted by the first and second light-emitting control signal lines. Furthermore, the first and second light-emitting control signal lines are intersected, forming a grid-like control structure. This helps to reduce the number of first and second light-emitting control signal lines, and the control and structure are simple, which is conducive to achieving high ppi (Pixels Per Inch).

[0007] Of course, any product implementing this invention does not necessarily need to achieve all of the technical effects described above at the same time.

[0008] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0010] Figure 1 The diagram shown is a pixel circuit diagram of the related technology; Figure 2 The diagram shown is a schematic of a pixel circuit array related to the technology. Figure 3 As shown Figure 2 A timing diagram of the pixel circuit array shown; Figure 4 The diagram shown is a schematic representation of the components of a display panel provided by the present invention. Figure 5 The diagram shown is another component of the display panel provided by the present invention. Figure 6 The diagram shown is another component of the display panel provided by the present invention; Figure 7 The diagram shown is a driving timing diagram of the pixel circuit of the present invention; Figure 8 The figure shown is a specific embodiment of the pixel circuit of the display panel of the present invention; Figure 9 The figure shown is a specific embodiment of the pixel circuit of the display panel of the present invention; Figure 10 The image shown is a schematic diagram of a display panel provided by the present invention; Figure 11The image shown is a schematic diagram of a display panel provided by the present invention; Figure 12 The image shown is a schematic diagram of a display panel provided by the present invention; Figure 13 The data writing timing diagram provided for this invention; Figure 14 The image shown is a schematic diagram of a display panel provided by the present invention; Figure 15 The data writing timing diagram provided for this invention; Figure 16 A timing diagram of a display panel provided by the present invention; Figure 17 The figure shows a driving timing diagram of a display panel provided by the present invention; Figure 18 The diagram shown is a structural schematic of a display device provided by the present invention. Detailed Implementation

[0011] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0012] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0013] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0014] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0015] Various modifications and variations can be made to this invention without departing from its spirit or scope, as will be apparent to those skilled in the art. Therefore, this invention is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this invention can be combined with each other without contradiction.

[0016] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0017] The display panel of the present invention includes a pixel circuit, a light-emitting element, and signal lines. The pixel circuit is electrically connected to the light-emitting element and includes a driving module, a first light-emitting control module, and a second light-emitting control module. The driving module is used to drive the light-emitting element to emit light. The first light-emitting control module and the second light-emitting control module are used to jointly control the light-emitting duration of the light-emitting element. The signal lines include a first light-emitting control signal line and a second light-emitting control signal line. The first light-emitting control module is electrically connected to the first light-emitting control signal line, which extends along a first direction parallel to the plane of the display panel. The second light-emitting control module is connected to the second light-emitting control signal line, which extends along a second direction parallel to the plane of the display panel. The first direction and the second direction intersect.

[0018] This invention employs a first light-emitting control module and a second light-emitting control module to jointly control the light-emitting duration of the light-emitting element. The control signals of the first and second light-emitting control modules can be transmitted through the first and second light-emitting control signal lines, respectively. Therefore, the grayscale of the pixel can be adjusted by changing the control signals transmitted by the first and second light-emitting control signal lines. Furthermore, the first and second light-emitting control signal lines are intersected, forming a grid-like control structure. This helps to reduce the number of first and second light-emitting control signal lines, and the control and structure are simple, which is conducive to achieving high ppi (Pixels Per Inch).

[0019] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0020] To address the technical problems mentioned in the background section, a solution is proposed. Figure 1 The image shown is the pixel circuit diagram of this solution. Figure 2 The diagram shown is a schematic of a pixel circuit array. Figure 3 As shown Figure 2 The shown pixel circuit array is a timing diagram; please refer to it. Figure 1 , Figure 2 and Figure 3 .

[0021] like Figure 1As shown, the pixel circuit P includes a driving transistor M1. The control terminal of the driving transistor M1 is used to connect to the control signal Gate. The first terminal of the driving transistor M1 is used to connect to the power supply signal VDD. The second terminal of the driving transistor M1 is used to connect to the anode of the light-emitting element to drive the light-emitting element to emit light.

[0022] like Figure 2 As shown, the pixel circuit P is arranged in a matrix of three rows and three columns. The scan signal lines S1, S2 and S3 that provide the control signal Gate are arranged in rows, and the power signal lines VDD1, VDD2 and VDD3 that provide the power signal VDD are arranged in columns.

[0023] like Figure 3 As shown, when the pixel circuit P is driven, the scanning signal lines S1, S2 and S3 turn on the driving transistor M1 row by row through the control signal Gate. When the driving transistor M1 is turned on in each row, the light emission time of each frame is determined according to the duration of the high level of the power supply signal VDD, and the light emission brightness is determined.

[0024] Figure 1 , Figure 2 and Figure 3 The pixel circuit and driving timing shown have a simple pixel circuit structure and a simple driving method. However, this pixel circuit and driving method have high requirements for the driving IC, require the use of multiple current source devices, and have a high cost.

[0025] Please refer to Figure 4 and Figure 5 , Figure 4 The diagram shown is a schematic representation of the composition of a display panel provided by the present invention. Figure 5 The diagram shows another schematic of the display panel provided by the present invention. The display panel provided by the present invention includes a pixel circuit P, a light-emitting element 4, and signal lines. The pixel circuit P is electrically connected to the light-emitting element 4. The pixel circuit P includes a driving module 1, a first light-emitting control module 2, and a second light-emitting control module 3. The driving module 1 is used to drive the light-emitting element 4 to emit light. The first light-emitting control module 2 and the second light-emitting control module 3 are used to jointly control the light-emitting duration of the light-emitting element 4. The signal lines include a first light-emitting control signal line EA and a second light-emitting control signal line EB. The first light-emitting control module 2 is electrically connected to the first light-emitting control signal line EA. The first light-emitting control signal line EA extends along a first direction V1, which is parallel to the plane of the display panel. The second light-emitting control module 3 is connected to the second light-emitting control signal line EB. The second light-emitting control signal line EB extends along a second direction V2, which is parallel to the plane of the display panel. The first direction V1 and the second direction V2 intersect.

[0026] Figure 4The pixel circuit used and Figure 1 Compared to the pixel circuit shown, the scheme of using the VDD power signal as the control signal for the light emission time is abandoned. Instead, a first light emission control module 2 and a second light emission control module 3 are set up. The light emission time of the light emission element 4 is determined by the coordinated work of the first light emission control module 2 and the second light emission control module 3. This makes the light emission time of the light emission element 4 driven by the pixel circuit P no longer dependent on the VDD power signal, thus reducing the cost of the driver IC.

[0027] Figure 6 The diagram shown is another component of the display panel provided by the present invention. Please refer to it. Figure 6 In some optional embodiments of the present invention, the pixel circuit P of the present invention further includes a data writing module 5, which is used to transmit data signals to the control terminal of the driving module 1.

[0028] Specifically, such as Figure 6 As shown, the data writing module 5 is connected to the scan signal line S and the data signal line D. Under the control of the valid signal transmitted by the scan signal line S, the data signal DATA is written to the drive module 1 through the data signal line D. In specific applications, the output current of the drive module 1 can be controlled by the data signal DATA written by the data writing module 5.

[0029] Figure 7 The diagram shown is a driving timing diagram of the pixel circuit of this invention. Please refer to it. Figure 5 and Figure 7 , Figure 5 S1, S2, and S3 are all scanning signal lines, D1, D2, and D3 are all data signal lines, EA1, EA2, and EA3 are all first light emission control signal lines, and EB1, EB2, and EB3 are all second light emission control signal lines. Figure 7In this context, t1 is the effective time period of the scan signal SCAN1 transmitted by scan signal line S1, t2 is the effective time period of the scan signal SCAN2 transmitted by scan signal line S2, and t3 is the effective time period of the scan signal SCAN2 transmitted by scan signal line S3; t1' is the effective time period of the signal transmitted by the first sub-light emission control signal line EA1, t2' is the effective time period of the signal transmitted by the second sub-light emission control signal line EA2, and t3' is the effective time period of the signal transmitted by the fifth sub-light emission control signal line EA3; t11' is the first effective time period of the signal transmitted by the third sub-light emission control signal line EB1, and t12' is the first effective time period of the signal transmitted by the third sub-light emission control signal line EB1. The second valid time period of the signal is t13', which is the third valid time period of the signal transmitted by the third sub-light emission control signal line EB3; t21' is the first valid time period of the signal transmitted by the fourth sub-light emission control signal line EB2, t22' is the second valid time period of the signal transmitted by the fourth sub-light emission control signal line EB2, t23' is the third valid time period of the signal transmitted by the fourth sub-light emission control signal line EB2; t31' is the first valid time period of the signal transmitted by the sixth sub-light emission control signal line EB3, t32' is the second valid time period of the signal transmitted by the sixth sub-light emission control signal line EB3, t33' is the third valid time period of the signal transmitted by the sixth sub-light emission control signal line EB3.

[0030] Please combine Figure 5 , Figure 6 and Figure 7 When adjusting the grayscale of the light-emitting element, the light intensity can be adjusted first. For example, under the control of the effective signal transmitted by the scanning signal line S1, data signal DATA1 can be written to the driving module 1 of pixel circuit P1 through data signal line D1, data signal DATA2 can be written to the driving module 1 of pixel circuit P2 through data signal line D2, and data signal DATA3 can be written to the driving module 1 of pixel circuit P3 through data signal line D3. The data signal writing method in pixel circuits P4, P5, P6, P7, P8, and P9 is the same as that in pixel circuits P1, P2, and P3. The output current of each pixel circuit can be adjusted by adjusting the input DATA signal to control the light intensity.

[0031] Then, the light emission duration is adjusted. For example, the effective phase t1' of the first light emission control signal EMA1 transmitted by the first light emission control signal line EA1 and the effective phase t11' of the second light emission control signal EMB1 transmitted by the second light emission control signal line EB1 can be controlled by the overlap of their effective phases to control the light emission duration of the light-emitting element 4 driven by the pixel circuit P1. Similarly, the effective phases of the first light emission control signals transmitted by the first light emission control signal lines EA1, EA2, and EA3 and the effective phases of the second light emission control signals transmitted by the second light emission control signal lines EB1, EB2, and EB3 can be adjusted by the overlap of their effective phases to control the light emission duration of the light-emitting element driven by the corresponding pixel circuit.

[0032] Specifically, the light intensity of the light-emitting element 4 is first controlled by the data writing module 5, and then the light emission duration of the light-emitting element 4 is controlled by the first light emission control signal line EA and the second light emission control signal line EB. In this way, the grayscale of the light-emitting element 4 can be adjusted from two dimensions: light emission time and light emission intensity. This increases the possibilities for grayscale adjustment levels, resulting in a more delicate image, suitable for high-end products. Furthermore, light emission time and light emission intensity can be used in combination to adjust pixel grayscale. For example, in Micro-LEDs, it is desirable to set the current as high as possible, thus requiring precise control of the light emission time to control grayscale brightness, ensuring that the LED operates at the optimal current at different grayscale levels. Alternatively, when displaying low grayscale levels, the precision of the light emission time control may be insufficient, and current intensity can be used for auxiliary adjustment.

[0033] It should be noted that, Figure 5 The display panel includes 9 pixel circuits. This is only for the convenience of illustrating the technical solution, and does not mean that the panel only includes 9 pixel circuits. Its purpose is to illustrate the method of adjusting pixel grayscale by current intensity and adjusting pixel grayscale by light emission time in this invention, and is not intended to limit the structure of the display panel of this invention. In actual applications, the number of pixel circuits in the panel can be determined according to actual needs.

[0034] Figure 8 The diagram shows a specific embodiment of the pixel circuit of the display panel of the present invention. Please refer to it. Figure 8In some optional embodiments of the present invention, the first light-emitting control module 2 includes a first sub-control module 21, the first end of the first sub-control module 21 is used to receive a power signal VDD, the second end of the first sub-control module 21 is electrically connected to the first end of the driving module 1, and the control end of the first sub-control module 21 is electrically connected to the first light-emitting control signal line EA; the first end of the second light-emitting control module 3 is electrically connected to the driving module 1, the second end of the second light-emitting control module 3 is electrically connected to the anode of the light-emitting element 4, and the control end of the second light-emitting control module 3 is electrically connected to the second light-emitting control signal line EB.

[0035] Specifically, please combine Figure 6 and Figure 8 The pixel circuit P includes a first sub-control module 21, a driving module 1, a second light-emitting control module 3, and a data writing module 5. The first sub-control module 21 includes a first transistor T1, the driving module 1 includes a second transistor T2, the second light-emitting control module 3 includes a third transistor T3, and the data writing module 5 includes a fourth transistor T4. The first electrode of the first transistor T1 receives the power signal VDD, and the second electrode of the first transistor T1 is electrically connected to the first electrode of the second transistor T2. The control electrode of the first transistor T1 is electrically connected to the first light-emitting control signal line EA, which transmits the first light-emitting control signal EMA. The first electrode of the third transistor T3 is electrically connected to the second electrode of the second transistor T2, and the second electrode of the third transistor T3 is electrically connected to the anode of the light-emitting element 4. The first electrode of the third transistor T3 is electrically connected to the second light-emitting control signal line EB, which transmits the second light-emitting control signal EMB. The control electrode of the fourth transistor T4 receives the scan signal SCAN, the first electrode of the fourth transistor T4 receives the data signal DATA, and the second electrode of the fourth transistor T4 is electrically connected to the control electrode of the second transistor T2.

[0036] Figure 9 The diagram shows a specific embodiment of the pixel circuit of the display panel of the present invention. Please refer to the diagram for details. Figure 6 and Figure 9 In some optional embodiments of the present invention, the first light-emitting control module 2 further includes a second sub-control module 22, which is located between the driving module 1 and the second light-emitting control module 3. The first end of the second sub-control module 22 is electrically connected to the second end of the driving module 1, the second end of the second sub-control module 22 is electrically connected to the first end of the second light-emitting control module 3, and the control end of the second sub-control module 22 is electrically connected to the first light-emitting control signal line EA.

[0037] Please continue to refer to this. Figure 9 ,exist Figure 9In the embodiment shown, the second sub-control module 22 includes a fifth transistor T5, which is located between the driving module 1 and the second light-emitting control module 3. The first electrode of the fifth transistor T5 is electrically connected to the second electrode of the second transistor T2, and the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3. The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting control signal line EA, which is used to transmit the first light-emitting control signal EMA.

[0038] It should be noted that the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 in the above pixel circuit can all be PMOS or all be NMOS, or some transistors can be PMOS and some can be NMOS; whether the first electrode and the second electrode are the source and drain of the transistors needs to be determined according to the specific circuit.

[0039] Please continue to refer to this. Figure 9 The first light-emitting control module of this invention includes a first sub-control module 2 and a second sub-control module 6. The second sub-control module 6 is located between the driving module 1 and the second light-emitting control module 3. Its main function is to stabilize the driving current of the driving module 1, so that after the data writing of the pixel circuit in this row, the second light-emitting control module 3 of the pixel circuit in this row can be in a conducting state during the data writing process of other pixel circuits. In the cycle of one frame of this invention, the light-emitting phase of the light-emitting element 4 overlaps with part of the data writing phase; therefore, by setting the second sub-control module 6, this invention can advance the light-emitting phase of the light-emitting element 4.

[0040] Please continue to refer to this. Figure 8 and Figure 9 In some specific embodiments, the pixel circuit includes a capacitor C. The first plate of capacitor C is electrically connected to the control electrode of the second transistor T2, and the second plate of capacitor C is electrically connected to a first fixed potential line. It should be noted that the first fixed potential line is used to transmit a first fixed potential, which can be the display panel power signal VDD or other fixed voltage signals.

[0041] Please continue to refer to this. Figure 5 and Figure 6 In some optional embodiments of the present invention, the first end of the data writing module 5 is electrically connected to the data signal line S, the data signal line S extends along a third direction V3, and the third direction V3 is parallel to the plane where the display panel is located; the control end of the data writing module 5 is electrically connected to the scan signal line S, the scan signal line S extends along a fourth direction V4, the fourth direction V4 is parallel to the plane where the display panel is located, and the third direction V3 intersects with the fourth direction V4.

[0042] Please refer to Figure 5 , Figure 5 S1, S2, and S3 are all scanning signal lines. The first scanning signal line S1, the second scanning signal line S2, and the third scanning signal line S3 all extend along the fourth direction V4. Each scanning signal line is electrically connected to the control terminal of the data writing module of the pixel circuit in its respective direction (fourth direction). D1, D2, and D3 are all data signal lines. The first data signal line D1, the second data signal line D2, and the third data signal line D3 all extend along the third direction V3. Each data signal line is electrically connected to the control terminal of the data writing module of the pixel circuit in its respective direction (third direction V3), forming a grid-like data writing structure, which can write data voltage signals to each pixel circuit in the pixel circuit array.

[0043] It should be noted that Figure 5 The layout of the pixel circuit and signal lines shown is only one embodiment of the present invention, and the layout of the pixel circuit and signal lines of the present invention can also have other forms.

[0044] In some alternative embodiments of the present invention, the third direction V3 is parallel to the first direction V1; or, the third direction V3 is parallel to the second direction V2.

[0045] Please combine Figure 5 and Figure 7 Specifically, the third direction V3 is parallel to the first direction V1; or, the third direction V3 is parallel to the second direction V2. This applies to some square displays; please refer to [reference needed]. Figure 5 , Figure 5It includes multiple pixel circuits, such as pixel circuit P1, pixel circuit P2, pixel circuit P3... pixel circuit P9. Pixel circuits P1, P2, P3... pixel circuit P9 are arranged in a rectangular pattern. EA1, EA2, and EA3 are first light-emitting control signal lines, and EB1, EB2, and EB3 are second light-emitting control signal lines. The extension direction of the first light-emitting control signal lines EA1, EA2, and EA3 is the first direction V1, and the extension direction of the second light-emitting control signal lines EB1, EB2, and EB3 is... The second direction is V2; D1, D2, and D3 are all data signal lines, and the extension direction of each data signal line D1, D2, and D3 is the third direction V3, which is parallel to the second direction V2; S1, S2, and S3 are all scan signal lines, and the extension direction of each scan signal line S1, S2, and S3 is the fourth direction V4; the first light emission control signal line EA1 is connected to pixel circuits P1, P2, and P3 in its extension direction, and the second light emission control signal line EB1 is connected to pixel circuits P1, P2, and P3 in its extension direction. Since pixel circuit P4 and pixel circuit P7 are connected, the light-emitting duration of the light-emitting element connected to pixel circuit P1 is determined by the effective phase t1' of the first light-emitting control signal EMA1 transmitted by the first light-emitting control signal line EA1 and the effective phase t11' of the second light-emitting control signal EMB1 transmitted by the second light-emitting control signal line EB1. Similarly, the light-emitting duration of the remaining pixel circuits is also determined by the effective signals transmitted by the first and second light-emitting control signal lines connected to them. Pixel circuit P1, pixel circuit P4, and pixel circuit P7 are connected to the first data signal line D1 in its extension direction, and pixel circuit P1, pixel circuit P2, and pixel circuit P3 are connected to the first scan signal line S1 in its extension direction. The driving current output by pixel circuit P1 is determined by the data signal DATA1 written through the first data signal line D1 under the control of the effective phase t1 of the first scan signal SCAN1 input by the first scan signal line S1. Similarly, the driving current of the remaining pixel circuits is also determined by the effective phase of the signals transmitted by the scan signal lines and data signal lines connected to them. In some other implementations, the third direction V3 of each data signal line (D1, D2, D3) is parallel to the first direction V1.

[0046] In some alternative embodiments of the present invention, the third direction V3 intersects with the first direction V1, and the third direction V3 intersects with the second direction V2.

[0047] Specifically, the scheme of the present invention, in which the third direction V3 intersects with the first direction V1 and the second direction V2, is applicable to some irregularly shaped displays. Please refer to [reference needed]. Figure 10 , Figure 10 This is another schematic diagram illustrating the display panel for the present invention; Figure 10 It includes multiple pixel circuits, such as pixel circuit P1, pixel circuit P2, pixel circuit P3... pixel circuit P7. The pixel circuits P1, P2, P3... pixel circuit P7 are arranged in an irregular pattern. EA1, EA2, and EA3 are all first light-emitting control signal lines. EB1, EB2, and EB3 are all second light emission control signal lines. The extension direction of the first light emission control signal lines EA1, EA2, and EA3 is the first direction V1, and the extension direction of the second light emission control signal lines EB1, EB2, and EB3 is the second direction V2. D1, D2, and D3 are all data signal lines. The extension direction of each data signal line D1, D2, and D3 is the third direction V3, which intersects the first direction V1 and the second direction V2. S1, S2, and S3 are all scan signal lines. The extension direction of each scan signal line S1, S2, and S3 is the fourth direction V4. The first light emission control signal line EA1 is connected to pixel circuit P1 and pixel circuit P5 in its extension direction, and the second light emission control signal line EB1 is connected to pixel circuit P1 and pixel circuit P3 in its extension direction. Please refer to... Figure 7 , Figure 8 , Figure 9 and Figure 10 The light-emitting duration of the light-emitting element connected to pixel circuit P1 is determined by the effective phase t1' of the signal EMA1 transmitted by the first light-emitting control signal line EA1 and the effective phase t11' of the signal EMB1 transmitted by the second light-emitting control signal line EB1. Similarly, the light-emitting duration of the remaining pixel circuits is also determined by the effective signals transmitted by the first and second light-emitting control signal lines connected to them. Pixel circuits P6 and P3 are connected to the first data signal line D1 in its extension direction, and pixel circuits P6 and P7 are connected to the first scan signal line S3 in its extension direction. Therefore, the driving current output by pixel circuit P6 is determined by the data signal written through the first data signal line D1 under the control of the effective signal input by the first scan signal line S1. Similarly, the driving current of the remaining pixel circuits is also determined by the effective signals transmitted by the scan signal lines and data signal lines connected to them.

[0048] In some alternative embodiments of the present invention, the first direction V1 is parallel to the fourth direction V4, and the first direction V1 intersects the third direction V3.

[0049] Specifically, the scheme in this invention, where the first direction V1 is parallel to the fourth direction V4 and the first direction V1 intersects with the third direction V3, is also applicable to some irregularly shaped displays. Please refer to [reference needed]. Figure 11 , Figure 11 This is another schematic diagram illustrating the display panel for the present invention; Figure 11It includes multiple pixel circuits, such as pixel circuit P1, pixel circuit P2, pixel circuit P3... pixel circuit P7. The pixel circuits P1, P2, P3... pixel circuit P7 are arranged in an irregular pattern. EA1, EA2, and EA3 are all first light-emitting control signal lines. EB1, EB2, and EB3 are all second light emission control signal lines. The extension direction of the first light emission control signal lines EA1, EA2, and EA3 is the first direction V1, and the extension direction of the second light emission control signal lines EB1, EB2, and EB3 is the second direction V2. D1, D2, and D3 are all data signal lines, and the extension direction of each data signal line D1, D2, and D3 is the third direction V3. S1, S2, and S3 are all scan signal lines, and the extension direction of each scan signal line S1, S2, and S3 is the fourth direction V4. The first direction V1 and the fourth direction V4 are parallel, and the first direction V1 intersects the third direction V3. The first light emission control signal line EA1 is connected to pixel circuit P1 and pixel circuit P2 in its extension direction, and the second light emission control signal line EB2 is connected to pixel circuit P1, pixel circuit P4, and pixel circuit P7 in its extension direction. Please refer to... Figure 7 , Figure 8 , Figure 9 and Figure 10 The light-emitting duration of the light-emitting element connected to pixel circuit P1 is determined by the effective phase t1' of the signal EMA1 transmitted by the first light-emitting control signal line EA1 and the effective phase t11' of the signal EMB1 transmitted by the second light-emitting control signal line EB2. Similarly, the light-emitting duration of the remaining pixel circuits is also determined by the effective phase of the signals transmitted by the first and second light-emitting control signal lines they are connected to. Pixel circuit P3 and pixel circuit P1 are connected to the first data signal line D1 in its extension direction, and pixel circuit P1 and pixel circuit P2 are connected to the first scan signal line S1 in its extension direction. Therefore, the driving current output by pixel circuit P1 is determined by the data signal DATA1 written through the first data signal line D1 under the control of the effective phase t1 of the scan signal SCAN1 input by the first scan signal line S1. Similarly, the driving current of the remaining pixel circuits is also determined by the effective signals transmitted by the scan signal lines and data signal lines they are connected to.

[0050] Figure 12 The image shown is a schematic diagram of a display panel provided by the present invention; Figure 13 The data writing timing diagram provided for this invention.

[0051] Please combine Figure 12 and Figure 13The pixel circuit of the present invention includes a first pixel circuit group L and a second pixel circuit group B, and the scanning signal lines include a first scanning signal line S1 and a second scanning signal line S2. The first pixel circuit group L is electrically connected to the first scanning signal line S1, and the first scanning signal line S1 provides a first scanning signal SCAN1 to the first pixel circuit group L. The second pixel circuit group B is electrically connected to the second scanning signal line S2, and the second scanning signal line S2 provides a second scanning signal SCAN2 to the second pixel circuit group B. In the same display cycle, the effective phase t1 of the first scanning signal SCAN1 and the effective phase t2 of the second scanning signal SCAN2 have the same duration, and the effective phases of the first scanning signal SCAN1 and the second scanning signal SCAN2 do not overlap at least partially.

[0052] It should be noted that, Figure 12 and corresponding Figure 13 This is merely one embodiment of the present invention and is not intended to limit the pixel circuit and driving timing of the invention. For example, the first pixel circuit group A may include more or fewer pixel circuit units.

[0053] In practical applications, the pixel circuit of the present invention may further include more pixel circuit groups, each pixel circuit group being electrically connected to a corresponding scan signal line. During the same display cycle, the effective phase duration of each scan signal line is the same, and the effective phases of each scan signal line at least partially do not overlap; in some embodiments, the effective phases of each scan signal line do not overlap at all, such as... Figure 13 As shown, the effective phase t1 of the scan signal SCAN1 transmitted by the first scan signal line S1 and the effective phase t2 of the scan signal SCAN2 transmitted by the second scan signal line S2 do not overlap at all.

[0054] Please continue to refer to this. Figure 12 and Figure 13 In some optional embodiments of the present invention, the first pixel circuit group L includes a first pixel circuit P1, and the second pixel circuit group B includes a second pixel circuit P2. The first pixel circuit P1 is electrically connected to the first data signal line D1. During the valid phase t1 of the first scan signal SCAN1, the first data signal line D1 provides the first data signal DATA1 to the first pixel circuit P1. The second pixel circuit B2 is electrically connected to the second data signal line D2. During the valid phase t2 of the second scan signal SCAN2, the second data signal line D2 provides the second data signal DATA2 to the second pixel circuit B2.

[0055] Please continue to refer to this. Figure 12 and Figure 13It should be noted that the first pixel circuit group P of the present invention may include not only the first pixel circuit P1, but also the first pixel circuit P2, the first pixel circuit P3, etc.; the second pixel circuit group B may include not only the second pixel circuit B2, but also the second pixel circuit B3, the second pixel circuit B1, etc.; correspondingly, the circuit connected to the first data signal line D1 includes not only the first pixel circuit P1, but also the second pixel circuit B1; and the circuit connected to the second data signal line D2 includes not only the first pixel circuit P2, but also the second pixel circuit B2.

[0056] In practical applications, the pixel circuit of this invention may further include more pixel circuit groups. The extension direction of the data signal lines may be column-oriented. Pixel circuits located in the same column may be connected to the same data signal line, while pixel circuits located in different columns may be connected to different data signal lines. The data signal DATA transmitted by each data signal line may be the same or different depending on the actual display requirements. When the data signal DATA transmitted by each data signal line is the same, the data signal lines may share the same data signal DATA. When it is necessary to use the DATA signal to control the on / off state of the driving transistor in order to control the magnitude of the output current of the driving transistor, the data signal DATA transmitted by each data signal line may be different.

[0057] In some optional embodiments of the present invention, the first pixel circuit group L and the second pixel circuit B can each be a row of pixels; the pixel circuits in the same row use the same scan signal, and the pixel circuits in the same column use the same data signal.

[0058] In other embodiments of the present invention, the first pixel circuit group P and the second pixel circuit B may each be a pixel of the same color. The data signal lines connected to the R pixel input the same data signal, the data signal lines connected to the B pixel input the same data signal, and the data signal lines connected to the G pixel input the same data signal. RGB inputs different DATA signals according to the color. In this case, the scan signal lines connected to the R pixel use the same scan signal, the scan signal lines connected to the G pixel use the same scan signal, and the scan signal lines connected to the B pixel use the same scan signal. Each time a scan signal is input, the corresponding data is written.

[0059] Figure 14 The image shown is a schematic diagram of a display panel provided by the present invention; Figure 15 The data writing timing diagram provided for this invention; please refer to Figure 14 and Figure 15In some optional embodiments of the present invention, the pixel circuit includes a third pixel circuit group E and a fourth pixel circuit group F, and the scan signal line includes a third scan signal line S3 and a fourth scan signal line S4; the third pixel circuit group E is electrically connected to the third scan signal line S3, and the third scan signal line S3 provides a third scan signal SCAN3 to the third pixel circuit group E; the fourth pixel circuit group F is electrically connected to the fourth scan signal line S4, and the fourth scan signal line S4 provides a fourth scan signal SCAN4 to the fourth pixel circuit group F; the waveforms of the third scan signal SCAN3 and the fourth scan signal SCAN4 are the same.

[0060] It should be noted that, Figure 14 and corresponding Figure 15 This is merely one embodiment of the present invention and is not intended to limit the pixel circuit and driving timing of the invention. For example, the third pixel circuit group E and the fourth pixel circuit group F may each include more or fewer pixel circuit units. The third pixel circuit group E is not limited to one row of pixels, and the fourth pixel circuit group F is also not limited to one row of pixels. The extension direction of the scan signal line is not limited to the row direction. The fourth direction in which the scan signal line extends may be consistent with the row direction or may intersect with the row direction. Therefore, the third pixel circuit group E may include multiple pixel circuit units connected to the third scan signal line S3 along the fourth direction, and the fourth pixel circuit group F may include multiple pixel circuit units connected to the fourth scan signal line S4 along the fourth direction.

[0061] In practical applications, the pixel circuit of the present invention may also include more pixel circuit groups, each pixel circuit group being electrically connected to a corresponding scan signal line. In the same display cycle, the scan signals transmitted by each scan signal line are the same, thus saving scanning time.

[0062] Please continue to refer to this. Figure 14 and Figure 15 The third pixel circuit group E includes a third pixel circuit E3, and the fourth pixel circuit group F includes a fourth pixel circuit F4. The third pixel circuit E3 is electrically connected to the third data signal line S3. During the valid phase t3 of the third scan signal SCAN3, the third data signal line S3 provides the third data signal DATA3 to the third pixel circuit E3. The fourth pixel circuit F4 is electrically connected to the fourth data signal line S4. During the valid phase T4 of the fourth scan signal SCAN4, the fourth data signal line S4 provides the fourth data signal DATA4 to the fourth pixel circuit F4. The third data signal DATA3 and the fourth data signal DATA4 are at the same level.

[0063] Using the same scanning signal and the same data signal in the pixel scanning stage can effectively save scanning time and simplify the driving process.

[0064] Figure 16 A timing diagram of a display panel provided by the present invention is shown below in conjunction with... Figure 5 , Figure 8 , Figure 9 and Figure 16 A driving method for the display panel of the present invention will be described in detail.

[0065] Please refer to Figure 5 , Figure 5 The display panel includes multiple pixel circuits, such as pixel circuit P1, pixel circuit P2, pixel circuit P3... pixel circuit P9, where D1, D2 and D3 are data signal lines, S1, S2 and S3 are scan signal lines, EA1, EA2 and EA3 are first light emission control signal lines, and EB1, EB2 and EB3 are second light emission control signal lines.

[0066] Please combine Figure 5 and Figure 16 When driving the light-emitting element, the same scan signal SCAN can be input to scan signal lines S1, S2, and S3, and the same data signal DATA can be written to data signal lines D1, D2, and D3. Then, the first sub-light-emitting control signal EMA1 is input through the first sub-light-emitting control signal line EA1, the second sub-light-emitting control signal EMA2 is input through the second sub-light-emitting control signal line EA2, the fifth sub-light-emitting control signal EMA3 is input through the fifth sub-light-emitting control signal line EA3, the third sub-light-emitting control signal EMB1 is input through the third sub-light-emitting control signal line EB1, the fourth sub-light-emitting control signal EMB2 is input through the fourth sub-light-emitting control signal line EB2, and the sixth sub-light-emitting control signal EMA3 is input through the sixth sub-light-emitting control signal line EB3. B3; The first sub-light emission control signal EMA1 has an effective period t1', the second sub-light emission control signal EMA2 has an effective period t2', and the fifth sub-light emission control signal EMA3 has an effective period t3'. The effective periods t1', t2', and t3' are transmitted sequentially and may not overlap. The third sub-light emission control signal EMB1 has a first effective period t11', a second effective period t12', and a third effective period t13'. The fourth sub-light emission control signal EMB2 has a first effective period t21', a second effective period t22', and a third effective period t23'. The sixth sub-light emission control signal EMB3 has a first effective period t31', a second effective period t32', and a third effective period t33'.

[0067] Taking pixel circuit P1 as an example, explain the control of the light emission duration of pixel circuit P1. Please refer to... Figure 16 , Figure 5 , Figure 8 and Figure 9The first light-emitting control signal line connected to the pixel circuit P1 is the first sub-light-emitting control signal line EA1, and the second light-emitting control signal line connected to the pixel circuit P1 is the third sub-light-emitting control signal line EB1. During the effective period t1' of the first sub-light-emitting control signal EA1, the first light-emitting control module 2 of the pixel circuit P1 is in the on state; the third sub-light-emitting control signal EMB1 has a first effective period t11', and during the duration of the first effective period t11', the second light-emitting control module 3 of the pixel circuit P1 connected to the third sub-light-emitting control signal line EB1 is in the on state; because The effective period t1' of the first sub-light emission control signal EMA1 and the first effective period t11' of the third sub-light emission control signal EMB1 overlap. During the overlap period, the first light emission control module 2 and the second light emission control module 3 of the pixel circuit P1 are simultaneously in the on state. Therefore, the light emission element driven by the pixel circuit P1 emits light, and the light emission duration depends on the overlap period of the first effective period T11' and the effective period t1'. Similarly, the light emission duration of other pixel circuits also depends on the overlap period of the effective period of the first light emission control line EA and the effective period of the second light emission control line EB connected to them.

[0068] The display panel uses the same scan signal and data signal, which is suitable for driving inorganic LEDs, as inorganic LEDs are well-suited for operating under the same current intensity. Furthermore, using the same scan signal and data signal can save scanning time. It should be noted that... Figure 5 The display panel includes 9 pixel circuits, but this is only for the purpose of illustrating the technical solution, and does not mean that the panel only includes 9 pixel circuits. The purpose is to illustrate the driving method of the present invention and is not intended to limit the structure of the display panel of the present invention. In actual applications, the number of pixel circuits of the panel can be determined according to actual needs.

[0069] Please combine Figure 5 and Figure 7 or Figure 5 and Figure 16 The first light emission control signal line includes a first sub-light emission control signal line EA1 and a second sub-light emission control signal line EA2. The first sub-light emission control signal line EA1 transmits a first sub-light emission control signal EMA1, and the second sub-light emission control signal line EA2 transmits a second sub-light emission control signal EMA2. The effective period t1' of the first sub-light emission control signal EMA1 and the effective period t2' of the second sub-light emission control signal EMA2 have the same duration, and the effective periods of the first sub-light emission control signal EMA1 and the second sub-light emission control signal EMA2 do not overlap at least partially.

[0070] It should be noted that, Figure 5 and corresponding Figure 7 or Figure 16This is merely one embodiment of the present invention and is not intended to limit the pixel circuit and driving timing of the invention. In practical applications, the first light emission control signal line of the present invention may also include more sub-light emission control signal lines. In the same display cycle, the effective phase of each sub-light emission control signal line has the same duration, and the effective phases of each sub-light emission control signal line do not overlap at least partially; in some embodiments, the effective phases of each sub-light emission control signal line may not overlap at all.

[0071] Please continue to refer to this. Figure 5 , Figure 5 The pixel circuit is arranged in a three-row, three-column configuration, including the first sub-light emission control signal line EA1, the second sub-light emission control signal line EA2, and the third sub-light emission control signal line EA3. Figure 5 The first sub-light emission control signal line EA1, the second sub-light emission control signal line EA2, and the fifth sub-light emission control signal line EA3 extend in the same direction as the row direction. In some optional embodiments of the present invention, the extension directions of the first sub-light emission control signal line EA1, the second sub-light emission control signal line EA2, and the fifth sub-light emission control signal line EA3 may be different from the row direction. In some optional embodiments of the present invention, the first sub-light emission control signal line EA1, the second sub-light emission control signal line EA2, and the fifth sub-light emission control signal line EA3 may be connected to multiple pixel circuits that extend in the same direction as them.

[0072] Please refer to Figure 7 or Figure 16 , Figure 7 and Figure 16 Low to medium level is a valid signal, from Figure 7 or Figure 16 It can be seen that the effective phases t1', t2', and t3' of the first sub-light emission control signal EMA1 transmitted by the first sub-light emission control signal line EA1, the second sub-light emission control signal EMA2 transmitted by the second sub-light emission control signal line EA2, and the fifth sub-light emission control signal EMA3 transmitted by the fifth sub-light emission control signal line EA3 are completely non-overlapping. This invention adjusts the emission time of each light-emitting element by changing the signals transmitted by the first and second light emission control signal lines, and by staggering the effective phases of each first light emission control signal line, it helps simplify the setting of the signals transmitted by the second light emission control signal line.

[0073] Please continue to refer to this. Figure 5 and Figure 7 or Figure 5 and Figure 16In some optional embodiments of the present invention, the second light emission control signal line includes a third sub-light emission control signal line EB1, which provides a third sub-light emission control signal EMB1 to the pixel circuit; the pixel circuit includes a fifth pixel circuit P1, which is electrically connected to the first sub-light emission control signal line EA1 and the third sub-light emission control signal line EB1, wherein the effective phase t1' of the first sub-light emission control signal EA1 and the effective phase t11' of the third sub-light emission control signal EMB1 at least partially overlap.

[0074] It should be noted that, Figure 5 and corresponding Figure 7 or Figure 16 This is merely one embodiment of the present invention and is not intended to limit the pixel circuit and driving timing of the invention. In practical applications, the second light-emitting control signal line may also include more sub-light-emitting control signal lines, such as... Figure 5 The fourth sub-light emission control signal line EB2 and the sixth sub-light emission control signal line EB3 are shown in the diagram. During the same display cycle, the effective phase t1' of the first sub-light emission control signal EMA1 not only partially overlaps with the effective phase t11' of the third sub-light emission control signal EMB1, but also at least partially overlaps with the effective phases t12' and t13' of the signals transmitted by the fourth sub-light emission control signal line EB2 and the sixth sub-light emission control signal line EB3. Thus, the light-emitting element can only emit light when the effective phases of the signals transmitted by the first and second light emission control signal lines overlap. Furthermore, when the effective phase of the same first sub-light emission control signal EMA1 overlaps with the effective phases of signals transmitted by multiple second light emission control signal lines, the number of first sub-light emission control signals EMA1 can be reduced, simplifying the driving method.

[0075] It should be noted that in some cases, the effective phase t1' of the first sub-light emission control signal EMA1 can completely enclose the effective phase t11' of the third sub-light emission control signal EMB1. In this way, within one line of time, the third sub-light emission control signal EMB1 can completely control the light emission, which is convenient for driving.

[0076] Please continue to refer to this. Figure 7 or Figure 16 In some optional embodiments of the present invention, the third sub-light emission control signal EMB1 includes at least two effective phases T11' and T12' in the same display cycle.

[0077] Please continue to refer to this. Figure 5 , Figure 5The pixel circuits are arranged in a 3x3 grid, including a first sub-light emission control signal line EA1, a second sub-light emission control signal line EA2, and a fifth sub-light emission control signal line EA3, as well as a third sub-light emission control signal line EB1, a fourth sub-light emission control signal line EB2, and a fifth sub-light emission control signal line EB3. The three first and three second sub-light emission control signal lines interweave to form a mesh structure. Each pixel circuit is connected to one first and one second sub-light emission control signal line, and three pixel circuits are connected to the same second sub-light emission control signal line. For example, if the third sub-light emission control signal line EB1 connects to three pixel circuits, the third sub-light emission control signal line EB1 has three effective time periods t11', t12', and t13'. These three effective time periods t11', t12', and t13' of the third sub-light emission control signal line EB1 overlap with the effective time periods t1' of the first sub-light emission control signal line EA1, t2' of the second sub-light emission control signal line EA2, and t3' of the third sub-light emission control signal line EA3. Please refer to... Figure 7 , Figure 8 and Figure 9 or Figure 16 , Figure 8 and Figure 9 Under the condition of overlapping corresponding valid signals, transistors T1 and T3 in the pixel circuit connected to the third sub-light emission control signal line EB1 are all turned on, or transistors T1, T3 and T5 are all turned on. At this time, the corresponding light-emitting element 4 can emit light.

[0078] Therefore, the third sub-light emission control signal EMB1 of the present invention includes at least two effective stages t11' and t12', which enables the same second light emission control signal line to have the ability to control the light emission time of the light emission elements driven by multiple pixel circuits connected to it. Similarly, this signal setting can reduce the number of second light emission control lines, making the panel structure and driving method simpler.

[0079] It should be noted that Figure 5 The third sub-light emission control signal line EB1, the fourth sub-light emission control signal line EB2, and the sixth light emission control signal line EB3 extend in the same direction as the column direction. In some alternative embodiments of the present invention, the extension directions of the third sub-light emission control signal line EB1, the fourth sub-light emission control signal line EB2, and the sixth light emission control signal line EB3 may be different from the column direction. In some alternative embodiments of the present invention, the third sub-light emission control signal line EB1, the fourth sub-light emission control signal line EB2, and the sixth light emission control signal line EB3 may be connected to multiple pixel circuits that extend in the same direction as them.

[0080] In some optional embodiments of the present invention, the third sub-light emission control signal EMB1 includes at least two effective phases t11' and t12' with different durations.

[0081] Specifically, please refer to point 5. Figure 7 , Figure 8 and Figure 9 or Figure 5 , Figure 16 , Figure 8 and Figure 9 , Figure 7 , Figure 16 The low-to-medium level is the effective signal. In the same display cycle, the third sub-light emission control signal EMB1 includes at least two effective stages t11' and t12' with different durations, so that the third sub-light emission control signal EMB1 can perform differentiated control on the light emission time of different light-emitting elements. When the first sub-light emission control signal is the same, the light emission time of the light-emitting element depends on the third sub-light emission control signal EMB1. Therefore, by setting effective stages with different durations, differentiated control on the light emission time of different light-emitting elements can be achieved, thereby enabling different gray levels of different light-emitting elements.

[0082] In some alternative embodiments of the present invention, the third sub-light emission control signal EMB1 includes a first effective phase t11' and a second effective phase t12', the first effective phase t11' overlaps with the effective phase t1' of the first sub-light emission control signal EMA1, and the second effective phase t12' overlaps with the effective phase t2' of the second sub-light emission control signal EMA2.

[0083] Specifically, please refer to point 5. Figure 7 , Figure 8 and Figure 9 or Figure 5 , Figure 16 , Figure 8 and Figure 9 The first effective phase t11' of the third sub-light emission control signal EMB1 overlaps with the effective phase t1' of the first sub-light emission control signal EMA1, and the second effective phase t12' of the third sub-light emission control signal EMB1 overlaps with the effective phase t2' of the second sub-light emission control signal EMA2. Thus, the third sub-light emission control signal EMB1 can work collaboratively with the first sub-light emission control signal EMA1 and the second sub-light emission control signal EMA2 in the most streamlined structure to jointly control the emission time of the light-emitting element.

[0084] In some implementations, such as Figure 7As shown, the start time of the effective phase t1' of the first sub-light emission control signal EMA1 is before the start of the first effective phase t11', and the start time of the effective phase t2' of the second sub-light emission control signal EMA2 is before the start of the second effective phase t12'. Setting the start time of the effective phase t1' of the first sub-light emission control signal EMA1 before the start of the first effective phase t11' of the third sub-light emission control signal EMB1 allows the light-emitting element 4 to emit light only after the driving module 2 has stably output current, which is beneficial for the display panel to stably output the display image.

[0085] In other implementations, such as Figure 16 As shown, the effective phase t1' of the first sub-light emission control signal EMA1 starts after the start of the first effective phase t11', and the effective phase t2' of the second sub-light emission control signal EMA2 starts before the start of the second effective phase t12'. This method facilitates flexible control of the light emission duration.

[0086] Please continue to refer to this. Figure 5 and Figure 7 or Figure 5 and Figure 16 In some alternative embodiments of the present invention, the second light emission control signal line includes a fourth sub-light emission control signal line EB2, which provides a fourth sub-light emission control signal EMB2 to the pixel circuit; the duration of at least one effective phase of the fourth sub-light emission control signal EMB2 is different from the duration of at least one effective phase of the third sub-light emission control signal EMB1.

[0087] For details, please refer to Figure 7 or Figure 16 The third sub-light emission control signal EMB1 includes a first effective time period t11', a second effective time period t12', and a third effective time period t13'; the fourth sub-light emission control signal EMB2 includes a first effective time period t21', a second effective time period t22', and a third effective time period t23', wherein the first effective time period t11' of the third sub-light emission control signal EMB1 is different from the first effective time period t21', the second effective time period t22', and the third effective time period t23' of the fourth sub-light emission control signal EMB2.

[0088] Please combine Figure 7 , Figure 8 and Figure 9 or Figure 16 , Figure 8 and Figure 9When the effective period of the fourth sub-light emission control signal EMB2 is different from that of the third sub-light emission control signal EMB1, the conduction time of the third transistor T3 input to the fourth sub-light emission control signal EMB2 is different from that of the other third transistor T3 input to the fourth sub-light emission control signal EMB2, which may result in different light emission times of the corresponding light-emitting element 4.

[0089] The duration of at least one effective phase of the fourth sub-light emission control signal EMB2 is different from the duration of at least one effective phase of the third sub-light emission control signal EMB1. This allows the light-emitting element driven by the pixel circuit connected to the third sub-light emission control signal line EB1 to be different from the light-emitting element driven by the pixel circuit connected to the fourth sub-light emission control signal line EB2. This facilitates the adjustment of the light emission time of the light-emitting elements driven by different second light emission control signal lines, thereby achieving the adjustment of the grayscale of different light-emitting elements.

[0090] In some optional embodiments of the present invention, the waveforms of the fourth sub-light emission control signal EMB2 and the third sub-light emission control signal EMB1 are different.

[0091] For details, please refer to Figure 7 or Figure 16 The waveforms of the fourth sub-light emission control signal EMB2 and the third sub-light emission control signal EMB1 are different. Specifically, the pulse width, rising edge, or falling edge of each corresponding effective stage of the fourth sub-light emission control signal EMB2 and the third sub-light emission control signal EMB1 are different. By adjusting the pulse width of each effective stage contained in the fourth sub-light emission control signal EMB2 and the time when each effective stage appears, the light emission duration of the light-emitting element can also be adjusted.

[0092] Figure 17 The diagram shows a driving timing sequence for a display panel provided by this invention. Please refer to the diagram for details. Figure 5 and Figure 17 In some optional embodiments of the present invention, the first direction V1 is parallel to the fourth direction V4, and the second direction V2 is parallel to the third direction V3; in one frame period, the effective phase t1' of the first light emission control signal line is located after the end of the effective phase t1 of the first light emission control signal line and before the start of the effective phase t3 of the latest light emission control signal line.

[0093] Specifically, in an optional embodiment of the present invention, please refer to Figure 5 , Figure 5The pixel circuits shown are arranged in a 3x3 matrix. Each pixel circuit controls its corresponding light-emitting element. The signal lines include data signal lines, scan signal lines, a first light-emitting control signal line, and a second light-emitting control signal line. The data signal lines include a first data signal line D1, a second data signal line D2, and a third data signal line D3. The scan signal lines include a first scan signal line S1, a second scan signal line S2, and a third scan signal line S3. The first light-emitting control signal line includes a first sub-light-emitting control signal line EA1, a second sub-light-emitting control signal line EA2, and a fifth sub-light-emitting control signal line EA3. The second light-emitting control signal line includes a third sub-light-emitting control signal line EB1, a fourth sub-light-emitting control signal line EB2, and a sixth sub-light-emitting control signal line EB3. Each pixel circuit is electrically connected to its corresponding first and second light-emitting control signal lines.

[0094] Figure 5 In this configuration, the scanning signal line extends in the same direction as the first light-emitting control signal line, and the data signal line extends in the same direction as the first light-emitting control signal line. The pixel circuits can be divided into three groups along a first direction and three groups along a second direction. Pixel circuits arranged along the first direction and located in the same group can be electrically connected to the same scanning signal line and the same first light-emitting control signal line. Pixel circuits arranged along the first direction and located in different groups can be electrically connected to different scanning signal lines and different first light-emitting control signal lines. Pixel circuits arranged along the second direction and located in the same group can be electrically connected to the same data signal line and the same second light-emitting control signal line. Pixel circuits arranged along the second direction and located in different groups can be electrically connected to different data signal lines and different second light-emitting control signal lines.

[0095] Please refer to Figure 9Each pixel circuit includes a first sub-control module 21, a second sub-control module 22, a driving module 1, a second light-emitting control module 3, a data writing module 5, and a capacitor C. The first sub-control module 21 includes a first transistor T1, the second sub-control module 22 includes a fifth transistor T5, the driving module 1 includes a second transistor T2, the second light-emitting control module 3 includes a third transistor T3, and the data writing module 5 includes a fourth transistor T4. The source of the first transistor T1 receives a first power supply signal VDD, the drain of the first transistor T1 is electrically connected to the source of the second transistor T2, and the gate of the first transistor T1 is connected to... The first light-emitting control signal line is electrically connected and is used to transmit the first light-emitting control signal EMA; the source of the fifth transistor T5 is electrically connected to the drain of the second transistor T2, the drain of the fifth transistor T5 is electrically connected to the source of the third transistor T3, and the gate of the fifth transistor T5 is electrically connected to the first light-emitting control signal line; the drain of the third transistor T3 is electrically connected to the anode of the light-emitting element 4, and the gate of the third transistor T3 is electrically connected to the second light-emitting control signal line, which is used to transmit the second light-emitting control signal EMB; the drain of the fourth transistor T4 is connected to the gate of the second transistor T2.

[0096] Please combine Figure 5 , Figure 9 and Figure 17 Since the first light-emitting control module 2 of the present invention includes a first sub-control module 21 and a second sub-control module 22, and the second sub-control module 22 is located between the driving module 1 and the second light-emitting control module 3, its main function is to stabilize the driving current of the driving module 1, so that after the pixel circuit connected to the first scan signal line S1 has written data, and during the data writing process of other pixel circuits, the second light-emitting control module 22 of the pixel circuit connected to the first scan signal line S1 can be in a conducting state. Please continue to refer to Figure 17 The display panel of the present invention can be driven as follows: Data is written to the connected pixel circuit sequentially through the first scan signal line S1, the second scan signal line S2, and the third scan signal line S3. 2) After data is written through the first scan signal line S1, the first sub-control module 21 and the second sub-control module 22 connected to it are turned on sequentially through the first sub-light emission control signal line EA1, the second sub-light emission control signal line EA2 and the fifth sub-light emission control signal line EA3. At any given time, only the first light emission control module 21 and the second sub-control module 22 connected by one of the first light emission control lines are in the on state. The second light emission control module 3 is turned on through the third sub-light emission control signal line EB1, the fourth sub-light emission control signal line EB2 and the sixth sub-light emission control signal line EB3. The light emission elements driven by the pixel circuits of the first sub-control module 21, the second sub-control module 22 and the second light emission control module 3, which are in the on state at the same time, emit light.

[0097] Based on the same inventive concept, the present invention also provides a display device, please refer to [reference needed]. Figure 18 , Figure 18 The diagram shown is a structural schematic of a display device provided by the present invention. The display device 200 provided in this embodiment includes the display panel 100 provided in any of the above embodiments of the present invention.

[0098] It is understood that the display device 200 provided in the embodiments of the present invention can be a computer, mobile phone, tablet, or other display device with display function, and the present invention does not impose specific limitations on it. The display device provided in the embodiments of the present invention has the beneficial effects of the display panel provided in the embodiments of the present invention. For details, please refer to the specific descriptions of the display panel in the above embodiments, which will not be repeated here.

[0099] In summary, the display panel and display device provided by the present invention achieve at least the following beneficial effects: First, this invention employs a first light-emitting control module and a second light-emitting control module to jointly control the light-emitting duration of the light-emitting element. The control signals from the first and second light-emitting control modules can be transmitted via first and second light-emitting control signal lines, respectively. Therefore, the grayscale of each pixel can be adjusted by changing the control signals transmitted through the first and second light-emitting control signal lines. Furthermore, the first and second light-emitting control signal lines are intersecting, forming a grid-like control structure. This helps to reduce the number of first and second light-emitting control signal lines, resulting in simple control and a simple structure, which contributes to high ppi (Pixels Per Pixel). The invention implements the following: First, the grayscale of the light-emitting element can be adjusted by adjusting the light-emitting time of the light-emitting element, and the grayscale can also be adjusted by controlling the output current of the driving module through the data writing module. In this way, the grayscale of the light-emitting element can be adjusted from two dimensions: light-emitting time and light-emitting intensity. The number of grayscale adjustment levels can be increased, and the presented image will be more delicate. Second, the first light-emitting control module of the invention includes a first sub-control module 21 and a second sub-control module 22. The second sub-control module 22 is located between the driving module 1 and the second light-emitting control module 3. Its main function is to stabilize the driving current of the driving module 1, so that after the data writing of the pixel circuit of this row, the second light-emitting control module 3 of the pixel circuit of this row can be in the conducting state during the data writing process of other pixel circuits. Compared with existing related technologies, the present invention can advance the light emission stage of the light-emitting element 4 by setting a second sub-control module 22; furthermore, the present invention uses the same scanning signal and the same data signal in the pixel scanning stage, which can effectively save scanning time and simplify the driving process; finally, the present invention has overlapping effective stages of the same first sub-light emission control signal EMA1 with the effective stages of signals transmitted by multiple second light emission control signal lines, the third sub-light emission control signal EMB1 includes at least two effective stages, the third sub-light emission control signal EMB1 includes at least two effective stages with different durations, and the duration of at least one effective stage of the fourth sub-light emission control signal EMB2 is different from the duration of at least one effective stage of the third sub-light emission control signal EMB1, which can reduce the number of signal lines and achieve adjustment of the light emission time of each pixel, and the structure and driving method of the display panel are more streamlined.

[0100] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, characterized in that, Includes pixel circuitry, light-emitting elements, and signal lines; The pixel circuit is electrically connected to the light-emitting element, and the pixel circuit includes a driving module, a first light-emitting control module, and a second light-emitting control module. The driving module is used to drive the light-emitting element to emit light; The first light-emitting control module and the second light-emitting control module are used to jointly control the light-emitting duration of the light-emitting element; The signal lines include a first light-emitting control signal line and a second light-emitting control signal line. The first light-emitting control module is electrically connected to the first light-emitting control signal line. The first light-emitting control signal line extends along a first direction, which is parallel to the plane of the display panel. The second light-emitting control module is connected to the second light-emitting control signal line. The second light-emitting control signal line extends along a second direction, which is parallel to the plane of the display panel. The first direction and the second direction intersect.

2. The display panel according to claim 1, characterized in that, The pixel circuit also includes a data writing module, which is used to transmit data signals to the control terminal of the driving module.

3. The display panel according to claim 2, characterized in that, The first light-emitting control module includes a first sub-control module. The first end of the first sub-control module is used to receive a first power signal. The second end of the first sub-control module is electrically connected to the first end of the driving module. The control end of the first sub-control module is electrically connected to the first light-emitting control signal line. The first end of the second light-emitting control module is electrically connected to the driving module, the second end of the second light-emitting control module is electrically connected to the light-emitting element, and the control end of the second light-emitting control module is electrically connected to the second light-emitting control signal line.

4. The display panel according to claim 3, characterized in that, The first light-emitting control module further includes a second sub-control module, which is located between the driving module and the second light-emitting control module. The first end of the second sub-control module is electrically connected to the second end of the driving module, the second end of the second sub-control module is electrically connected to the first end of the second light-emitting control module, and the control end of the second sub-control module is electrically connected to the first light-emitting control signal line.

5. The display panel according to claim 2, characterized in that, The pixel circuit includes a capacitor, the first plate of which is electrically connected to the control terminal of the driving module, and the second plate of which is electrically connected to a first fixed potential line.

6. The display panel according to claim 2, characterized in that, The first end of the data writing module is electrically connected to the data signal line, which extends along a third direction and is parallel to the plane where the display panel is located. The control terminal of the data writing module is electrically connected to the scanning signal line, which extends along a fourth direction. The fourth direction is parallel to the plane where the display panel is located, and the third direction intersects the fourth direction.

7. The display panel according to claim 6, characterized in that, The third direction is parallel to the first direction; or, the third direction is parallel to the second direction.

8. The display panel according to claim 6, characterized in that, The third direction intersects with the first direction, and the third direction intersects with the second direction.

9. The display panel according to claim 6, characterized in that, The first direction is parallel to the fourth direction, and the first direction intersects with the third direction.

10. The display panel according to claim 2, characterized in that, The pixel circuit includes a first pixel circuit group and a second pixel circuit group. The control terminal of the data writing module is electrically connected to the scan signal line. The scan signal line includes a first scan signal line and a second scan signal line. The first pixel circuit group is electrically connected to the first scan signal line, and the first scan signal line provides a first scan signal to the first pixel circuit group; the second pixel circuit group is electrically connected to the second scan signal line, and the second scan signal line provides a second scan signal to the second pixel circuit group. In the same display cycle, the effective phases of the first scan signal and the second scan signal have the same duration, and the effective phases of the first scan signal and the second scan signal do not overlap at least partially.

11. The display panel according to claim 10, characterized in that, The first pixel circuit group includes a first pixel circuit, and the second pixel circuit group includes a second pixel circuit. The first pixel circuit is electrically connected to a first data signal line. During the valid phase of the first scan signal, the first data signal line provides a first data signal to the first pixel circuit. The second pixel circuit is electrically connected to the second data signal line. During the valid phase of the second scan signal, the second data signal line provides the second data signal to the second pixel circuit.

12. The display panel according to claim 2, characterized in that, The pixel circuit includes a third pixel circuit group and a fourth pixel circuit group. The control terminal of the data writing module is electrically connected to the scan signal line, and the scan signal line includes a third scan signal line and a fourth scan signal line. The third pixel circuit group is electrically connected to the third scan signal line, and the third scan signal line provides a third scan signal to the third pixel circuit group; the fourth pixel circuit group is electrically connected to the fourth scan signal line, and the fourth scan signal line provides a fourth scan signal to the fourth pixel circuit group; The waveforms of the third scan signal and the fourth scan signal are the same.

13. The display panel according to claim 12, characterized in that, The third pixel circuit group includes a third pixel circuit, the fourth pixel circuit group includes a fourth pixel circuit, the third pixel circuit is electrically connected to the third data signal line, and during the valid phase of the third scan signal, the third data signal line provides a third data signal to the third pixel circuit; The fourth pixel circuit is electrically connected to the fourth data signal line. During the effective phase of the fourth scan signal, the fourth data signal line provides a fourth data signal to the fourth pixel circuit. The third data signal and the fourth data signal are signals with the same level.

14. The display panel according to claim 1, characterized in that, The first light emission control signal line includes a first sub-light emission control signal line and a second sub-light emission control signal line. The first sub-light emission control signal line transmits a first sub-light emission control signal, and the second sub-light emission control signal line transmits a second sub-light emission control signal. The effective periods of the first sub-light emission control signal and the second sub-light emission control signal are of the same duration, and the effective periods of the first sub-light emission control signal and the second sub-light emission control signal do not overlap at least partially.

15. The display panel according to claim 14, characterized in that, The second light emission control signal line includes a third sub-light emission control signal line, which provides a third sub-light emission control signal to the pixel circuit; The pixel circuit includes a fifth pixel circuit, which is electrically connected to the first sub-light emission control signal line and the third sub-light emission control signal line, wherein the effective phase of the first sub-light emission control signal and the effective phase of the third sub-light emission control signal at least partially overlap.

16. The display panel according to claim 15, characterized in that, Within the same display cycle, the third sub-light emission control signal includes at least two effective phases.

17. The display panel according to claim 16, characterized in that, The third sub-light emission control signal includes at least two effective phases with different durations.

18. The display panel according to claim 16, characterized in that, The third sub-light emission control signal includes a first effective phase and a second effective phase, wherein the first effective phase overlaps with the effective phase of the first sub-light emission control signal, and the second effective phase overlaps with the effective phase of the second sub-light emission control signal.

19. The display panel according to claim 15, characterized in that, The second light emission control signal line includes a fourth sub-light emission control signal line, which provides a fourth sub-light emission control signal to the pixel circuit; The duration of at least one effective phase of the fourth sub-light emission control signal is different from the duration of at least one effective phase of the third sub-light emission control signal.

20. The display panel according to claim 19, characterized in that, The waveform of the fourth sub-light emission control signal is different from that of the third sub-light emission control signal.

21. The display panel according to claim 6, characterized in that, The first direction is parallel to the fourth direction, and the second direction is parallel to the third direction; In one frame period, the first effective phase of the first light emission control signal line is after the end of the first effective phase of the scan signal line and before the start of the last effective phase of the scan signal line.

22. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 21.

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